1 //===---------------------------------------------------------------------===//
2 // Random notes about and ideas for the SystemZ backend.
3 //===---------------------------------------------------------------------===//
5 The initial backend is deliberately restricted to z10. We should add support
6 for later architectures at some point.
10 SystemZDAGToDAGISel::SelectInlineAsmMemoryOperand() is passed "m" for all
11 inline asm memory constraints; it doesn't get to see the original constraint.
12 This means that it must conservatively treat all inline asm constraints
13 as the most restricted type, "R".
17 If an inline asm ties an i32 "r" result to an i64 input, the input
18 will be treated as an i32, leaving the upper bits uninitialised.
21 define void @f4(i32 *%dst) {
22 %val = call i32 asm "blah $0", "=r,0" (i64 103)
23 store i32 %val, i32 *%dst
27 from CodeGen/SystemZ/asm-09.ll will use LHI rather than LGHI.
28 to load 103. This seems to be a general target-independent problem.
32 The tuning of the choice between LOAD ADDRESS (LA) and addition in
33 SystemZISelDAGToDAG.cpp is suspect. It should be tweaked based on
34 performance measurements.
38 We don't support prefetching yet.
42 There is no scheduling support.
46 We don't use the BRANCH ON INDEX instructions.
50 We might want to use BRANCH ON CONDITION for conditional indirect calls
51 and conditional returns.
55 We don't use the TEST DATA CLASS instructions.
59 We could use the generic floating-point forms of LOAD COMPLEMENT,
60 LOAD NEGATIVE and LOAD POSITIVE in cases where we don't need the
61 condition codes. For example, we could use LCDFR instead of LCDBR.
65 We don't optimize block memory operations, except using single MVCs
66 for memcpy and single CLCs for memcmp.
68 It's definitely worth using things like NC, XC and OC with
69 constant lengths. MVCIN may be worthwhile too.
71 We should probably implement general memcpy using MVC with EXECUTE.
72 Likewise memcmp and CLC. MVCLE and CLCLE could be useful too.
76 We don't optimize string operations.
78 MVST, CLST, SRST and CUSE could be useful here. Some of the TRANSLATE
79 family might be too, although they are probably more difficult to exploit.
83 We don't take full advantage of builtins like fabsl because the calling
84 conventions require f128s to be returned by invisible reference.
88 ADD LOGICAL WITH SIGNED IMMEDIATE could be useful when we need to
89 produce a carry. SUBTRACT LOGICAL IMMEDIATE could be useful when we
90 need to produce a borrow. (Note that there are no memory forms of
91 ADD LOGICAL WITH CARRY and SUBTRACT LOGICAL WITH BORROW, so the high
92 part of 128-bit memory operations would probably need to be done
97 We don't use the halfword forms of LOAD REVERSED and STORE REVERSED
102 We could take advantage of the various ... UNDER MASK instructions,
103 such as ICM and STCM.
107 DAGCombiner doesn't yet fold truncations of extended loads. Functions like:
109 unsigned long f (unsigned long x, unsigned short *y)
111 return (x << 32) | *y;
121 but truncating the load would give:
131 define i64 @f1(i64 %a) {
136 ought to be implemented as:
142 but two-address optimisations reverse the order of the AND and force:
149 CodeGen/SystemZ/and-04.ll has several examples of this.
153 Out-of-range displacements are usually handled by loading the full
154 address into a register. In many cases it would be better to create
155 an anchor point instead. E.g. for:
157 define void @f4a(i128 *%aptr, i64 %base) {
158 %addr = add i64 %base, 524288
159 %bptr = inttoptr i64 %addr to i128 *
160 %a = load volatile i128 *%aptr
161 %b = load i128 *%bptr
162 %add = add i128 %a, %b
163 store i128 %add, i128 *%aptr
167 (from CodeGen/SystemZ/int-add-08.ll) we load %base+524288 and %base+524296
168 into separate registers, rather than using %base+524288 as a base for both.
172 Dynamic stack allocations round the size to 8 bytes and then allocate
173 that rounded amount. It would be simpler to subtract the unrounded
174 size from the copy of the stack pointer and then align the result.
175 See CodeGen/SystemZ/alloca-01.ll for an example.
179 Atomic loads and stores use the default compare-and-swap based implementation.
180 This is much too conservative in practice, since the architecture guarantees
181 that 1-, 2-, 4- and 8-byte loads and stores to aligned addresses are
186 If needed, we can support 16-byte atomics using LPQ, STPQ and CSDG.
190 We might want to model all access registers and use them to spill