1 //===-- SystemZ.td - Describe the SystemZ target machine -----*- tblgen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Target-independent interfaces which we are implementing
12 //===----------------------------------------------------------------------===//
14 include "llvm/Target/Target.td"
16 //===----------------------------------------------------------------------===//
17 // SystemZ supported processors
18 //===----------------------------------------------------------------------===//
20 class Proc<string Name, list<SubtargetFeature> Features>
21 : Processor<Name, NoItineraries, Features>;
23 def : Proc<"z10", []>;
25 //===----------------------------------------------------------------------===//
26 // Register file description
27 //===----------------------------------------------------------------------===//
29 include "SystemZRegisterInfo.td"
31 //===----------------------------------------------------------------------===//
32 // Calling convention description
33 //===----------------------------------------------------------------------===//
35 include "SystemZCallingConv.td"
37 //===----------------------------------------------------------------------===//
38 // Instruction descriptions
39 //===----------------------------------------------------------------------===//
41 include "SystemZOperators.td"
42 include "SystemZOperands.td"
43 include "SystemZPatterns.td"
44 include "SystemZInstrFormats.td"
45 include "SystemZInstrInfo.td"
46 include "SystemZInstrFP.td"
48 def SystemZInstrInfo : InstrInfo {}
50 //===----------------------------------------------------------------------===//
52 //===----------------------------------------------------------------------===//
54 def SystemZAsmParser : AsmParser {
55 let ShouldEmitMatchRegisterName = 0;
58 //===----------------------------------------------------------------------===//
60 //===----------------------------------------------------------------------===//
62 def SystemZAsmWriter : AsmWriter {
63 string AsmWriterClassName = "InstPrinter";
64 bit isMCAsmWriter = 1;
67 //===----------------------------------------------------------------------===//
68 // Top-level target declaration
69 //===----------------------------------------------------------------------===//
71 def SystemZ : Target {
72 let InstructionSet = SystemZInstrInfo;
73 let AssemblyParsers = [SystemZAsmParser];
74 let AssemblyWriters = [SystemZAsmWriter];