1 //===-- SystemZFrameLowering.cpp - Frame lowering for SystemZ -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "SystemZFrameLowering.h"
11 #include "SystemZCallingConv.h"
12 #include "SystemZInstrBuilder.h"
13 #include "SystemZInstrInfo.h"
14 #include "SystemZMachineFunctionInfo.h"
15 #include "SystemZRegisterInfo.h"
16 #include "SystemZSubtarget.h"
17 #include "llvm/CodeGen/MachineModuleInfo.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/CodeGen/RegisterScavenging.h"
20 #include "llvm/IR/Function.h"
25 // The ABI-defined register save slots, relative to the incoming stack
27 static const TargetFrameLowering::SpillSlot SpillOffsetTable[] = {
28 { SystemZ::R2D, 0x10 },
29 { SystemZ::R3D, 0x18 },
30 { SystemZ::R4D, 0x20 },
31 { SystemZ::R5D, 0x28 },
32 { SystemZ::R6D, 0x30 },
33 { SystemZ::R7D, 0x38 },
34 { SystemZ::R8D, 0x40 },
35 { SystemZ::R9D, 0x48 },
36 { SystemZ::R10D, 0x50 },
37 { SystemZ::R11D, 0x58 },
38 { SystemZ::R12D, 0x60 },
39 { SystemZ::R13D, 0x68 },
40 { SystemZ::R14D, 0x70 },
41 { SystemZ::R15D, 0x78 },
42 { SystemZ::F0D, 0x80 },
43 { SystemZ::F2D, 0x88 },
44 { SystemZ::F4D, 0x90 },
45 { SystemZ::F6D, 0x98 }
47 } // end anonymous namespace
49 SystemZFrameLowering::SystemZFrameLowering()
50 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 8,
51 -SystemZMC::CallFrameSize, 8) {
52 // Create a mapping from register number to save slot offset.
53 RegSpillOffsets.grow(SystemZ::NUM_TARGET_REGS);
54 for (unsigned I = 0, E = array_lengthof(SpillOffsetTable); I != E; ++I)
55 RegSpillOffsets[SpillOffsetTable[I].Reg] = SpillOffsetTable[I].Offset;
58 const TargetFrameLowering::SpillSlot *
59 SystemZFrameLowering::getCalleeSavedSpillSlots(unsigned &NumEntries) const {
60 NumEntries = array_lengthof(SpillOffsetTable);
61 return SpillOffsetTable;
64 void SystemZFrameLowering::
65 processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
66 RegScavenger *RS) const {
67 MachineFrameInfo *MFFrame = MF.getFrameInfo();
68 MachineRegisterInfo &MRI = MF.getRegInfo();
69 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
70 bool HasFP = hasFP(MF);
71 SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>();
72 bool IsVarArg = MF.getFunction()->isVarArg();
74 // va_start stores incoming FPR varargs in the normal way, but delegates
75 // the saving of incoming GPR varargs to spillCalleeSavedRegisters().
76 // Record these pending uses, which typically include the call-saved
77 // argument register R6D.
79 for (unsigned I = MFI->getVarArgsFirstGPR(); I < SystemZ::NumArgGPRs; ++I)
80 MRI.setPhysRegUsed(SystemZ::ArgGPRs[I]);
82 // If the function requires a frame pointer, record that the hard
83 // frame pointer will be clobbered.
85 MRI.setPhysRegUsed(SystemZ::R11D);
87 // If the function calls other functions, record that the return
88 // address register will be clobbered.
89 if (MFFrame->hasCalls())
90 MRI.setPhysRegUsed(SystemZ::R14D);
92 // If we are saving GPRs other than the stack pointer, we might as well
93 // save and restore the stack pointer at the same time, via STMG and LMG.
94 // This allows the deallocation to be done by the LMG, rather than needing
95 // a separate %r15 addition.
96 const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
97 for (unsigned I = 0; CSRegs[I]; ++I) {
98 unsigned Reg = CSRegs[I];
99 if (SystemZ::GR64BitRegClass.contains(Reg) && MRI.isPhysRegUsed(Reg)) {
100 MRI.setPhysRegUsed(SystemZ::R15D);
106 // Add GPR64 to the save instruction being built by MIB, which is in basic
107 // block MBB. IsImplicit says whether this is an explicit operand to the
108 // instruction, or an implicit one that comes between the explicit start
109 // and end registers.
110 static void addSavedGPR(MachineBasicBlock &MBB, MachineInstrBuilder &MIB,
111 unsigned GPR64, bool IsImplicit) {
112 const TargetRegisterInfo *RI =
113 MBB.getParent()->getSubtarget().getRegisterInfo();
114 unsigned GPR32 = RI->getSubReg(GPR64, SystemZ::subreg_l32);
115 bool IsLive = MBB.isLiveIn(GPR64) || MBB.isLiveIn(GPR32);
116 if (!IsLive || !IsImplicit) {
117 MIB.addReg(GPR64, getImplRegState(IsImplicit) | getKillRegState(!IsLive));
119 MBB.addLiveIn(GPR64);
123 bool SystemZFrameLowering::
124 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
125 MachineBasicBlock::iterator MBBI,
126 const std::vector<CalleeSavedInfo> &CSI,
127 const TargetRegisterInfo *TRI) const {
131 MachineFunction &MF = *MBB.getParent();
132 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
133 SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>();
134 bool IsVarArg = MF.getFunction()->isVarArg();
135 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
137 // Scan the call-saved GPRs and find the bounds of the register spill area.
139 unsigned HighGPR = SystemZ::R15D;
140 unsigned StartOffset = -1U;
141 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
142 unsigned Reg = CSI[I].getReg();
143 if (SystemZ::GR64BitRegClass.contains(Reg)) {
144 unsigned Offset = RegSpillOffsets[Reg];
145 assert(Offset && "Unexpected GPR save");
146 if (StartOffset > Offset) {
148 StartOffset = Offset;
153 // Save the range of call-saved registers, for use by the epilogue inserter.
154 ZFI->setLowSavedGPR(LowGPR);
155 ZFI->setHighSavedGPR(HighGPR);
157 // Include the GPR varargs, if any. R6D is call-saved, so would
158 // be included by the loop above, but we also need to handle the
159 // call-clobbered argument registers.
161 unsigned FirstGPR = ZFI->getVarArgsFirstGPR();
162 if (FirstGPR < SystemZ::NumArgGPRs) {
163 unsigned Reg = SystemZ::ArgGPRs[FirstGPR];
164 unsigned Offset = RegSpillOffsets[Reg];
165 if (StartOffset > Offset) {
166 LowGPR = Reg; StartOffset = Offset;
173 assert(LowGPR != HighGPR && "Should be saving %r15 and something else");
175 // Build an STMG instruction.
176 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::STMG));
178 // Add the explicit register operands.
179 addSavedGPR(MBB, MIB, LowGPR, false);
180 addSavedGPR(MBB, MIB, HighGPR, false);
183 MIB.addReg(SystemZ::R15D).addImm(StartOffset);
185 // Make sure all call-saved GPRs are included as operands and are
186 // marked as live on entry.
187 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
188 unsigned Reg = CSI[I].getReg();
189 if (SystemZ::GR64BitRegClass.contains(Reg))
190 addSavedGPR(MBB, MIB, Reg, true);
193 // ...likewise GPR varargs.
195 for (unsigned I = ZFI->getVarArgsFirstGPR(); I < SystemZ::NumArgGPRs; ++I)
196 addSavedGPR(MBB, MIB, SystemZ::ArgGPRs[I], true);
199 // Save FPRs in the normal TargetInstrInfo way.
200 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
201 unsigned Reg = CSI[I].getReg();
202 if (SystemZ::FP64BitRegClass.contains(Reg)) {
204 TII->storeRegToStackSlot(MBB, MBBI, Reg, true, CSI[I].getFrameIdx(),
205 &SystemZ::FP64BitRegClass, TRI);
212 bool SystemZFrameLowering::
213 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
214 MachineBasicBlock::iterator MBBI,
215 const std::vector<CalleeSavedInfo> &CSI,
216 const TargetRegisterInfo *TRI) const {
220 MachineFunction &MF = *MBB.getParent();
221 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
222 SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>();
223 bool HasFP = hasFP(MF);
224 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
226 // Restore FPRs in the normal TargetInstrInfo way.
227 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
228 unsigned Reg = CSI[I].getReg();
229 if (SystemZ::FP64BitRegClass.contains(Reg))
230 TII->loadRegFromStackSlot(MBB, MBBI, Reg, CSI[I].getFrameIdx(),
231 &SystemZ::FP64BitRegClass, TRI);
234 // Restore call-saved GPRs (but not call-clobbered varargs, which at
235 // this point might hold return values).
236 unsigned LowGPR = ZFI->getLowSavedGPR();
237 unsigned HighGPR = ZFI->getHighSavedGPR();
238 unsigned StartOffset = RegSpillOffsets[LowGPR];
240 // If we saved any of %r2-%r5 as varargs, we should also be saving
241 // and restoring %r6. If we're saving %r6 or above, we should be
243 assert(LowGPR != HighGPR && "Should be loading %r15 and something else");
245 // Build an LMG instruction.
246 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::LMG));
248 // Add the explicit register operands.
249 MIB.addReg(LowGPR, RegState::Define);
250 MIB.addReg(HighGPR, RegState::Define);
253 MIB.addReg(HasFP ? SystemZ::R11D : SystemZ::R15D);
254 MIB.addImm(StartOffset);
256 // Do a second scan adding regs as being defined by instruction
257 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
258 unsigned Reg = CSI[I].getReg();
259 if (Reg != LowGPR && Reg != HighGPR)
260 MIB.addReg(Reg, RegState::ImplicitDefine);
267 void SystemZFrameLowering::
268 processFunctionBeforeFrameFinalized(MachineFunction &MF,
269 RegScavenger *RS) const {
270 MachineFrameInfo *MFFrame = MF.getFrameInfo();
271 uint64_t MaxReach = (MFFrame->estimateStackSize(MF) +
272 SystemZMC::CallFrameSize * 2);
273 if (!isUInt<12>(MaxReach)) {
274 // We may need register scavenging slots if some parts of the frame
275 // are outside the reach of an unsigned 12-bit displacement.
276 // Create 2 for the case where both addresses in an MVC are
278 RS->addScavengingFrameIndex(MFFrame->CreateStackObject(8, 8, false));
279 RS->addScavengingFrameIndex(MFFrame->CreateStackObject(8, 8, false));
283 // Emit instructions before MBBI (in MBB) to add NumBytes to Reg.
284 static void emitIncrement(MachineBasicBlock &MBB,
285 MachineBasicBlock::iterator &MBBI,
287 unsigned Reg, int64_t NumBytes,
288 const TargetInstrInfo *TII) {
291 int64_t ThisVal = NumBytes;
292 if (isInt<16>(NumBytes))
293 Opcode = SystemZ::AGHI;
295 Opcode = SystemZ::AGFI;
296 // Make sure we maintain 8-byte stack alignment.
297 int64_t MinVal = -uint64_t(1) << 31;
298 int64_t MaxVal = (int64_t(1) << 31) - 8;
299 if (ThisVal < MinVal)
301 else if (ThisVal > MaxVal)
304 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII->get(Opcode), Reg)
305 .addReg(Reg).addImm(ThisVal);
306 // The CC implicit def is dead.
307 MI->getOperand(3).setIsDead();
312 void SystemZFrameLowering::emitPrologue(MachineFunction &MF,
313 MachineBasicBlock &MBB) const {
314 assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
315 MachineFrameInfo *MFFrame = MF.getFrameInfo();
317 static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
318 SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>();
319 MachineBasicBlock::iterator MBBI = MBB.begin();
320 MachineModuleInfo &MMI = MF.getMMI();
321 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
322 const std::vector<CalleeSavedInfo> &CSI = MFFrame->getCalleeSavedInfo();
323 bool HasFP = hasFP(MF);
324 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
326 // The current offset of the stack pointer from the CFA.
327 int64_t SPOffsetFromCFA = -SystemZMC::CFAOffsetFromInitialSP;
329 if (ZFI->getLowSavedGPR()) {
330 // Skip over the GPR saves.
331 if (MBBI != MBB.end() && MBBI->getOpcode() == SystemZ::STMG)
334 llvm_unreachable("Couldn't skip over GPR saves");
336 // Add CFI for the GPR saves.
337 for (auto &Save : CSI) {
338 unsigned Reg = Save.getReg();
339 if (SystemZ::GR64BitRegClass.contains(Reg)) {
340 int64_t Offset = SPOffsetFromCFA + RegSpillOffsets[Reg];
341 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
342 nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
343 BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
344 .addCFIIndex(CFIIndex);
349 uint64_t StackSize = getAllocatedStackSize(MF);
351 // Allocate StackSize bytes.
352 int64_t Delta = -int64_t(StackSize);
353 emitIncrement(MBB, MBBI, DL, SystemZ::R15D, Delta, ZII);
355 // Add CFI for the allocation.
356 unsigned CFIIndex = MMI.addFrameInst(
357 MCCFIInstruction::createDefCfaOffset(nullptr, SPOffsetFromCFA + Delta));
358 BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
359 .addCFIIndex(CFIIndex);
360 SPOffsetFromCFA += Delta;
364 // Copy the base of the frame to R11.
365 BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::LGR), SystemZ::R11D)
366 .addReg(SystemZ::R15D);
368 // Add CFI for the new frame location.
369 unsigned HardFP = MRI->getDwarfRegNum(SystemZ::R11D, true);
370 unsigned CFIIndex = MMI.addFrameInst(
371 MCCFIInstruction::createDefCfaRegister(nullptr, HardFP));
372 BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
373 .addCFIIndex(CFIIndex);
375 // Mark the FramePtr as live at the beginning of every block except
376 // the entry block. (We'll have marked R11 as live on entry when
378 for (auto I = std::next(MF.begin()), E = MF.end(); I != E; ++I)
379 I->addLiveIn(SystemZ::R11D);
382 // Skip over the FPR saves.
383 SmallVector<unsigned, 8> CFIIndexes;
384 for (auto &Save : CSI) {
385 unsigned Reg = Save.getReg();
386 if (SystemZ::FP64BitRegClass.contains(Reg)) {
387 if (MBBI != MBB.end() &&
388 (MBBI->getOpcode() == SystemZ::STD ||
389 MBBI->getOpcode() == SystemZ::STDY))
392 llvm_unreachable("Couldn't skip over FPR save");
394 // Add CFI for the this save.
395 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
396 int64_t Offset = getFrameIndexOffset(MF, Save.getFrameIdx());
397 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
398 nullptr, DwarfReg, SPOffsetFromCFA + Offset));
399 CFIIndexes.push_back(CFIIndex);
402 // Complete the CFI for the FPR saves, modelling them as taking effect
403 // after the last save.
404 for (auto CFIIndex : CFIIndexes) {
405 BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
406 .addCFIIndex(CFIIndex);
410 void SystemZFrameLowering::emitEpilogue(MachineFunction &MF,
411 MachineBasicBlock &MBB) const {
412 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
414 static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
415 SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>();
417 // Skip the return instruction.
418 assert(MBBI->isReturn() && "Can only insert epilogue into returning blocks");
420 uint64_t StackSize = getAllocatedStackSize(MF);
421 if (ZFI->getLowSavedGPR()) {
423 unsigned Opcode = MBBI->getOpcode();
424 if (Opcode != SystemZ::LMG)
425 llvm_unreachable("Expected to see callee-save register restore code");
427 unsigned AddrOpNo = 2;
428 DebugLoc DL = MBBI->getDebugLoc();
429 uint64_t Offset = StackSize + MBBI->getOperand(AddrOpNo + 1).getImm();
430 unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset);
432 // If the offset is too large, use the largest stack-aligned offset
433 // and add the rest to the base register (the stack or frame pointer).
435 uint64_t NumBytes = Offset - 0x7fff8;
436 emitIncrement(MBB, MBBI, DL, MBBI->getOperand(AddrOpNo).getReg(),
439 NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset);
440 assert(NewOpcode && "No restore instruction available");
443 MBBI->setDesc(ZII->get(NewOpcode));
444 MBBI->getOperand(AddrOpNo + 1).ChangeToImmediate(Offset);
445 } else if (StackSize) {
446 DebugLoc DL = MBBI->getDebugLoc();
447 emitIncrement(MBB, MBBI, DL, SystemZ::R15D, StackSize, ZII);
451 bool SystemZFrameLowering::hasFP(const MachineFunction &MF) const {
452 return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
453 MF.getFrameInfo()->hasVarSizedObjects() ||
454 MF.getInfo<SystemZMachineFunctionInfo>()->getManipulatesSP());
457 int SystemZFrameLowering::getFrameIndexOffset(const MachineFunction &MF,
459 const MachineFrameInfo *MFFrame = MF.getFrameInfo();
461 // Start with the offset of FI from the top of the caller-allocated frame
462 // (i.e. the top of the 160 bytes allocated by the caller). This initial
463 // offset is therefore negative.
464 int64_t Offset = (MFFrame->getObjectOffset(FI) +
465 MFFrame->getOffsetAdjustment());
467 // Make the offset relative to the incoming stack pointer.
468 Offset -= getOffsetOfLocalArea();
470 // Make the offset relative to the bottom of the frame.
471 Offset += getAllocatedStackSize(MF);
476 uint64_t SystemZFrameLowering::
477 getAllocatedStackSize(const MachineFunction &MF) const {
478 const MachineFrameInfo *MFFrame = MF.getFrameInfo();
480 // Start with the size of the local variables and spill slots.
481 uint64_t StackSize = MFFrame->getStackSize();
483 // We need to allocate the ABI-defined 160-byte base area whenever
484 // we allocate stack space for our own use and whenever we call another
486 if (StackSize || MFFrame->hasVarSizedObjects() || MFFrame->hasCalls())
487 StackSize += SystemZMC::CallFrameSize;
493 SystemZFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
494 // The ABI requires us to allocate 160 bytes of stack space for the callee,
495 // with any outgoing stack arguments being placed above that. It seems
496 // better to make that area a permanent feature of the frame even if
497 // we're using a frame pointer.
501 void SystemZFrameLowering::
502 eliminateCallFramePseudoInstr(MachineFunction &MF,
503 MachineBasicBlock &MBB,
504 MachineBasicBlock::iterator MI) const {
505 switch (MI->getOpcode()) {
506 case SystemZ::ADJCALLSTACKDOWN:
507 case SystemZ::ADJCALLSTACKUP:
508 assert(hasReservedCallFrame(MF) &&
509 "ADJSTACKDOWN and ADJSTACKUP should be no-ops");
514 llvm_unreachable("Unexpected call frame instruction");