1 //==-- SystemZISelDAGToDAG.cpp - A dag to dag inst selector for SystemZ ---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the SystemZ target.
12 //===----------------------------------------------------------------------===//
15 #include "SystemZISelLowering.h"
16 #include "SystemZTargetMachine.h"
17 #include "llvm/DerivedTypes.h"
18 #include "llvm/Function.h"
19 #include "llvm/Intrinsics.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/SelectionDAGISel.h"
28 #include "llvm/Target/TargetLowering.h"
29 #include "llvm/Support/Compiler.h"
30 #include "llvm/Support/Debug.h"
33 static const unsigned subreg_even32 = 1;
34 static const unsigned subreg_odd32 = 2;
35 static const unsigned subreg_even = 3;
36 static const unsigned subreg_odd = 4;
39 /// SystemZRRIAddressMode - This corresponds to rriaddr, but uses SDValue's
40 /// instead of register numbers for the leaves of the matched tree.
41 struct SystemZRRIAddressMode {
47 struct { // This is really a union, discriminated by BaseType!
56 SystemZRRIAddressMode(bool RI = false)
57 : BaseType(RegBase), IndexReg(), Disp(0), isRI(RI) {
61 cerr << "SystemZRRIAddressMode " << this << '\n';
62 if (BaseType == RegBase) {
64 if (Base.Reg.getNode() != 0) Base.Reg.getNode()->dump();
68 cerr << " Base.FrameIndex " << Base.FrameIndex << '\n';
72 if (IndexReg.getNode() != 0) IndexReg.getNode()->dump();
75 cerr << " Disp " << Disp << '\n';
80 /// SystemZDAGToDAGISel - SystemZ specific code to select SystemZ machine
81 /// instructions for SelectionDAG operations.
84 class SystemZDAGToDAGISel : public SelectionDAGISel {
85 SystemZTargetLowering &Lowering;
86 const SystemZSubtarget &Subtarget;
88 void getAddressOperandsRI(const SystemZRRIAddressMode &AM,
89 SDValue &Base, SDValue &Disp);
90 void getAddressOperands(const SystemZRRIAddressMode &AM,
91 SDValue &Base, SDValue &Disp,
95 SystemZDAGToDAGISel(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel)
96 : SelectionDAGISel(TM, OptLevel),
97 Lowering(*TM.getTargetLowering()),
98 Subtarget(*TM.getSubtargetImpl()) { }
100 virtual void InstructionSelect();
102 virtual const char *getPassName() const {
103 return "SystemZ DAG->DAG Pattern Instruction Selection";
106 /// getI16Imm - Return a target constant with the specified value, of type
108 inline SDValue getI16Imm(uint64_t Imm) {
109 return CurDAG->getTargetConstant(Imm, MVT::i16);
112 /// getI32Imm - Return a target constant with the specified value, of type
114 inline SDValue getI32Imm(uint64_t Imm) {
115 return CurDAG->getTargetConstant(Imm, MVT::i32);
118 // Include the pieces autogenerated from the target description.
119 #include "SystemZGenDAGISel.inc"
122 bool SelectAddrRI12Only(SDValue Op, SDValue& Addr,
123 SDValue &Base, SDValue &Disp);
124 bool SelectAddrRI12(SDValue Op, SDValue& Addr,
125 SDValue &Base, SDValue &Disp,
126 bool is12BitOnly = false);
127 bool SelectAddrRI(SDValue Op, SDValue& Addr,
128 SDValue &Base, SDValue &Disp);
129 bool SelectAddrRRI12(SDValue Op, SDValue Addr,
130 SDValue &Base, SDValue &Disp, SDValue &Index);
131 bool SelectAddrRRI20(SDValue Op, SDValue Addr,
132 SDValue &Base, SDValue &Disp, SDValue &Index);
133 bool SelectLAAddr(SDValue Op, SDValue Addr,
134 SDValue &Base, SDValue &Disp, SDValue &Index);
136 SDNode *Select(SDValue Op);
138 bool TryFoldLoad(SDValue P, SDValue N,
139 SDValue &Base, SDValue &Disp, SDValue &Index);
141 bool MatchAddress(SDValue N, SystemZRRIAddressMode &AM,
142 bool is12Bit, unsigned Depth = 0);
143 bool MatchAddressBase(SDValue N, SystemZRRIAddressMode &AM);
144 bool MatchAddressRI(SDValue N, SystemZRRIAddressMode &AM,
151 } // end anonymous namespace
153 /// createSystemZISelDag - This pass converts a legalized DAG into a
154 /// SystemZ-specific DAG, ready for instruction scheduling.
156 FunctionPass *llvm::createSystemZISelDag(SystemZTargetMachine &TM,
157 CodeGenOpt::Level OptLevel) {
158 return new SystemZDAGToDAGISel(TM, OptLevel);
161 /// isImmSExt20 - This method tests to see if the node is either a 32-bit
162 /// or 64-bit immediate, and if the value can be accurately represented as a
163 /// sign extension from a 20-bit value. If so, this returns true and the
165 static bool isImmSExt20(int64_t Val, int64_t &Imm) {
166 if (Val >= -524288 && Val <= 524287) {
173 /// isImmZExt12 - This method tests to see if the node is either a 32-bit
174 /// or 64-bit immediate, and if the value can be accurately represented as a
175 /// zero extension from a 12-bit value. If so, this returns true and the
177 static bool isImmZExt12(int64_t Val, int64_t &Imm) {
178 if (Val >= 0 && Val <= 0xFFF) {
185 /// MatchAddress - Add the specified node to the specified addressing mode,
186 /// returning true if it cannot be done. This just pattern matches for the
188 bool SystemZDAGToDAGISel::MatchAddress(SDValue N, SystemZRRIAddressMode &AM,
189 bool is12Bit, unsigned Depth) {
190 DebugLoc dl = N.getDebugLoc();
191 DOUT << "MatchAddress: "; DEBUG(AM.dump());
194 return MatchAddressBase(N, AM);
196 // FIXME: We can perform better here. If we have something like
197 // (shift (add A, imm), N), we can try to reassociate stuff and fold shift of
198 // imm into addressing mode.
199 switch (N.getOpcode()) {
201 case ISD::Constant: {
202 int64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
204 bool Match = (is12Bit ?
205 isImmZExt12(AM.Disp + Val, Imm) :
206 isImmSExt20(AM.Disp + Val, Imm));
214 case ISD::FrameIndex:
215 if (AM.BaseType == SystemZRRIAddressMode::RegBase &&
216 AM.Base.Reg.getNode() == 0) {
217 AM.BaseType = SystemZRRIAddressMode::FrameIndexBase;
218 AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
224 // Given A-B, if A can be completely folded into the address and
225 // the index field with the index field unused, use -B as the index.
226 // This is a win if a has multiple parts that can be folded into
227 // the address. Also, this saves a mov if the base register has
228 // other uses, since it avoids a two-address sub instruction, however
229 // it costs an additional mov if the index register has other uses.
231 // Test if the LHS of the sub can be folded.
232 SystemZRRIAddressMode Backup = AM;
233 if (MatchAddress(N.getNode()->getOperand(0), AM, is12Bit, Depth+1)) {
237 // Test if the index field is free for use.
238 if (AM.IndexReg.getNode() && !AM.isRI) {
243 // If the base is a register with multiple uses, this transformation may
244 // save a mov. Otherwise it's probably better not to do it.
245 if (AM.BaseType == SystemZRRIAddressMode::RegBase &&
246 (!AM.Base.Reg.getNode() || AM.Base.Reg.getNode()->hasOneUse())) {
251 // Ok, the transformation is legal and appears profitable. Go for it.
252 SDValue RHS = N.getNode()->getOperand(1);
253 SDValue Zero = CurDAG->getConstant(0, N.getValueType());
254 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS);
257 // Insert the new nodes into the topological ordering.
258 if (Zero.getNode()->getNodeId() == -1 ||
259 Zero.getNode()->getNodeId() > N.getNode()->getNodeId()) {
260 CurDAG->RepositionNode(N.getNode(), Zero.getNode());
261 Zero.getNode()->setNodeId(N.getNode()->getNodeId());
263 if (Neg.getNode()->getNodeId() == -1 ||
264 Neg.getNode()->getNodeId() > N.getNode()->getNodeId()) {
265 CurDAG->RepositionNode(N.getNode(), Neg.getNode());
266 Neg.getNode()->setNodeId(N.getNode()->getNodeId());
272 SystemZRRIAddressMode Backup = AM;
273 if (!MatchAddress(N.getNode()->getOperand(0), AM, is12Bit, Depth+1) &&
274 !MatchAddress(N.getNode()->getOperand(1), AM, is12Bit, Depth+1))
277 if (!MatchAddress(N.getNode()->getOperand(1), AM, is12Bit, Depth+1) &&
278 !MatchAddress(N.getNode()->getOperand(0), AM, is12Bit, Depth+1))
282 // If we couldn't fold both operands into the address at the same time,
283 // see if we can just put each operand into a register and fold at least
286 AM.BaseType == SystemZRRIAddressMode::RegBase &&
287 !AM.Base.Reg.getNode() && !AM.IndexReg.getNode()) {
288 AM.Base.Reg = N.getNode()->getOperand(0);
289 AM.IndexReg = N.getNode()->getOperand(1);
296 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
297 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
298 SystemZRRIAddressMode Backup = AM;
299 int64_t Offset = CN->getSExtValue();
301 bool MatchOffset = (is12Bit ?
302 isImmZExt12(AM.Disp + Offset, Imm) :
303 isImmSExt20(AM.Disp + Offset, Imm));
304 // The resultant disp must fit in 12 or 20-bits.
306 // LHS should be an addr mode.
307 !MatchAddress(N.getOperand(0), AM, is12Bit, Depth+1) &&
308 // Check to see if the LHS & C is zero.
309 CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
318 return MatchAddressBase(N, AM);
321 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
322 /// specified addressing mode without any further recursion.
323 bool SystemZDAGToDAGISel::MatchAddressBase(SDValue N,
324 SystemZRRIAddressMode &AM) {
325 // Is the base register already occupied?
326 if (AM.BaseType != SystemZRRIAddressMode::RegBase || AM.Base.Reg.getNode()) {
327 // If so, check to see if the index register is set.
328 if (AM.IndexReg.getNode() == 0 && !AM.isRI) {
333 // Otherwise, we cannot select it.
337 // Default, generate it as a register.
338 AM.BaseType = SystemZRRIAddressMode::RegBase;
343 void SystemZDAGToDAGISel::getAddressOperandsRI(const SystemZRRIAddressMode &AM,
344 SDValue &Base, SDValue &Disp) {
345 if (AM.BaseType == SystemZRRIAddressMode::RegBase)
348 Base = CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy());
349 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i64);
352 void SystemZDAGToDAGISel::getAddressOperands(const SystemZRRIAddressMode &AM,
353 SDValue &Base, SDValue &Disp,
355 getAddressOperandsRI(AM, Base, Disp);
359 /// Returns true if the address can be represented by a base register plus
360 /// an unsigned 12-bit displacement [r+imm].
361 bool SystemZDAGToDAGISel::SelectAddrRI12Only(SDValue Op, SDValue& Addr,
362 SDValue &Base, SDValue &Disp) {
363 return SelectAddrRI12(Op, Addr, Base, Disp, /*is12BitOnly*/true);
366 bool SystemZDAGToDAGISel::SelectAddrRI12(SDValue Op, SDValue& Addr,
367 SDValue &Base, SDValue &Disp,
369 SystemZRRIAddressMode AM20(/*isRI*/true), AM12(/*isRI*/true);
372 if (!Addr.hasOneUse()) {
373 unsigned Opcode = Addr.getOpcode();
374 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) {
375 // If we are able to fold N into addressing mode, then we'll allow it even
376 // if N has multiple uses. In general, addressing computation is used as
377 // addresses by all of its uses. But watch out for CopyToReg uses, that
378 // means the address computation is liveout. It will be computed by a LA
379 // so we want to avoid computing the address twice.
380 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
381 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
382 if (UI->getOpcode() == ISD::CopyToReg) {
383 MatchAddressBase(Addr, AM12);
390 if (!Done && MatchAddress(Addr, AM12, /* is12Bit */ true))
393 // Check, whether we can match stuff using 20-bit displacements
394 if (!Done && !is12BitOnly &&
395 !MatchAddress(Addr, AM20, /* is12Bit */ false))
396 if (AM12.Disp == 0 && AM20.Disp != 0)
399 DOUT << "MatchAddress (final): "; DEBUG(AM12.dump());
401 MVT VT = Addr.getValueType();
402 if (AM12.BaseType == SystemZRRIAddressMode::RegBase) {
403 if (!AM12.Base.Reg.getNode())
404 AM12.Base.Reg = CurDAG->getRegister(0, VT);
407 assert(AM12.IndexReg.getNode() == 0 && "Invalid reg-imm address mode!");
409 getAddressOperandsRI(AM12, Base, Disp);
414 /// Returns true if the address can be represented by a base register plus
415 /// a signed 20-bit displacement [r+imm].
416 bool SystemZDAGToDAGISel::SelectAddrRI(SDValue Op, SDValue& Addr,
417 SDValue &Base, SDValue &Disp) {
418 SystemZRRIAddressMode AM(/*isRI*/true);
421 if (!Addr.hasOneUse()) {
422 unsigned Opcode = Addr.getOpcode();
423 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) {
424 // If we are able to fold N into addressing mode, then we'll allow it even
425 // if N has multiple uses. In general, addressing computation is used as
426 // addresses by all of its uses. But watch out for CopyToReg uses, that
427 // means the address computation is liveout. It will be computed by a LA
428 // so we want to avoid computing the address twice.
429 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
430 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
431 if (UI->getOpcode() == ISD::CopyToReg) {
432 MatchAddressBase(Addr, AM);
439 if (!Done && MatchAddress(Addr, AM, /* is12Bit */ false))
442 DOUT << "MatchAddress (final): "; DEBUG(AM.dump());
444 MVT VT = Addr.getValueType();
445 if (AM.BaseType == SystemZRRIAddressMode::RegBase) {
446 if (!AM.Base.Reg.getNode())
447 AM.Base.Reg = CurDAG->getRegister(0, VT);
450 assert(AM.IndexReg.getNode() == 0 && "Invalid reg-imm address mode!");
452 getAddressOperandsRI(AM, Base, Disp);
457 /// Returns true if the address can be represented by a base register plus
458 /// index register plus an unsigned 12-bit displacement [base + idx + imm].
459 bool SystemZDAGToDAGISel::SelectAddrRRI12(SDValue Op, SDValue Addr,
460 SDValue &Base, SDValue &Disp, SDValue &Index) {
461 SystemZRRIAddressMode AM20, AM12;
464 if (!Addr.hasOneUse()) {
465 unsigned Opcode = Addr.getOpcode();
466 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) {
467 // If we are able to fold N into addressing mode, then we'll allow it even
468 // if N has multiple uses. In general, addressing computation is used as
469 // addresses by all of its uses. But watch out for CopyToReg uses, that
470 // means the address computation is liveout. It will be computed by a LA
471 // so we want to avoid computing the address twice.
472 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
473 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
474 if (UI->getOpcode() == ISD::CopyToReg) {
475 MatchAddressBase(Addr, AM12);
482 if (!Done && MatchAddress(Addr, AM12, /* is12Bit */ true))
485 // Check, whether we can match stuff using 20-bit displacements
486 if (!Done && !MatchAddress(Addr, AM20, /* is12Bit */ false))
487 if (AM12.Disp == 0 && AM20.Disp != 0)
490 DOUT << "MatchAddress (final): "; DEBUG(AM12.dump());
492 MVT VT = Addr.getValueType();
493 if (AM12.BaseType == SystemZRRIAddressMode::RegBase) {
494 if (!AM12.Base.Reg.getNode())
495 AM12.Base.Reg = CurDAG->getRegister(0, VT);
498 if (!AM12.IndexReg.getNode())
499 AM12.IndexReg = CurDAG->getRegister(0, VT);
501 getAddressOperands(AM12, Base, Disp, Index);
506 /// Returns true if the address can be represented by a base register plus
507 /// index register plus a signed 20-bit displacement [base + idx + imm].
508 bool SystemZDAGToDAGISel::SelectAddrRRI20(SDValue Op, SDValue Addr,
509 SDValue &Base, SDValue &Disp, SDValue &Index) {
510 SystemZRRIAddressMode AM;
513 if (!Addr.hasOneUse()) {
514 unsigned Opcode = Addr.getOpcode();
515 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) {
516 // If we are able to fold N into addressing mode, then we'll allow it even
517 // if N has multiple uses. In general, addressing computation is used as
518 // addresses by all of its uses. But watch out for CopyToReg uses, that
519 // means the address computation is liveout. It will be computed by a LA
520 // so we want to avoid computing the address twice.
521 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
522 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
523 if (UI->getOpcode() == ISD::CopyToReg) {
524 MatchAddressBase(Addr, AM);
531 if (!Done && MatchAddress(Addr, AM, /* is12Bit */ false))
534 DOUT << "MatchAddress (final): "; DEBUG(AM.dump());
536 MVT VT = Addr.getValueType();
537 if (AM.BaseType == SystemZRRIAddressMode::RegBase) {
538 if (!AM.Base.Reg.getNode())
539 AM.Base.Reg = CurDAG->getRegister(0, VT);
542 if (!AM.IndexReg.getNode())
543 AM.IndexReg = CurDAG->getRegister(0, VT);
545 getAddressOperands(AM, Base, Disp, Index);
550 /// SelectLAAddr - it calls SelectAddr and determines if the maximal addressing
551 /// mode it matches can be cost effectively emitted as an LA/LAY instruction.
552 bool SystemZDAGToDAGISel::SelectLAAddr(SDValue Op, SDValue Addr,
553 SDValue &Base, SDValue &Disp, SDValue &Index) {
554 SystemZRRIAddressMode AM;
556 if (MatchAddress(Addr, AM, false))
559 MVT VT = Addr.getValueType();
560 unsigned Complexity = 0;
561 if (AM.BaseType == SystemZRRIAddressMode::RegBase)
562 if (AM.Base.Reg.getNode())
565 AM.Base.Reg = CurDAG->getRegister(0, VT);
566 else if (AM.BaseType == SystemZRRIAddressMode::FrameIndexBase)
569 if (AM.IndexReg.getNode())
572 AM.IndexReg = CurDAG->getRegister(0, VT);
574 if (AM.Disp && (AM.Base.Reg.getNode() || AM.IndexReg.getNode()))
577 if (Complexity > 2) {
578 getAddressOperands(AM, Base, Disp, Index);
585 bool SystemZDAGToDAGISel::TryFoldLoad(SDValue P, SDValue N,
586 SDValue &Base, SDValue &Disp, SDValue &Index) {
587 if (ISD::isNON_EXTLoad(N.getNode()) &&
589 IsLegalAndProfitableToFold(N.getNode(), P.getNode(), P.getNode()))
590 return SelectAddrRRI20(P, N.getOperand(1), Base, Disp, Index);
594 /// InstructionSelect - This callback is invoked by
595 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
596 void SystemZDAGToDAGISel::InstructionSelect() {
599 // Codegen the basic block.
601 DOUT << "===== Instruction selection begins:\n";
606 DOUT << "===== Instruction selection ends:\n";
609 CurDAG->RemoveDeadNodes();
612 SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
613 SDNode *Node = Op.getNode();
614 MVT NVT = Node->getValueType(0);
615 DebugLoc dl = Op.getDebugLoc();
616 unsigned Opcode = Node->getOpcode();
618 // Dump information about the Node being selected
620 DOUT << std::string(Indent, ' ') << "Selecting: ";
621 DEBUG(Node->dump(CurDAG));
626 // If we have a custom node, we already have selected!
627 if (Node->isMachineOpcode()) {
629 DOUT << std::string(Indent-2, ' ') << "== ";
630 DEBUG(Node->dump(CurDAG));
634 return NULL; // Already selected.
641 SDValue N0 = Node->getOperand(0);
642 SDValue N1 = Node->getOperand(1);
645 bool is32Bit = false;
646 switch (NVT.getSimpleVT()) {
647 default: assert(0 && "Unsupported VT!");
649 Opc = SystemZ::SDIVREM32r; MOpc = SystemZ::SDIVREM32m;
654 Opc = SystemZ::SDIVREM64r; MOpc = SystemZ::SDIVREM64m;
659 SDValue Tmp0, Tmp1, Tmp2;
660 bool foldedLoad = TryFoldLoad(Op, N1, Tmp0, Tmp1, Tmp2);
662 // Prepare the dividend
665 Dividend = CurDAG->getTargetNode(SystemZ::MOVSX64rr32, dl, MVT::i64, N0);
667 Dividend = N0.getNode();
669 // Insert prepared dividend into suitable 'subreg'
670 SDNode *Tmp = CurDAG->getTargetNode(TargetInstrInfo::IMPLICIT_DEF,
673 CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT,
674 SDValue(Tmp, 0), SDValue(Dividend, 0),
675 CurDAG->getTargetConstant(subreg_odd, MVT::i32));
678 SDValue DivVal = SDValue(Dividend, 0);
680 SDValue Ops[] = { DivVal, Tmp0, Tmp1, Tmp2, N1.getOperand(0) };
681 Result = CurDAG->getTargetNode(MOpc, dl, ResVT, Ops, array_lengthof(Ops));
683 ReplaceUses(N1.getValue(1), SDValue(Result, 0));
685 Result = CurDAG->getTargetNode(Opc, dl, ResVT, SDValue(Dividend, 0), N1);
688 // Copy the division (odd subreg) result, if it is needed.
689 if (!Op.getValue(0).use_empty()) {
690 unsigned SubRegIdx = (is32Bit ? subreg_odd32 : subreg_odd);
691 SDNode *Div = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,
694 CurDAG->getTargetConstant(SubRegIdx,
697 ReplaceUses(Op.getValue(0), SDValue(Div, 0));
699 DOUT << std::string(Indent-2, ' ') << "=> ";
700 DEBUG(Result->dump(CurDAG));
705 // Copy the remainder (even subreg) result, if it is needed.
706 if (!Op.getValue(1).use_empty()) {
707 unsigned SubRegIdx = (is32Bit ? subreg_even32 : subreg_even);
708 SDNode *Rem = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,
711 CurDAG->getTargetConstant(SubRegIdx,
714 ReplaceUses(Op.getValue(1), SDValue(Rem, 0));
716 DOUT << std::string(Indent-2, ' ') << "=> ";
717 DEBUG(Result->dump(CurDAG));
729 unsigned Opc, MOpc, ClrOpc;
730 SDValue N0 = Node->getOperand(0);
731 SDValue N1 = Node->getOperand(1);
734 bool is32Bit = false;
735 switch (NVT.getSimpleVT()) {
736 default: assert(0 && "Unsupported VT!");
738 Opc = SystemZ::UDIVREM32r; MOpc = SystemZ::UDIVREM32m;
739 ClrOpc = SystemZ::MOV64Pr0_even;
744 Opc = SystemZ::UDIVREM64r; MOpc = SystemZ::UDIVREM64m;
745 ClrOpc = SystemZ::MOV128r0_even;
750 SDValue Tmp0, Tmp1, Tmp2;
751 bool foldedLoad = TryFoldLoad(Op, N1, Tmp0, Tmp1, Tmp2);
753 // Prepare the dividend
754 SDNode *Dividend = N0.getNode();
756 // Insert prepared dividend into suitable 'subreg'
757 SDNode *Tmp = CurDAG->getTargetNode(TargetInstrInfo::IMPLICIT_DEF,
760 unsigned SubRegIdx = (is32Bit ? subreg_odd32 : subreg_odd);
762 CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT,
763 SDValue(Tmp, 0), SDValue(Dividend, 0),
764 CurDAG->getTargetConstant(SubRegIdx, MVT::i32));
767 // Zero out even subreg
768 Dividend = CurDAG->getTargetNode(ClrOpc, dl, ResVT, SDValue(Dividend, 0));
770 SDValue DivVal = SDValue(Dividend, 0);
773 SDValue Ops[] = { DivVal, Tmp0, Tmp1, Tmp2, N1.getOperand(0) };
774 Result = CurDAG->getTargetNode(MOpc, dl,ResVT,
775 Ops, array_lengthof(Ops));
777 ReplaceUses(N1.getValue(1), SDValue(Result, 0));
779 Result = CurDAG->getTargetNode(Opc, dl, ResVT, DivVal, N1);
782 // Copy the division (odd subreg) result, if it is needed.
783 if (!Op.getValue(0).use_empty()) {
784 unsigned SubRegIdx = (is32Bit ? subreg_odd32 : subreg_odd);
785 SDNode *Div = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,
788 CurDAG->getTargetConstant(SubRegIdx,
790 ReplaceUses(Op.getValue(0), SDValue(Div, 0));
792 DOUT << std::string(Indent-2, ' ') << "=> ";
793 DEBUG(Result->dump(CurDAG));
798 // Copy the remainder (even subreg) result, if it is needed.
799 if (!Op.getValue(1).use_empty()) {
800 unsigned SubRegIdx = (is32Bit ? subreg_even32 : subreg_even);
801 SDNode *Rem = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,
804 CurDAG->getTargetConstant(SubRegIdx,
806 ReplaceUses(Op.getValue(1), SDValue(Rem, 0));
808 DOUT << std::string(Indent-2, ' ') << "=> ";
809 DEBUG(Result->dump(CurDAG));
822 // Select the default instruction
823 SDNode *ResNode = SelectCode(Op);
826 DOUT << std::string(Indent-2, ' ') << "=> ";
827 if (ResNode == NULL || ResNode == Op.getNode())
828 DEBUG(Op.getNode()->dump(CurDAG));
830 DEBUG(ResNode->dump(CurDAG));