1 //==-- SystemZISelDAGToDAG.cpp - A dag to dag inst selector for SystemZ ---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the SystemZ target.
12 //===----------------------------------------------------------------------===//
15 #include "SystemZISelLowering.h"
16 #include "SystemZTargetMachine.h"
17 #include "llvm/DerivedTypes.h"
18 #include "llvm/Function.h"
19 #include "llvm/Intrinsics.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/SelectionDAGISel.h"
28 #include "llvm/Target/TargetLowering.h"
29 #include "llvm/Support/Compiler.h"
30 #include "llvm/Support/Debug.h"
34 /// SystemZRRIAddressMode - This corresponds to rriaddr, but uses SDValue's
35 /// instead of register numbers for the leaves of the matched tree.
36 struct SystemZRRIAddressMode {
42 struct { // This is really a union, discriminated by BaseType!
50 SystemZRRIAddressMode()
51 : BaseType(RegBase), IndexReg(), Disp(0) {
55 cerr << "SystemZRRIAddressMode " << this << '\n';
56 if (BaseType == RegBase) {
58 if (Base.Reg.getNode() != 0) Base.Reg.getNode()->dump();
62 cerr << " Base.FrameIndex " << Base.FrameIndex << '\n';
65 if (IndexReg.getNode() != 0) IndexReg.getNode()->dump();
67 cerr << " Disp " << Disp << '\n';
72 /// SystemZDAGToDAGISel - SystemZ specific code to select SystemZ machine
73 /// instructions for SelectionDAG operations.
76 class SystemZDAGToDAGISel : public SelectionDAGISel {
77 SystemZTargetLowering &Lowering;
78 const SystemZSubtarget &Subtarget;
81 SystemZDAGToDAGISel(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel)
82 : SelectionDAGISel(TM, OptLevel),
83 Lowering(*TM.getTargetLowering()),
84 Subtarget(*TM.getSubtargetImpl()) { }
86 virtual void InstructionSelect();
88 virtual const char *getPassName() const {
89 return "SystemZ DAG->DAG Pattern Instruction Selection";
92 /// getI16Imm - Return a target constant with the specified value, of type
94 inline SDValue getI16Imm(uint64_t Imm) {
95 return CurDAG->getTargetConstant(Imm, MVT::i16);
98 /// getI32Imm - Return a target constant with the specified value, of type
100 inline SDValue getI32Imm(uint64_t Imm) {
101 return CurDAG->getTargetConstant(Imm, MVT::i32);
104 // Include the pieces autogenerated from the target description.
105 #include "SystemZGenDAGISel.inc"
108 bool SelectAddrRI32(const SDValue& Op, SDValue& Addr,
109 SDValue &Base, SDValue &Disp);
110 bool SelectAddrRI(const SDValue& Op, SDValue& Addr,
111 SDValue &Base, SDValue &Disp);
112 bool SelectAddrRRI(SDValue Op, SDValue Addr,
113 SDValue &Base, SDValue &Disp, SDValue &Index);
114 bool SelectLAAddr(SDValue Op, SDValue Addr,
115 SDValue &Base, SDValue &Disp, SDValue &Index);
117 SDNode *Select(SDValue Op);
118 bool MatchAddress(SDValue N, SystemZRRIAddressMode &AM, unsigned Depth = 0);
119 bool MatchAddressBase(SDValue N, SystemZRRIAddressMode &AM);
125 } // end anonymous namespace
127 /// createSystemZISelDag - This pass converts a legalized DAG into a
128 /// SystemZ-specific DAG, ready for instruction scheduling.
130 FunctionPass *llvm::createSystemZISelDag(SystemZTargetMachine &TM,
131 CodeGenOpt::Level OptLevel) {
132 return new SystemZDAGToDAGISel(TM, OptLevel);
135 /// isImmSExt20 - This method tests to see if the node is either a 32-bit
136 /// or 64-bit immediate, and if the value can be accurately represented as a
137 /// sign extension from a 20-bit value. If so, this returns true and the
139 static bool isImmSExt20(int64_t Val, int64_t &Imm) {
140 if (Val >= -524288 && Val <= 524287) {
147 static bool isImmSExt20(SDNode *N, int64_t &Imm) {
148 if (N->getOpcode() != ISD::Constant)
151 return isImmSExt20(cast<ConstantSDNode>(N)->getSExtValue(), Imm);
154 static bool isImmSExt20(SDValue Op, int64_t &Imm) {
155 return isImmSExt20(Op.getNode(), Imm);
158 /// isImmSExt12 - This method tests to see if the node is either a 32-bit
159 /// or 64-bit immediate, and if the value can be accurately represented as a
160 /// zero extension from a 12-bit value. If so, this returns true and the
162 static bool isImmZExt12(SDNode *N, uint64_t &Imm) {
163 if (N->getOpcode() != ISD::Constant)
166 uint64_t Val = cast<ConstantSDNode>(N)->getZExtValue();
175 static bool isImmZExt12(SDValue Op, uint64_t &Imm) {
176 return isImmZExt12(Op.getNode(), Imm);
179 /// Returns true if the address can be represented by a base register plus
180 /// an unsigned 12-bit displacement [r+imm].
181 bool SystemZDAGToDAGISel::SelectAddrRI32(const SDValue& Op, SDValue& Addr,
182 SDValue &Base, SDValue &Disp) {
183 // FIXME dl should come from parent load or store, not from address
184 DebugLoc dl = Addr.getDebugLoc();
185 MVT VT = Addr.getValueType();
187 if (Addr.getOpcode() == ISD::ADD) {
189 if (isImmZExt12(Addr.getOperand(1), Imm)) {
190 Disp = CurDAG->getTargetConstant(Imm, MVT::i64);
191 if (FrameIndexSDNode *FI =
192 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
193 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), VT);
195 Base = Addr.getOperand(0);
197 return true; // [r+i]
199 } else if (Addr.getOpcode() == ISD::OR) {
201 if (isImmZExt12(Addr.getOperand(1), Imm)) {
202 // If this is an or of disjoint bitfields, we can codegen this as an add
203 // (for better address arithmetic) if the LHS and RHS of the OR are
204 // provably disjoint.
205 APInt LHSKnownZero, LHSKnownOne;
206 CurDAG->ComputeMaskedBits(Addr.getOperand(0),
207 APInt::getAllOnesValue(Addr.getOperand(0)
208 .getValueSizeInBits()),
209 LHSKnownZero, LHSKnownOne);
211 if ((LHSKnownZero.getZExtValue()|~(uint64_t)Imm) == ~0ULL) {
212 // If all of the bits are known zero on the LHS or RHS, the add won't
214 Base = Addr.getOperand(0);
215 Disp = CurDAG->getTargetConstant(Imm, MVT::i64);
219 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr)) {
220 // Loading from a constant address.
222 // If this address fits entirely in a 12-bit zext immediate field, codegen
225 if (isImmZExt12(CN, Imm)) {
226 Disp = CurDAG->getTargetConstant(Imm, MVT::i64);
227 Base = CurDAG->getRegister(0, VT);
232 Disp = CurDAG->getTargetConstant(0, MVT::i64);
233 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Addr))
234 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), VT);
237 return true; // [r+0]
240 /// Returns true if the address can be represented by a base register plus
241 /// a signed 20-bit displacement [r+imm].
242 bool SystemZDAGToDAGISel::SelectAddrRI(const SDValue& Op, SDValue& Addr,
243 SDValue &Base, SDValue &Disp) {
244 // FIXME dl should come from parent load or store, not from address
245 DebugLoc dl = Addr.getDebugLoc();
246 MVT VT = Addr.getValueType();
248 if (Addr.getOpcode() == ISD::ADD) {
250 if (isImmSExt20(Addr.getOperand(1), Imm)) {
251 Disp = CurDAG->getTargetConstant(Imm, MVT::i64);
252 if (FrameIndexSDNode *FI =
253 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
254 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), VT);
256 Base = Addr.getOperand(0);
258 return true; // [r+i]
260 } else if (Addr.getOpcode() == ISD::OR) {
262 if (isImmSExt20(Addr.getOperand(1), Imm)) {
263 // If this is an or of disjoint bitfields, we can codegen this as an add
264 // (for better address arithmetic) if the LHS and RHS of the OR are
265 // provably disjoint.
266 APInt LHSKnownZero, LHSKnownOne;
267 CurDAG->ComputeMaskedBits(Addr.getOperand(0),
268 APInt::getAllOnesValue(Addr.getOperand(0)
269 .getValueSizeInBits()),
270 LHSKnownZero, LHSKnownOne);
272 if ((LHSKnownZero.getZExtValue()|~(uint64_t)Imm) == ~0ULL) {
273 // If all of the bits are known zero on the LHS or RHS, the add won't
275 Base = Addr.getOperand(0);
276 Disp = CurDAG->getTargetConstant(Imm, MVT::i64);
280 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr)) {
281 // Loading from a constant address.
283 // If this address fits entirely in a 20-bit sext immediate field, codegen
286 if (isImmSExt20(CN, Imm)) {
287 Disp = CurDAG->getTargetConstant(Imm, MVT::i64);
288 Base = CurDAG->getRegister(0, VT);
293 Disp = CurDAG->getTargetConstant(0, MVT::i64);
294 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Addr))
295 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), VT);
298 return true; // [r+0]
301 /// MatchAddress - Add the specified node to the specified addressing mode,
302 /// returning true if it cannot be done. This just pattern matches for the
304 bool SystemZDAGToDAGISel::MatchAddress(SDValue N, SystemZRRIAddressMode &AM,
306 DebugLoc dl = N.getDebugLoc();
307 DOUT << "MatchAddress: "; DEBUG(AM.dump());
310 return MatchAddressBase(N, AM);
312 // FIXME: We can perform better here. If we have something like
313 // (shift (add A, imm), N), we can try to reassociate stuff and fold shift of
314 // imm into addressing mode.
315 switch (N.getOpcode()) {
317 case ISD::Constant: {
318 int64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
320 if (isImmSExt20(AM.Disp + Val, Imm)) {
327 case ISD::FrameIndex:
328 if (AM.BaseType == SystemZRRIAddressMode::RegBase
329 && AM.Base.Reg.getNode() == 0) {
330 AM.BaseType = SystemZRRIAddressMode::FrameIndexBase;
331 AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
337 // Given A-B, if A can be completely folded into the address and
338 // the index field with the index field unused, use -B as the index.
339 // This is a win if a has multiple parts that can be folded into
340 // the address. Also, this saves a mov if the base register has
341 // other uses, since it avoids a two-address sub instruction, however
342 // it costs an additional mov if the index register has other uses.
344 // Test if the LHS of the sub can be folded.
345 SystemZRRIAddressMode Backup = AM;
346 if (MatchAddress(N.getNode()->getOperand(0), AM, Depth+1)) {
350 // Test if the index field is free for use.
351 if (AM.IndexReg.getNode()) {
356 // If the base is a register with multiple uses, this transformation may
357 // save a mov. Otherwise it's probably better not to do it.
358 if (AM.BaseType == SystemZRRIAddressMode::RegBase &&
359 (!AM.Base.Reg.getNode() || AM.Base.Reg.getNode()->hasOneUse())) {
364 // Ok, the transformation is legal and appears profitable. Go for it.
365 SDValue RHS = N.getNode()->getOperand(1);
366 SDValue Zero = CurDAG->getConstant(0, N.getValueType());
367 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS);
370 // Insert the new nodes into the topological ordering.
371 if (Zero.getNode()->getNodeId() == -1 ||
372 Zero.getNode()->getNodeId() > N.getNode()->getNodeId()) {
373 CurDAG->RepositionNode(N.getNode(), Zero.getNode());
374 Zero.getNode()->setNodeId(N.getNode()->getNodeId());
376 if (Neg.getNode()->getNodeId() == -1 ||
377 Neg.getNode()->getNodeId() > N.getNode()->getNodeId()) {
378 CurDAG->RepositionNode(N.getNode(), Neg.getNode());
379 Neg.getNode()->setNodeId(N.getNode()->getNodeId());
385 SystemZRRIAddressMode Backup = AM;
386 if (!MatchAddress(N.getNode()->getOperand(0), AM, Depth+1) &&
387 !MatchAddress(N.getNode()->getOperand(1), AM, Depth+1))
390 if (!MatchAddress(N.getNode()->getOperand(1), AM, Depth+1) &&
391 !MatchAddress(N.getNode()->getOperand(0), AM, Depth+1))
395 // If we couldn't fold both operands into the address at the same time,
396 // see if we can just put each operand into a register and fold at least
398 if (AM.BaseType == SystemZRRIAddressMode::RegBase &&
399 !AM.Base.Reg.getNode() && !AM.IndexReg.getNode()) {
400 AM.Base.Reg = N.getNode()->getOperand(0);
401 AM.IndexReg = N.getNode()->getOperand(1);
408 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
409 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
410 SystemZRRIAddressMode Backup = AM;
411 int64_t Offset = CN->getSExtValue();
413 // Start with the LHS as an addr mode.
414 if (!MatchAddress(N.getOperand(0), AM, Depth+1) &&
415 // The resultant disp must fit in 20-bits.
416 isImmSExt20(AM.Disp + Offset, Imm) &&
417 // Check to see if the LHS & C is zero.
418 CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
427 return MatchAddressBase(N, AM);
430 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
431 /// specified addressing mode without any further recursion.
432 bool SystemZDAGToDAGISel::MatchAddressBase(SDValue N,
433 SystemZRRIAddressMode &AM) {
434 // Is the base register already occupied?
435 if (AM.BaseType != SystemZRRIAddressMode::RegBase || AM.Base.Reg.getNode()) {
436 // If so, check to see if the scale index register is set.
437 if (AM.IndexReg.getNode() == 0) {
442 // Otherwise, we cannot select it.
446 // Default, generate it as a register.
447 AM.BaseType = SystemZRRIAddressMode::RegBase;
452 /// Returns true if the address can be represented by a base register plus
453 /// index register plus a signed 20-bit displacement [base + idx + imm].
454 bool SystemZDAGToDAGISel::SelectAddrRRI(SDValue Op, SDValue Addr,
455 SDValue &Base, SDValue &Disp, SDValue &Index) {
456 SystemZRRIAddressMode AM;
459 if (!Addr.hasOneUse()) {
460 unsigned Opcode = Addr.getOpcode();
461 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) {
462 // If we are able to fold N into addressing mode, then we'll allow it even
463 // if N has multiple uses. In general, addressing computation is used as
464 // addresses by all of its uses. But watch out for CopyToReg uses, that
465 // means the address computation is liveout. It will be computed by a LA
466 // so we want to avoid computing the address twice.
467 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
468 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
469 if (UI->getOpcode() == ISD::CopyToReg) {
470 MatchAddressBase(Addr, AM);
477 if (!Done && MatchAddress(Addr, AM))
480 DOUT << "MatchAddress (final): "; DEBUG(AM.dump());
482 MVT VT = Addr.getValueType();
483 if (AM.BaseType == SystemZRRIAddressMode::RegBase) {
484 if (!AM.Base.Reg.getNode())
485 AM.Base.Reg = CurDAG->getRegister(0, VT);
488 if (!AM.IndexReg.getNode())
489 AM.IndexReg = CurDAG->getRegister(0, VT);
491 if (AM.BaseType == SystemZRRIAddressMode::RegBase)
494 Base = CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy());
496 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i64);
501 /// SelectLAAddr - it calls SelectAddr and determines if the maximal addressing
502 /// mode it matches can be cost effectively emitted as an LA/LAY instruction.
503 bool SystemZDAGToDAGISel::SelectLAAddr(SDValue Op, SDValue Addr,
504 SDValue &Base, SDValue &Disp, SDValue &Index) {
505 SystemZRRIAddressMode AM;
507 if (MatchAddress(Addr, AM))
510 MVT VT = Addr.getValueType();
511 unsigned Complexity = 0;
512 if (AM.BaseType == SystemZRRIAddressMode::RegBase)
513 if (AM.Base.Reg.getNode())
516 AM.Base.Reg = CurDAG->getRegister(0, VT);
517 else if (AM.BaseType == SystemZRRIAddressMode::FrameIndexBase)
520 if (AM.IndexReg.getNode())
523 AM.IndexReg = CurDAG->getRegister(0, VT);
525 if (AM.Disp && (AM.Base.Reg.getNode() || AM.IndexReg.getNode()))
528 if (Complexity > 2) {
529 if (AM.BaseType == SystemZRRIAddressMode::RegBase)
532 Base = CurDAG->getTargetFrameIndex(AM.Base.FrameIndex,
535 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i64);
542 /// InstructionSelect - This callback is invoked by
543 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
544 void SystemZDAGToDAGISel::InstructionSelect() {
547 // Codegen the basic block.
549 DOUT << "===== Instruction selection begins:\n";
554 DOUT << "===== Instruction selection ends:\n";
557 CurDAG->RemoveDeadNodes();
560 SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
561 SDNode *Node = Op.getNode();
562 DebugLoc dl = Op.getDebugLoc();
564 // Dump information about the Node being selected
566 DOUT << std::string(Indent, ' ') << "Selecting: ";
567 DEBUG(Node->dump(CurDAG));
572 // If we have a custom node, we already have selected!
573 if (Node->isMachineOpcode()) {
575 DOUT << std::string(Indent-2, ' ') << "== ";
576 DEBUG(Node->dump(CurDAG));
583 // Select the default instruction
584 SDNode *ResNode = SelectCode(Op);
587 DOUT << std::string(Indent-2, ' ') << "=> ";
588 if (ResNode == NULL || ResNode == Op.getNode())
589 DEBUG(Op.getNode()->dump(CurDAG));
591 DEBUG(ResNode->dump(CurDAG));