1 //===-- SystemZISelDAGToDAG.cpp - A dag to dag inst selector for SystemZ --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the SystemZ target.
12 //===----------------------------------------------------------------------===//
14 #include "SystemZTargetMachine.h"
15 #include "llvm/Analysis/AliasAnalysis.h"
16 #include "llvm/CodeGen/SelectionDAGISel.h"
17 #include "llvm/Support/Debug.h"
18 #include "llvm/Support/raw_ostream.h"
23 // Used to build addressing modes.
24 struct SystemZAddressingMode {
25 // The shape of the address.
30 // base+displacement+index for load and store operands
33 // base+displacement+index for load address operands
36 // base+displacement+index+ADJDYNALLOC
41 // The type of displacement. The enum names here correspond directly
42 // to the definitions in SystemZOperand.td. We could split them into
43 // flags -- single/pair, 128-bit, etc. -- but it hardly seems worth it.
53 // The parts of the address. The address is equivalent to:
55 // Base + Disp + Index + (IncludesDynAlloc ? ADJDYNALLOC : 0)
59 bool IncludesDynAlloc;
61 SystemZAddressingMode(AddrForm form, DispRange dr)
62 : Form(form), DR(dr), Base(), Disp(0), Index(),
63 IncludesDynAlloc(false) {}
65 // True if the address can have an index register.
66 bool hasIndexField() { return Form != FormBD; }
68 // True if the address can (and must) include ADJDYNALLOC.
69 bool isDynAlloc() { return Form == FormBDXDynAlloc; }
72 errs() << "SystemZAddressingMode " << this << '\n';
75 if (Base.getNode() != 0)
76 Base.getNode()->dump();
80 if (hasIndexField()) {
82 if (Index.getNode() != 0)
83 Index.getNode()->dump();
88 errs() << " Disp " << Disp;
90 errs() << " + ADJDYNALLOC";
95 // Return a mask with Count low bits set.
96 static uint64_t allOnes(unsigned int Count) {
97 return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1;
100 // Represents operands 2 to 5 of the ROTATE AND ... SELECTED BITS operation
101 // given by Opcode. The operands are: Input (R2), Start (I3), End (I4) and
102 // Rotate (I5). The combined operand value is effectively:
104 // (or (rotl Input, Rotate), ~Mask)
108 // (and (rotl Input, Rotate), Mask)
110 // otherwise. The output value has BitSize bits, although Input may be
111 // narrower (in which case the upper bits are don't care).
112 struct RxSBGOperands {
113 RxSBGOperands(unsigned Op, SDValue N)
114 : Opcode(Op), BitSize(N.getValueType().getSizeInBits()),
115 Mask(allOnes(BitSize)), Input(N), Start(64 - BitSize), End(63),
127 class SystemZDAGToDAGISel : public SelectionDAGISel {
128 const SystemZTargetLowering &Lowering;
129 const SystemZSubtarget &Subtarget;
131 // Used by SystemZOperands.td to create integer constants.
132 inline SDValue getImm(const SDNode *Node, uint64_t Imm) const {
133 return CurDAG->getTargetConstant(Imm, Node->getValueType(0));
136 const SystemZTargetMachine &getTargetMachine() const {
137 return static_cast<const SystemZTargetMachine &>(TM);
140 const SystemZInstrInfo *getInstrInfo() const {
141 return getTargetMachine().getInstrInfo();
144 // Try to fold more of the base or index of AM into AM, where IsBase
145 // selects between the base and index.
146 bool expandAddress(SystemZAddressingMode &AM, bool IsBase) const;
148 // Try to describe N in AM, returning true on success.
149 bool selectAddress(SDValue N, SystemZAddressingMode &AM) const;
151 // Extract individual target operands from matched address AM.
152 void getAddressOperands(const SystemZAddressingMode &AM, EVT VT,
153 SDValue &Base, SDValue &Disp) const;
154 void getAddressOperands(const SystemZAddressingMode &AM, EVT VT,
155 SDValue &Base, SDValue &Disp, SDValue &Index) const;
157 // Try to match Addr as a FormBD address with displacement type DR.
158 // Return true on success, storing the base and displacement in
159 // Base and Disp respectively.
160 bool selectBDAddr(SystemZAddressingMode::DispRange DR, SDValue Addr,
161 SDValue &Base, SDValue &Disp) const;
163 // Try to match Addr as a FormBDX address with displacement type DR.
164 // Return true on success and if the result had no index. Store the
165 // base and displacement in Base and Disp respectively.
166 bool selectMVIAddr(SystemZAddressingMode::DispRange DR, SDValue Addr,
167 SDValue &Base, SDValue &Disp) const;
169 // Try to match Addr as a FormBDX* address of form Form with
170 // displacement type DR. Return true on success, storing the base,
171 // displacement and index in Base, Disp and Index respectively.
172 bool selectBDXAddr(SystemZAddressingMode::AddrForm Form,
173 SystemZAddressingMode::DispRange DR, SDValue Addr,
174 SDValue &Base, SDValue &Disp, SDValue &Index) const;
176 // PC-relative address matching routines used by SystemZOperands.td.
177 bool selectPCRelAddress(SDValue Addr, SDValue &Target) const {
178 if (SystemZISD::isPCREL(Addr.getOpcode())) {
179 Target = Addr.getOperand(0);
185 // BD matching routines used by SystemZOperands.td.
186 bool selectBDAddr12Only(SDValue Addr, SDValue &Base, SDValue &Disp) const {
187 return selectBDAddr(SystemZAddressingMode::Disp12Only, Addr, Base, Disp);
189 bool selectBDAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp) const {
190 return selectBDAddr(SystemZAddressingMode::Disp12Pair, Addr, Base, Disp);
192 bool selectBDAddr20Only(SDValue Addr, SDValue &Base, SDValue &Disp) const {
193 return selectBDAddr(SystemZAddressingMode::Disp20Only, Addr, Base, Disp);
195 bool selectBDAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp) const {
196 return selectBDAddr(SystemZAddressingMode::Disp20Pair, Addr, Base, Disp);
199 // MVI matching routines used by SystemZOperands.td.
200 bool selectMVIAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp) const {
201 return selectMVIAddr(SystemZAddressingMode::Disp12Pair, Addr, Base, Disp);
203 bool selectMVIAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp) const {
204 return selectMVIAddr(SystemZAddressingMode::Disp20Pair, Addr, Base, Disp);
207 // BDX matching routines used by SystemZOperands.td.
208 bool selectBDXAddr12Only(SDValue Addr, SDValue &Base, SDValue &Disp,
209 SDValue &Index) const {
210 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal,
211 SystemZAddressingMode::Disp12Only,
212 Addr, Base, Disp, Index);
214 bool selectBDXAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp,
215 SDValue &Index) const {
216 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal,
217 SystemZAddressingMode::Disp12Pair,
218 Addr, Base, Disp, Index);
220 bool selectDynAlloc12Only(SDValue Addr, SDValue &Base, SDValue &Disp,
221 SDValue &Index) const {
222 return selectBDXAddr(SystemZAddressingMode::FormBDXDynAlloc,
223 SystemZAddressingMode::Disp12Only,
224 Addr, Base, Disp, Index);
226 bool selectBDXAddr20Only(SDValue Addr, SDValue &Base, SDValue &Disp,
227 SDValue &Index) const {
228 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal,
229 SystemZAddressingMode::Disp20Only,
230 Addr, Base, Disp, Index);
232 bool selectBDXAddr20Only128(SDValue Addr, SDValue &Base, SDValue &Disp,
233 SDValue &Index) const {
234 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal,
235 SystemZAddressingMode::Disp20Only128,
236 Addr, Base, Disp, Index);
238 bool selectBDXAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp,
239 SDValue &Index) const {
240 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal,
241 SystemZAddressingMode::Disp20Pair,
242 Addr, Base, Disp, Index);
244 bool selectLAAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp,
245 SDValue &Index) const {
246 return selectBDXAddr(SystemZAddressingMode::FormBDXLA,
247 SystemZAddressingMode::Disp12Pair,
248 Addr, Base, Disp, Index);
250 bool selectLAAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp,
251 SDValue &Index) const {
252 return selectBDXAddr(SystemZAddressingMode::FormBDXLA,
253 SystemZAddressingMode::Disp20Pair,
254 Addr, Base, Disp, Index);
257 // Check whether (or Op (and X InsertMask)) is effectively an insertion
258 // of X into bits InsertMask of some Y != Op. Return true if so and
260 bool detectOrAndInsertion(SDValue &Op, uint64_t InsertMask) const;
262 // Try to update RxSBG so that only the bits of RxSBG.Input in Mask are used.
263 // Return true on success.
264 bool refineRxSBGMask(RxSBGOperands &RxSBG, uint64_t Mask) const;
266 // Try to fold some of RxSBG.Input into other fields of RxSBG.
267 // Return true on success.
268 bool expandRxSBG(RxSBGOperands &RxSBG) const;
270 // Return an undefined value of type VT.
271 SDValue getUNDEF(SDLoc DL, EVT VT) const;
273 // Convert N to VT, if it isn't already.
274 SDValue convertTo(SDLoc DL, EVT VT, SDValue N) const;
276 // Try to implement AND or shift node N using RISBG with the zero flag set.
277 // Return the selected node on success, otherwise return null.
278 SDNode *tryRISBGZero(SDNode *N);
280 // Try to use RISBG or Opcode to implement OR or XOR node N.
281 // Return the selected node on success, otherwise return null.
282 SDNode *tryRxSBG(SDNode *N, unsigned Opcode);
284 // If Op0 is null, then Node is a constant that can be loaded using:
286 // (Opcode UpperVal LowerVal)
288 // If Op0 is nonnull, then Node can be implemented using:
290 // (Opcode (Opcode Op0 UpperVal) LowerVal)
291 SDNode *splitLargeImmediate(unsigned Opcode, SDNode *Node, SDValue Op0,
292 uint64_t UpperVal, uint64_t LowerVal);
294 // Return true if Load and Store are loads and stores of the same size
295 // and are guaranteed not to overlap. Such operations can be implemented
296 // using block (SS-format) instructions.
298 // Partial overlap would lead to incorrect code, since the block operations
299 // are logically bytewise, even though they have a fast path for the
300 // non-overlapping case. We also need to avoid full overlap (i.e. two
301 // addresses that might be equal at run time) because although that case
302 // would be handled correctly, it might be implemented by millicode.
303 bool canUseBlockOperation(StoreSDNode *Store, LoadSDNode *Load) const;
305 // N is a (store (load Y), X) pattern. Return true if it can use an MVC
307 bool storeLoadCanUseMVC(SDNode *N) const;
309 // N is a (store (op (load A[0]), (load A[1])), X) pattern. Return true
310 // if A[1 - I] == X and if N can use a block operation like NC from A[I]
312 bool storeLoadCanUseBlockBinary(SDNode *N, unsigned I) const;
315 SystemZDAGToDAGISel(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel)
316 : SelectionDAGISel(TM, OptLevel),
317 Lowering(*TM.getTargetLowering()),
318 Subtarget(*TM.getSubtargetImpl()) { }
320 // Override MachineFunctionPass.
321 virtual const char *getPassName() const LLVM_OVERRIDE {
322 return "SystemZ DAG->DAG Pattern Instruction Selection";
325 // Override SelectionDAGISel.
326 virtual SDNode *Select(SDNode *Node) LLVM_OVERRIDE;
327 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
329 std::vector<SDValue> &OutOps)
332 // Include the pieces autogenerated from the target description.
333 #include "SystemZGenDAGISel.inc"
335 } // end anonymous namespace
337 FunctionPass *llvm::createSystemZISelDag(SystemZTargetMachine &TM,
338 CodeGenOpt::Level OptLevel) {
339 return new SystemZDAGToDAGISel(TM, OptLevel);
342 // Return true if Val should be selected as a displacement for an address
343 // with range DR. Here we're interested in the range of both the instruction
344 // described by DR and of any pairing instruction.
345 static bool selectDisp(SystemZAddressingMode::DispRange DR, int64_t Val) {
347 case SystemZAddressingMode::Disp12Only:
348 return isUInt<12>(Val);
350 case SystemZAddressingMode::Disp12Pair:
351 case SystemZAddressingMode::Disp20Only:
352 case SystemZAddressingMode::Disp20Pair:
353 return isInt<20>(Val);
355 case SystemZAddressingMode::Disp20Only128:
356 return isInt<20>(Val) && isInt<20>(Val + 8);
358 llvm_unreachable("Unhandled displacement range");
361 // Change the base or index in AM to Value, where IsBase selects
362 // between the base and index.
363 static void changeComponent(SystemZAddressingMode &AM, bool IsBase,
371 // The base or index of AM is equivalent to Value + ADJDYNALLOC,
372 // where IsBase selects between the base and index. Try to fold the
373 // ADJDYNALLOC into AM.
374 static bool expandAdjDynAlloc(SystemZAddressingMode &AM, bool IsBase,
376 if (AM.isDynAlloc() && !AM.IncludesDynAlloc) {
377 changeComponent(AM, IsBase, Value);
378 AM.IncludesDynAlloc = true;
384 // The base of AM is equivalent to Base + Index. Try to use Index as
385 // the index register.
386 static bool expandIndex(SystemZAddressingMode &AM, SDValue Base,
388 if (AM.hasIndexField() && !AM.Index.getNode()) {
396 // The base or index of AM is equivalent to Op0 + Op1, where IsBase selects
397 // between the base and index. Try to fold Op1 into AM's displacement.
398 static bool expandDisp(SystemZAddressingMode &AM, bool IsBase,
399 SDValue Op0, uint64_t Op1) {
400 // First try adjusting the displacement.
401 int64_t TestDisp = AM.Disp + Op1;
402 if (selectDisp(AM.DR, TestDisp)) {
403 changeComponent(AM, IsBase, Op0);
408 // We could consider forcing the displacement into a register and
409 // using it as an index, but it would need to be carefully tuned.
413 bool SystemZDAGToDAGISel::expandAddress(SystemZAddressingMode &AM,
415 SDValue N = IsBase ? AM.Base : AM.Index;
416 unsigned Opcode = N.getOpcode();
417 if (Opcode == ISD::TRUNCATE) {
419 Opcode = N.getOpcode();
421 if (Opcode == ISD::ADD || CurDAG->isBaseWithConstantOffset(N)) {
422 SDValue Op0 = N.getOperand(0);
423 SDValue Op1 = N.getOperand(1);
425 unsigned Op0Code = Op0->getOpcode();
426 unsigned Op1Code = Op1->getOpcode();
428 if (Op0Code == SystemZISD::ADJDYNALLOC)
429 return expandAdjDynAlloc(AM, IsBase, Op1);
430 if (Op1Code == SystemZISD::ADJDYNALLOC)
431 return expandAdjDynAlloc(AM, IsBase, Op0);
433 if (Op0Code == ISD::Constant)
434 return expandDisp(AM, IsBase, Op1,
435 cast<ConstantSDNode>(Op0)->getSExtValue());
436 if (Op1Code == ISD::Constant)
437 return expandDisp(AM, IsBase, Op0,
438 cast<ConstantSDNode>(Op1)->getSExtValue());
440 if (IsBase && expandIndex(AM, Op0, Op1))
443 if (Opcode == SystemZISD::PCREL_OFFSET) {
444 SDValue Full = N.getOperand(0);
445 SDValue Base = N.getOperand(1);
446 SDValue Anchor = Base.getOperand(0);
447 uint64_t Offset = (cast<GlobalAddressSDNode>(Full)->getOffset() -
448 cast<GlobalAddressSDNode>(Anchor)->getOffset());
449 return expandDisp(AM, IsBase, Base, Offset);
454 // Return true if an instruction with displacement range DR should be
455 // used for displacement value Val. selectDisp(DR, Val) must already hold.
456 static bool isValidDisp(SystemZAddressingMode::DispRange DR, int64_t Val) {
457 assert(selectDisp(DR, Val) && "Invalid displacement");
459 case SystemZAddressingMode::Disp12Only:
460 case SystemZAddressingMode::Disp20Only:
461 case SystemZAddressingMode::Disp20Only128:
464 case SystemZAddressingMode::Disp12Pair:
465 // Use the other instruction if the displacement is too large.
466 return isUInt<12>(Val);
468 case SystemZAddressingMode::Disp20Pair:
469 // Use the other instruction if the displacement is small enough.
470 return !isUInt<12>(Val);
472 llvm_unreachable("Unhandled displacement range");
475 // Return true if Base + Disp + Index should be performed by LA(Y).
476 static bool shouldUseLA(SDNode *Base, int64_t Disp, SDNode *Index) {
477 // Don't use LA(Y) for constants.
481 // Always use LA(Y) for frame addresses, since we know that the destination
482 // register is almost always (perhaps always) going to be different from
483 // the frame register.
484 if (Base->getOpcode() == ISD::FrameIndex)
488 // Always use LA(Y) if there is a base, displacement and index.
492 // Always use LA if the displacement is small enough. It should always
493 // be no worse than AGHI (and better if it avoids a move).
494 if (isUInt<12>(Disp))
497 // For similar reasons, always use LAY if the constant is too big for AGHI.
498 // LAY should be no worse than AGFI.
499 if (!isInt<16>(Disp))
502 // Don't use LA for plain registers.
506 // Don't use LA for plain addition if the index operand is only used
507 // once. It should be a natural two-operand addition in that case.
508 if (Index->hasOneUse())
511 // Prefer addition if the second operation is sign-extended, in the
512 // hope of using AGF.
513 unsigned IndexOpcode = Index->getOpcode();
514 if (IndexOpcode == ISD::SIGN_EXTEND ||
515 IndexOpcode == ISD::SIGN_EXTEND_INREG)
519 // Don't use LA for two-operand addition if either operand is only
520 // used once. The addition instructions are better in that case.
521 if (Base->hasOneUse())
527 // Return true if Addr is suitable for AM, updating AM if so.
528 bool SystemZDAGToDAGISel::selectAddress(SDValue Addr,
529 SystemZAddressingMode &AM) const {
530 // Start out assuming that the address will need to be loaded separately,
531 // then try to extend it as much as we can.
534 // First try treating the address as a constant.
535 if (Addr.getOpcode() == ISD::Constant &&
536 expandDisp(AM, true, SDValue(),
537 cast<ConstantSDNode>(Addr)->getSExtValue()))
540 // Otherwise try expanding each component.
541 while (expandAddress(AM, true) ||
542 (AM.Index.getNode() && expandAddress(AM, false)))
545 // Reject cases where it isn't profitable to use LA(Y).
546 if (AM.Form == SystemZAddressingMode::FormBDXLA &&
547 !shouldUseLA(AM.Base.getNode(), AM.Disp, AM.Index.getNode()))
550 // Reject cases where the other instruction in a pair should be used.
551 if (!isValidDisp(AM.DR, AM.Disp))
554 // Make sure that ADJDYNALLOC is included where necessary.
555 if (AM.isDynAlloc() && !AM.IncludesDynAlloc)
562 // Insert a node into the DAG at least before Pos. This will reposition
563 // the node as needed, and will assign it a node ID that is <= Pos's ID.
564 // Note that this does *not* preserve the uniqueness of node IDs!
565 // The selection DAG must no longer depend on their uniqueness when this
567 static void insertDAGNode(SelectionDAG *DAG, SDNode *Pos, SDValue N) {
568 if (N.getNode()->getNodeId() == -1 ||
569 N.getNode()->getNodeId() > Pos->getNodeId()) {
570 DAG->RepositionNode(Pos, N.getNode());
571 N.getNode()->setNodeId(Pos->getNodeId());
575 void SystemZDAGToDAGISel::getAddressOperands(const SystemZAddressingMode &AM,
576 EVT VT, SDValue &Base,
577 SDValue &Disp) const {
580 // Register 0 means "no base". This is mostly useful for shifts.
581 Base = CurDAG->getRegister(0, VT);
582 else if (Base.getOpcode() == ISD::FrameIndex) {
583 // Lower a FrameIndex to a TargetFrameIndex.
584 int64_t FrameIndex = cast<FrameIndexSDNode>(Base)->getIndex();
585 Base = CurDAG->getTargetFrameIndex(FrameIndex, VT);
586 } else if (Base.getValueType() != VT) {
587 // Truncate values from i64 to i32, for shifts.
588 assert(VT == MVT::i32 && Base.getValueType() == MVT::i64 &&
589 "Unexpected truncation");
591 SDValue Trunc = CurDAG->getNode(ISD::TRUNCATE, DL, VT, Base);
592 insertDAGNode(CurDAG, Base.getNode(), Trunc);
596 // Lower the displacement to a TargetConstant.
597 Disp = CurDAG->getTargetConstant(AM.Disp, VT);
600 void SystemZDAGToDAGISel::getAddressOperands(const SystemZAddressingMode &AM,
601 EVT VT, SDValue &Base,
603 SDValue &Index) const {
604 getAddressOperands(AM, VT, Base, Disp);
607 if (!Index.getNode())
608 // Register 0 means "no index".
609 Index = CurDAG->getRegister(0, VT);
612 bool SystemZDAGToDAGISel::selectBDAddr(SystemZAddressingMode::DispRange DR,
613 SDValue Addr, SDValue &Base,
614 SDValue &Disp) const {
615 SystemZAddressingMode AM(SystemZAddressingMode::FormBD, DR);
616 if (!selectAddress(Addr, AM))
619 getAddressOperands(AM, Addr.getValueType(), Base, Disp);
623 bool SystemZDAGToDAGISel::selectMVIAddr(SystemZAddressingMode::DispRange DR,
624 SDValue Addr, SDValue &Base,
625 SDValue &Disp) const {
626 SystemZAddressingMode AM(SystemZAddressingMode::FormBDXNormal, DR);
627 if (!selectAddress(Addr, AM) || AM.Index.getNode())
630 getAddressOperands(AM, Addr.getValueType(), Base, Disp);
634 bool SystemZDAGToDAGISel::selectBDXAddr(SystemZAddressingMode::AddrForm Form,
635 SystemZAddressingMode::DispRange DR,
636 SDValue Addr, SDValue &Base,
637 SDValue &Disp, SDValue &Index) const {
638 SystemZAddressingMode AM(Form, DR);
639 if (!selectAddress(Addr, AM))
642 getAddressOperands(AM, Addr.getValueType(), Base, Disp, Index);
646 bool SystemZDAGToDAGISel::detectOrAndInsertion(SDValue &Op,
647 uint64_t InsertMask) const {
648 // We're only interested in cases where the insertion is into some operand
649 // of Op, rather than into Op itself. The only useful case is an AND.
650 if (Op.getOpcode() != ISD::AND)
653 // We need a constant mask.
654 ConstantSDNode *MaskNode =
655 dyn_cast<ConstantSDNode>(Op.getOperand(1).getNode());
659 // It's not an insertion of Op.getOperand(0) if the two masks overlap.
660 uint64_t AndMask = MaskNode->getZExtValue();
661 if (InsertMask & AndMask)
664 // It's only an insertion if all bits are covered or are known to be zero.
665 // The inner check covers all cases but is more expensive.
666 uint64_t Used = allOnes(Op.getValueType().getSizeInBits());
667 if (Used != (AndMask | InsertMask)) {
668 APInt KnownZero, KnownOne;
669 CurDAG->ComputeMaskedBits(Op.getOperand(0), KnownZero, KnownOne);
670 if (Used != (AndMask | InsertMask | KnownZero.getZExtValue()))
674 Op = Op.getOperand(0);
678 bool SystemZDAGToDAGISel::refineRxSBGMask(RxSBGOperands &RxSBG,
679 uint64_t Mask) const {
680 const SystemZInstrInfo *TII = getInstrInfo();
681 if (RxSBG.Rotate != 0)
682 Mask = (Mask << RxSBG.Rotate) | (Mask >> (64 - RxSBG.Rotate));
684 if (TII->isRxSBGMask(Mask, RxSBG.BitSize, RxSBG.Start, RxSBG.End)) {
691 // RxSBG.Input is a shift of Count bits in the direction given by IsLeft.
692 // Return true if the result depends on the signs or zeros that are
694 static bool shiftedInBitsMatter(RxSBGOperands &RxSBG, uint64_t Count,
696 // Work out which bits of the shift result are zeros or sign copies.
697 uint64_t ShiftedIn = allOnes(Count);
699 ShiftedIn <<= RxSBG.BitSize - Count;
701 // Rotate that mask in the same way as RxSBG.Input is rotated.
702 if (RxSBG.Rotate != 0)
703 ShiftedIn = ((ShiftedIn << RxSBG.Rotate) |
704 (ShiftedIn >> (64 - RxSBG.Rotate)));
706 // Fail if any of the zero or sign bits are used.
707 return (ShiftedIn & RxSBG.Mask) != 0;
710 bool SystemZDAGToDAGISel::expandRxSBG(RxSBGOperands &RxSBG) const {
711 SDValue N = RxSBG.Input;
712 unsigned Opcode = N.getOpcode();
715 if (RxSBG.Opcode == SystemZ::RNSBG)
718 ConstantSDNode *MaskNode =
719 dyn_cast<ConstantSDNode>(N.getOperand(1).getNode());
723 SDValue Input = N.getOperand(0);
724 uint64_t Mask = MaskNode->getZExtValue();
725 if (!refineRxSBGMask(RxSBG, Mask)) {
726 // If some bits of Input are already known zeros, those bits will have
727 // been removed from the mask. See if adding them back in makes the
729 APInt KnownZero, KnownOne;
730 CurDAG->ComputeMaskedBits(Input, KnownZero, KnownOne);
731 Mask |= KnownZero.getZExtValue();
732 if (!refineRxSBGMask(RxSBG, Mask))
740 if (RxSBG.Opcode != SystemZ::RNSBG)
743 ConstantSDNode *MaskNode =
744 dyn_cast<ConstantSDNode>(N.getOperand(1).getNode());
748 SDValue Input = N.getOperand(0);
749 uint64_t Mask = ~MaskNode->getZExtValue();
750 if (!refineRxSBGMask(RxSBG, Mask)) {
751 // If some bits of Input are already known ones, those bits will have
752 // been removed from the mask. See if adding them back in makes the
754 APInt KnownZero, KnownOne;
755 CurDAG->ComputeMaskedBits(Input, KnownZero, KnownOne);
756 Mask &= ~KnownOne.getZExtValue();
757 if (!refineRxSBGMask(RxSBG, Mask))
765 // Any 64-bit rotate left can be merged into the RxSBG.
766 if (RxSBG.BitSize != 64 || N.getValueType() != MVT::i64)
768 ConstantSDNode *CountNode
769 = dyn_cast<ConstantSDNode>(N.getOperand(1).getNode());
773 RxSBG.Rotate = (RxSBG.Rotate + CountNode->getZExtValue()) & 63;
774 RxSBG.Input = N.getOperand(0);
778 case ISD::SIGN_EXTEND:
779 case ISD::ZERO_EXTEND:
780 case ISD::ANY_EXTEND: {
781 // Check that the extension bits are don't-care (i.e. are masked out
782 // by the final mask).
783 unsigned InnerBitSize = N.getOperand(0).getValueType().getSizeInBits();
784 if (shiftedInBitsMatter(RxSBG, RxSBG.BitSize - InnerBitSize, false))
787 RxSBG.Input = N.getOperand(0);
792 ConstantSDNode *CountNode =
793 dyn_cast<ConstantSDNode>(N.getOperand(1).getNode());
797 uint64_t Count = CountNode->getZExtValue();
798 unsigned BitSize = N.getValueType().getSizeInBits();
799 if (Count < 1 || Count >= BitSize)
802 if (RxSBG.Opcode == SystemZ::RNSBG) {
803 // Treat (shl X, count) as (rotl X, size-count) as long as the bottom
804 // count bits from RxSBG.Input are ignored.
805 if (shiftedInBitsMatter(RxSBG, Count, true))
808 // Treat (shl X, count) as (and (rotl X, count), ~0<<count).
809 if (!refineRxSBGMask(RxSBG, allOnes(BitSize - Count) << Count))
813 RxSBG.Rotate = (RxSBG.Rotate + Count) & 63;
814 RxSBG.Input = N.getOperand(0);
820 ConstantSDNode *CountNode =
821 dyn_cast<ConstantSDNode>(N.getOperand(1).getNode());
825 uint64_t Count = CountNode->getZExtValue();
826 unsigned BitSize = N.getValueType().getSizeInBits();
827 if (Count < 1 || Count >= BitSize)
830 if (RxSBG.Opcode == SystemZ::RNSBG || Opcode == ISD::SRA) {
831 // Treat (srl|sra X, count) as (rotl X, size-count) as long as the top
832 // count bits from RxSBG.Input are ignored.
833 if (shiftedInBitsMatter(RxSBG, Count, false))
836 // Treat (srl X, count), mask) as (and (rotl X, size-count), ~0>>count),
837 // which is similar to SLL above.
838 if (!refineRxSBGMask(RxSBG, allOnes(BitSize - Count)))
842 RxSBG.Rotate = (RxSBG.Rotate - Count) & 63;
843 RxSBG.Input = N.getOperand(0);
851 SDValue SystemZDAGToDAGISel::getUNDEF(SDLoc DL, EVT VT) const {
852 SDNode *N = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, VT);
853 return SDValue(N, 0);
856 SDValue SystemZDAGToDAGISel::convertTo(SDLoc DL, EVT VT, SDValue N) const {
857 if (N.getValueType() == MVT::i32 && VT == MVT::i64)
858 return CurDAG->getTargetInsertSubreg(SystemZ::subreg_l32,
859 DL, VT, getUNDEF(DL, MVT::i64), N);
860 if (N.getValueType() == MVT::i64 && VT == MVT::i32)
861 return CurDAG->getTargetExtractSubreg(SystemZ::subreg_l32, DL, VT, N);
862 assert(N.getValueType() == VT && "Unexpected value types");
866 SDNode *SystemZDAGToDAGISel::tryRISBGZero(SDNode *N) {
867 EVT VT = N->getValueType(0);
868 RxSBGOperands RISBG(SystemZ::RISBG, SDValue(N, 0));
870 while (expandRxSBG(RISBG))
871 if (RISBG.Input.getOpcode() != ISD::ANY_EXTEND)
876 // Prefer to use normal shift instructions over RISBG, since they can handle
877 // all cases and are sometimes shorter.
878 if (N->getOpcode() != ISD::AND)
881 // Prefer register extensions like LLC over RISBG. Also prefer to start
882 // out with normal ANDs if one instruction would be enough. We can convert
883 // these ANDs into an RISBG later if a three-address instruction is useful.
884 if (VT == MVT::i32 ||
885 RISBG.Mask == 0xff ||
886 RISBG.Mask == 0xffff ||
887 SystemZ::isImmLF(~RISBG.Mask) ||
888 SystemZ::isImmHF(~RISBG.Mask)) {
889 // Force the new mask into the DAG, since it may include known-one bits.
890 ConstantSDNode *MaskN = cast<ConstantSDNode>(N->getOperand(1).getNode());
891 if (MaskN->getZExtValue() != RISBG.Mask) {
892 SDValue NewMask = CurDAG->getConstant(RISBG.Mask, VT);
893 N = CurDAG->UpdateNodeOperands(N, N->getOperand(0), NewMask);
894 return SelectCode(N);
900 unsigned Opcode = SystemZ::RISBG;
901 EVT OpcodeVT = MVT::i64;
902 if (VT == MVT::i32 && Subtarget.hasHighWord()) {
903 Opcode = SystemZ::RISBMux;
909 getUNDEF(SDLoc(N), OpcodeVT),
910 convertTo(SDLoc(N), OpcodeVT, RISBG.Input),
911 CurDAG->getTargetConstant(RISBG.Start, MVT::i32),
912 CurDAG->getTargetConstant(RISBG.End | 128, MVT::i32),
913 CurDAG->getTargetConstant(RISBG.Rotate, MVT::i32)
915 N = CurDAG->getMachineNode(Opcode, SDLoc(N), OpcodeVT, Ops);
916 return convertTo(SDLoc(N), VT, SDValue(N, 0)).getNode();
919 SDNode *SystemZDAGToDAGISel::tryRxSBG(SDNode *N, unsigned Opcode) {
920 // Try treating each operand of N as the second operand of the RxSBG
921 // and see which goes deepest.
922 RxSBGOperands RxSBG[] = {
923 RxSBGOperands(Opcode, N->getOperand(0)),
924 RxSBGOperands(Opcode, N->getOperand(1))
926 unsigned Count[] = { 0, 0 };
927 for (unsigned I = 0; I < 2; ++I)
928 while (expandRxSBG(RxSBG[I]))
929 if (RxSBG[I].Input.getOpcode() != ISD::ANY_EXTEND)
932 // Do nothing if neither operand is suitable.
933 if (Count[0] == 0 && Count[1] == 0)
936 // Pick the deepest second operand.
937 unsigned I = Count[0] > Count[1] ? 0 : 1;
938 SDValue Op0 = N->getOperand(I ^ 1);
940 // Prefer IC for character insertions from memory.
941 if (Opcode == SystemZ::ROSBG && (RxSBG[I].Mask & 0xff) == 0)
942 if (LoadSDNode *Load = dyn_cast<LoadSDNode>(Op0.getNode()))
943 if (Load->getMemoryVT() == MVT::i8)
946 // See whether we can avoid an AND in the first operand by converting
948 if (Opcode == SystemZ::ROSBG && detectOrAndInsertion(Op0, RxSBG[I].Mask))
949 Opcode = SystemZ::RISBG;
951 EVT VT = N->getValueType(0);
953 convertTo(SDLoc(N), MVT::i64, Op0),
954 convertTo(SDLoc(N), MVT::i64, RxSBG[I].Input),
955 CurDAG->getTargetConstant(RxSBG[I].Start, MVT::i32),
956 CurDAG->getTargetConstant(RxSBG[I].End, MVT::i32),
957 CurDAG->getTargetConstant(RxSBG[I].Rotate, MVT::i32)
959 N = CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i64, Ops);
960 return convertTo(SDLoc(N), VT, SDValue(N, 0)).getNode();
963 SDNode *SystemZDAGToDAGISel::splitLargeImmediate(unsigned Opcode, SDNode *Node,
964 SDValue Op0, uint64_t UpperVal,
966 EVT VT = Node->getValueType(0);
968 SDValue Upper = CurDAG->getConstant(UpperVal, VT);
970 Upper = CurDAG->getNode(Opcode, DL, VT, Op0, Upper);
971 Upper = SDValue(Select(Upper.getNode()), 0);
973 SDValue Lower = CurDAG->getConstant(LowerVal, VT);
974 SDValue Or = CurDAG->getNode(Opcode, DL, VT, Upper, Lower);
978 bool SystemZDAGToDAGISel::canUseBlockOperation(StoreSDNode *Store,
979 LoadSDNode *Load) const {
980 // Check that the two memory operands have the same size.
981 if (Load->getMemoryVT() != Store->getMemoryVT())
984 // Volatility stops an access from being decomposed.
985 if (Load->isVolatile() || Store->isVolatile())
988 // There's no chance of overlap if the load is invariant.
989 if (Load->isInvariant())
992 // Otherwise we need to check whether there's an alias.
993 const Value *V1 = Load->getSrcValue();
994 const Value *V2 = Store->getSrcValue();
999 uint64_t Size = Load->getMemoryVT().getStoreSize();
1000 int64_t End1 = Load->getSrcValueOffset() + Size;
1001 int64_t End2 = Store->getSrcValueOffset() + Size;
1002 if (V1 == V2 && End1 == End2)
1005 return !AA->alias(AliasAnalysis::Location(V1, End1, Load->getTBAAInfo()),
1006 AliasAnalysis::Location(V2, End2, Store->getTBAAInfo()));
1009 bool SystemZDAGToDAGISel::storeLoadCanUseMVC(SDNode *N) const {
1010 StoreSDNode *Store = cast<StoreSDNode>(N);
1011 LoadSDNode *Load = cast<LoadSDNode>(Store->getValue());
1013 // Prefer not to use MVC if either address can use ... RELATIVE LONG
1015 uint64_t Size = Load->getMemoryVT().getStoreSize();
1016 if (Size > 1 && Size <= 8) {
1017 // Prefer LHRL, LRL and LGRL.
1018 if (SystemZISD::isPCREL(Load->getBasePtr().getOpcode()))
1020 // Prefer STHRL, STRL and STGRL.
1021 if (SystemZISD::isPCREL(Store->getBasePtr().getOpcode()))
1025 return canUseBlockOperation(Store, Load);
1028 bool SystemZDAGToDAGISel::storeLoadCanUseBlockBinary(SDNode *N,
1030 StoreSDNode *StoreA = cast<StoreSDNode>(N);
1031 LoadSDNode *LoadA = cast<LoadSDNode>(StoreA->getValue().getOperand(1 - I));
1032 LoadSDNode *LoadB = cast<LoadSDNode>(StoreA->getValue().getOperand(I));
1033 return !LoadA->isVolatile() && canUseBlockOperation(StoreA, LoadB);
1036 SDNode *SystemZDAGToDAGISel::Select(SDNode *Node) {
1037 // Dump information about the Node being selected
1038 DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
1040 // If we have a custom node, we already have selected!
1041 if (Node->isMachineOpcode()) {
1042 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
1043 Node->setNodeId(-1);
1047 unsigned Opcode = Node->getOpcode();
1048 SDNode *ResNode = 0;
1051 if (Node->getOperand(1).getOpcode() != ISD::Constant)
1052 ResNode = tryRxSBG(Node, SystemZ::ROSBG);
1056 if (Node->getOperand(1).getOpcode() != ISD::Constant)
1057 ResNode = tryRxSBG(Node, SystemZ::RXSBG);
1060 // If this is a 64-bit operation in which both 32-bit halves are nonzero,
1061 // split the operation into two.
1062 if (!ResNode && Node->getValueType(0) == MVT::i64)
1063 if (ConstantSDNode *Op1 = dyn_cast<ConstantSDNode>(Node->getOperand(1))) {
1064 uint64_t Val = Op1->getZExtValue();
1065 if (!SystemZ::isImmLF(Val) && !SystemZ::isImmHF(Val))
1066 Node = splitLargeImmediate(Opcode, Node, Node->getOperand(0),
1067 Val - uint32_t(Val), uint32_t(Val));
1072 if (Node->getOperand(1).getOpcode() != ISD::Constant)
1073 ResNode = tryRxSBG(Node, SystemZ::RNSBG);
1079 ResNode = tryRISBGZero(Node);
1083 // If this is a 64-bit constant that is out of the range of LLILF,
1084 // LLIHF and LGFI, split it into two 32-bit pieces.
1085 if (Node->getValueType(0) == MVT::i64) {
1086 uint64_t Val = cast<ConstantSDNode>(Node)->getZExtValue();
1087 if (!SystemZ::isImmLF(Val) && !SystemZ::isImmHF(Val) && !isInt<32>(Val))
1088 Node = splitLargeImmediate(ISD::OR, Node, SDValue(),
1089 Val - uint32_t(Val), uint32_t(Val));
1093 case ISD::ATOMIC_LOAD_SUB:
1094 // Try to convert subtractions of constants to additions.
1095 if (ConstantSDNode *Op2 = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
1096 uint64_t Value = -Op2->getZExtValue();
1097 EVT VT = Node->getValueType(0);
1098 if (VT == MVT::i32 || isInt<32>(Value)) {
1099 SDValue Ops[] = { Node->getOperand(0), Node->getOperand(1),
1100 CurDAG->getConstant(int32_t(Value), VT) };
1101 Node = CurDAG->MorphNodeTo(Node, ISD::ATOMIC_LOAD_ADD,
1102 Node->getVTList(), Ops, array_lengthof(Ops));
1107 case SystemZISD::SELECT_CCMASK: {
1108 SDValue Op0 = Node->getOperand(0);
1109 SDValue Op1 = Node->getOperand(1);
1110 // Prefer to put any load first, so that it can be matched as a
1111 // conditional load.
1112 if (Op1.getOpcode() == ISD::LOAD && Op0.getOpcode() != ISD::LOAD) {
1113 SDValue CCValid = Node->getOperand(2);
1114 SDValue CCMask = Node->getOperand(3);
1115 uint64_t ConstCCValid =
1116 cast<ConstantSDNode>(CCValid.getNode())->getZExtValue();
1117 uint64_t ConstCCMask =
1118 cast<ConstantSDNode>(CCMask.getNode())->getZExtValue();
1119 // Invert the condition.
1120 CCMask = CurDAG->getConstant(ConstCCValid ^ ConstCCMask,
1121 CCMask.getValueType());
1122 SDValue Op4 = Node->getOperand(4);
1123 Node = CurDAG->UpdateNodeOperands(Node, Op1, Op0, CCValid, CCMask, Op4);
1129 // Select the default instruction
1131 ResNode = SelectCode(Node);
1133 DEBUG(errs() << "=> ";
1134 if (ResNode == NULL || ResNode == Node)
1137 ResNode->dump(CurDAG);
1143 bool SystemZDAGToDAGISel::
1144 SelectInlineAsmMemoryOperand(const SDValue &Op,
1145 char ConstraintCode,
1146 std::vector<SDValue> &OutOps) {
1147 assert(ConstraintCode == 'm' && "Unexpected constraint code");
1148 // Accept addresses with short displacements, which are compatible
1149 // with Q, R, S and T. But keep the index operand for future expansion.
1150 SDValue Base, Disp, Index;
1151 if (!selectBDXAddr(SystemZAddressingMode::FormBD,
1152 SystemZAddressingMode::Disp12Only,
1153 Op, Base, Disp, Index))
1155 OutOps.push_back(Base);
1156 OutOps.push_back(Disp);
1157 OutOps.push_back(Index);