1 //==-- SystemZISelDAGToDAG.cpp - A dag to dag inst selector for SystemZ ---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the SystemZ target.
12 //===----------------------------------------------------------------------===//
15 #include "SystemZISelLowering.h"
16 #include "SystemZTargetMachine.h"
17 #include "llvm/DerivedTypes.h"
18 #include "llvm/Function.h"
19 #include "llvm/Intrinsics.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/SelectionDAGISel.h"
28 #include "llvm/Target/TargetLowering.h"
29 #include "llvm/Support/Compiler.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/raw_ostream.h"
34 static const unsigned subreg_even32 = 1;
35 static const unsigned subreg_odd32 = 2;
36 static const unsigned subreg_even = 3;
37 static const unsigned subreg_odd = 4;
40 /// SystemZRRIAddressMode - This corresponds to rriaddr, but uses SDValue's
41 /// instead of register numbers for the leaves of the matched tree.
42 struct SystemZRRIAddressMode {
48 struct { // This is really a union, discriminated by BaseType!
57 SystemZRRIAddressMode(bool RI = false)
58 : BaseType(RegBase), IndexReg(), Disp(0), isRI(RI) {
62 errs() << "SystemZRRIAddressMode " << this << '\n';
63 if (BaseType == RegBase) {
64 errs() << "Base.Reg ";
65 if (Base.Reg.getNode() != 0)
66 Base.Reg.getNode()->dump();
71 errs() << " Base.FrameIndex " << Base.FrameIndex << '\n';
74 errs() << "IndexReg ";
75 if (IndexReg.getNode() != 0) IndexReg.getNode()->dump();
78 errs() << " Disp " << Disp << '\n';
83 /// SystemZDAGToDAGISel - SystemZ specific code to select SystemZ machine
84 /// instructions for SelectionDAG operations.
87 class SystemZDAGToDAGISel : public SelectionDAGISel {
88 SystemZTargetLowering &Lowering;
89 const SystemZSubtarget &Subtarget;
91 void getAddressOperandsRI(const SystemZRRIAddressMode &AM,
92 SDValue &Base, SDValue &Disp);
93 void getAddressOperands(const SystemZRRIAddressMode &AM,
94 SDValue &Base, SDValue &Disp,
98 SystemZDAGToDAGISel(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel)
99 : SelectionDAGISel(TM, OptLevel),
100 Lowering(*TM.getTargetLowering()),
101 Subtarget(*TM.getSubtargetImpl()) { }
103 virtual const char *getPassName() const {
104 return "SystemZ DAG->DAG Pattern Instruction Selection";
107 /// getI8Imm - Return a target constant with the specified value, of type
109 inline SDValue getI8Imm(uint64_t Imm) {
110 return CurDAG->getTargetConstant(Imm, MVT::i8);
113 /// getI16Imm - Return a target constant with the specified value, of type
115 inline SDValue getI16Imm(uint64_t Imm) {
116 return CurDAG->getTargetConstant(Imm, MVT::i16);
119 /// getI32Imm - Return a target constant with the specified value, of type
121 inline SDValue getI32Imm(uint64_t Imm) {
122 return CurDAG->getTargetConstant(Imm, MVT::i32);
125 // Include the pieces autogenerated from the target description.
126 #include "SystemZGenDAGISel.inc"
129 bool SelectAddrRI12Only(SDNode *Op, SDValue& Addr,
130 SDValue &Base, SDValue &Disp);
131 bool SelectAddrRI12(SDNode *Op, SDValue& Addr,
132 SDValue &Base, SDValue &Disp,
133 bool is12BitOnly = false);
134 bool SelectAddrRI(SDNode *Op, SDValue& Addr,
135 SDValue &Base, SDValue &Disp);
136 bool SelectAddrRRI12(SDNode *Op, SDValue Addr,
137 SDValue &Base, SDValue &Disp, SDValue &Index);
138 bool SelectAddrRRI20(SDNode *Op, SDValue Addr,
139 SDValue &Base, SDValue &Disp, SDValue &Index);
140 bool SelectLAAddr(SDNode *Op, SDValue Addr,
141 SDValue &Base, SDValue &Disp, SDValue &Index);
143 SDNode *Select(SDNode *Node);
145 bool TryFoldLoad(SDNode *P, SDValue N,
146 SDValue &Base, SDValue &Disp, SDValue &Index);
148 bool MatchAddress(SDValue N, SystemZRRIAddressMode &AM,
149 bool is12Bit, unsigned Depth = 0);
150 bool MatchAddressBase(SDValue N, SystemZRRIAddressMode &AM);
151 bool MatchAddressRI(SDValue N, SystemZRRIAddressMode &AM,
154 } // end anonymous namespace
156 /// createSystemZISelDag - This pass converts a legalized DAG into a
157 /// SystemZ-specific DAG, ready for instruction scheduling.
159 FunctionPass *llvm::createSystemZISelDag(SystemZTargetMachine &TM,
160 CodeGenOpt::Level OptLevel) {
161 return new SystemZDAGToDAGISel(TM, OptLevel);
164 /// isImmSExt20 - This method tests to see if the node is either a 32-bit
165 /// or 64-bit immediate, and if the value can be accurately represented as a
166 /// sign extension from a 20-bit value. If so, this returns true and the
168 static bool isImmSExt20(int64_t Val, int64_t &Imm) {
169 if (Val >= -524288 && Val <= 524287) {
176 /// isImmZExt12 - This method tests to see if the node is either a 32-bit
177 /// or 64-bit immediate, and if the value can be accurately represented as a
178 /// zero extension from a 12-bit value. If so, this returns true and the
180 static bool isImmZExt12(int64_t Val, int64_t &Imm) {
181 if (Val >= 0 && Val <= 0xFFF) {
188 /// MatchAddress - Add the specified node to the specified addressing mode,
189 /// returning true if it cannot be done. This just pattern matches for the
191 bool SystemZDAGToDAGISel::MatchAddress(SDValue N, SystemZRRIAddressMode &AM,
192 bool is12Bit, unsigned Depth) {
193 DebugLoc dl = N.getDebugLoc();
194 DEBUG(errs() << "MatchAddress: "; AM.dump());
197 return MatchAddressBase(N, AM);
199 // FIXME: We can perform better here. If we have something like
200 // (shift (add A, imm), N), we can try to reassociate stuff and fold shift of
201 // imm into addressing mode.
202 switch (N.getOpcode()) {
204 case ISD::Constant: {
205 int64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
207 bool Match = (is12Bit ?
208 isImmZExt12(AM.Disp + Val, Imm) :
209 isImmSExt20(AM.Disp + Val, Imm));
217 case ISD::FrameIndex:
218 if (AM.BaseType == SystemZRRIAddressMode::RegBase &&
219 AM.Base.Reg.getNode() == 0) {
220 AM.BaseType = SystemZRRIAddressMode::FrameIndexBase;
221 AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
227 // Given A-B, if A can be completely folded into the address and
228 // the index field with the index field unused, use -B as the index.
229 // This is a win if a has multiple parts that can be folded into
230 // the address. Also, this saves a mov if the base register has
231 // other uses, since it avoids a two-address sub instruction, however
232 // it costs an additional mov if the index register has other uses.
234 // Test if the LHS of the sub can be folded.
235 SystemZRRIAddressMode Backup = AM;
236 if (MatchAddress(N.getNode()->getOperand(0), AM, is12Bit, Depth+1)) {
240 // Test if the index field is free for use.
241 if (AM.IndexReg.getNode() || AM.isRI) {
246 // If the base is a register with multiple uses, this transformation may
247 // save a mov. Otherwise it's probably better not to do it.
248 if (AM.BaseType == SystemZRRIAddressMode::RegBase &&
249 (!AM.Base.Reg.getNode() || AM.Base.Reg.getNode()->hasOneUse())) {
254 // Ok, the transformation is legal and appears profitable. Go for it.
255 SDValue RHS = N.getNode()->getOperand(1);
256 SDValue Zero = CurDAG->getConstant(0, N.getValueType());
257 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS);
260 // Insert the new nodes into the topological ordering.
261 if (Zero.getNode()->getNodeId() == -1 ||
262 Zero.getNode()->getNodeId() > N.getNode()->getNodeId()) {
263 CurDAG->RepositionNode(N.getNode(), Zero.getNode());
264 Zero.getNode()->setNodeId(N.getNode()->getNodeId());
266 if (Neg.getNode()->getNodeId() == -1 ||
267 Neg.getNode()->getNodeId() > N.getNode()->getNodeId()) {
268 CurDAG->RepositionNode(N.getNode(), Neg.getNode());
269 Neg.getNode()->setNodeId(N.getNode()->getNodeId());
275 SystemZRRIAddressMode Backup = AM;
276 if (!MatchAddress(N.getNode()->getOperand(0), AM, is12Bit, Depth+1) &&
277 !MatchAddress(N.getNode()->getOperand(1), AM, is12Bit, Depth+1))
280 if (!MatchAddress(N.getNode()->getOperand(1), AM, is12Bit, Depth+1) &&
281 !MatchAddress(N.getNode()->getOperand(0), AM, is12Bit, Depth+1))
285 // If we couldn't fold both operands into the address at the same time,
286 // see if we can just put each operand into a register and fold at least
289 AM.BaseType == SystemZRRIAddressMode::RegBase &&
290 !AM.Base.Reg.getNode() && !AM.IndexReg.getNode()) {
291 AM.Base.Reg = N.getNode()->getOperand(0);
292 AM.IndexReg = N.getNode()->getOperand(1);
299 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
300 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
301 SystemZRRIAddressMode Backup = AM;
302 int64_t Offset = CN->getSExtValue();
304 bool MatchOffset = (is12Bit ?
305 isImmZExt12(AM.Disp + Offset, Imm) :
306 isImmSExt20(AM.Disp + Offset, Imm));
307 // The resultant disp must fit in 12 or 20-bits.
309 // LHS should be an addr mode.
310 !MatchAddress(N.getOperand(0), AM, is12Bit, Depth+1) &&
311 // Check to see if the LHS & C is zero.
312 CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
321 return MatchAddressBase(N, AM);
324 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
325 /// specified addressing mode without any further recursion.
326 bool SystemZDAGToDAGISel::MatchAddressBase(SDValue N,
327 SystemZRRIAddressMode &AM) {
328 // Is the base register already occupied?
329 if (AM.BaseType != SystemZRRIAddressMode::RegBase || AM.Base.Reg.getNode()) {
330 // If so, check to see if the index register is set.
331 if (AM.IndexReg.getNode() == 0 && !AM.isRI) {
336 // Otherwise, we cannot select it.
340 // Default, generate it as a register.
341 AM.BaseType = SystemZRRIAddressMode::RegBase;
346 void SystemZDAGToDAGISel::getAddressOperandsRI(const SystemZRRIAddressMode &AM,
347 SDValue &Base, SDValue &Disp) {
348 if (AM.BaseType == SystemZRRIAddressMode::RegBase)
351 Base = CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy());
352 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i64);
355 void SystemZDAGToDAGISel::getAddressOperands(const SystemZRRIAddressMode &AM,
356 SDValue &Base, SDValue &Disp,
358 getAddressOperandsRI(AM, Base, Disp);
362 /// Returns true if the address can be represented by a base register plus
363 /// an unsigned 12-bit displacement [r+imm].
364 bool SystemZDAGToDAGISel::SelectAddrRI12Only(SDNode *Op, SDValue& Addr,
365 SDValue &Base, SDValue &Disp) {
366 return SelectAddrRI12(Op, Addr, Base, Disp, /*is12BitOnly*/true);
369 bool SystemZDAGToDAGISel::SelectAddrRI12(SDNode *Op, SDValue& Addr,
370 SDValue &Base, SDValue &Disp,
372 SystemZRRIAddressMode AM20(/*isRI*/true), AM12(/*isRI*/true);
375 if (!Addr.hasOneUse()) {
376 unsigned Opcode = Addr.getOpcode();
377 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) {
378 // If we are able to fold N into addressing mode, then we'll allow it even
379 // if N has multiple uses. In general, addressing computation is used as
380 // addresses by all of its uses. But watch out for CopyToReg uses, that
381 // means the address computation is liveout. It will be computed by a LA
382 // so we want to avoid computing the address twice.
383 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
384 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
385 if (UI->getOpcode() == ISD::CopyToReg) {
386 MatchAddressBase(Addr, AM12);
393 if (!Done && MatchAddress(Addr, AM12, /* is12Bit */ true))
396 // Check, whether we can match stuff using 20-bit displacements
397 if (!Done && !is12BitOnly &&
398 !MatchAddress(Addr, AM20, /* is12Bit */ false))
399 if (AM12.Disp == 0 && AM20.Disp != 0)
402 DEBUG(errs() << "MatchAddress (final): "; AM12.dump());
404 EVT VT = Addr.getValueType();
405 if (AM12.BaseType == SystemZRRIAddressMode::RegBase) {
406 if (!AM12.Base.Reg.getNode())
407 AM12.Base.Reg = CurDAG->getRegister(0, VT);
410 assert(AM12.IndexReg.getNode() == 0 && "Invalid reg-imm address mode!");
412 getAddressOperandsRI(AM12, Base, Disp);
417 /// Returns true if the address can be represented by a base register plus
418 /// a signed 20-bit displacement [r+imm].
419 bool SystemZDAGToDAGISel::SelectAddrRI(SDNode *Op, SDValue& Addr,
420 SDValue &Base, SDValue &Disp) {
421 SystemZRRIAddressMode AM(/*isRI*/true);
424 if (!Addr.hasOneUse()) {
425 unsigned Opcode = Addr.getOpcode();
426 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) {
427 // If we are able to fold N into addressing mode, then we'll allow it even
428 // if N has multiple uses. In general, addressing computation is used as
429 // addresses by all of its uses. But watch out for CopyToReg uses, that
430 // means the address computation is liveout. It will be computed by a LA
431 // so we want to avoid computing the address twice.
432 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
433 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
434 if (UI->getOpcode() == ISD::CopyToReg) {
435 MatchAddressBase(Addr, AM);
442 if (!Done && MatchAddress(Addr, AM, /* is12Bit */ false))
445 DEBUG(errs() << "MatchAddress (final): "; AM.dump());
447 EVT VT = Addr.getValueType();
448 if (AM.BaseType == SystemZRRIAddressMode::RegBase) {
449 if (!AM.Base.Reg.getNode())
450 AM.Base.Reg = CurDAG->getRegister(0, VT);
453 assert(AM.IndexReg.getNode() == 0 && "Invalid reg-imm address mode!");
455 getAddressOperandsRI(AM, Base, Disp);
460 /// Returns true if the address can be represented by a base register plus
461 /// index register plus an unsigned 12-bit displacement [base + idx + imm].
462 bool SystemZDAGToDAGISel::SelectAddrRRI12(SDNode *Op, SDValue Addr,
463 SDValue &Base, SDValue &Disp, SDValue &Index) {
464 SystemZRRIAddressMode AM20, AM12;
467 if (!Addr.hasOneUse()) {
468 unsigned Opcode = Addr.getOpcode();
469 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) {
470 // If we are able to fold N into addressing mode, then we'll allow it even
471 // if N has multiple uses. In general, addressing computation is used as
472 // addresses by all of its uses. But watch out for CopyToReg uses, that
473 // means the address computation is liveout. It will be computed by a LA
474 // so we want to avoid computing the address twice.
475 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
476 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
477 if (UI->getOpcode() == ISD::CopyToReg) {
478 MatchAddressBase(Addr, AM12);
485 if (!Done && MatchAddress(Addr, AM12, /* is12Bit */ true))
488 // Check, whether we can match stuff using 20-bit displacements
489 if (!Done && !MatchAddress(Addr, AM20, /* is12Bit */ false))
490 if (AM12.Disp == 0 && AM20.Disp != 0)
493 DEBUG(errs() << "MatchAddress (final): "; AM12.dump());
495 EVT VT = Addr.getValueType();
496 if (AM12.BaseType == SystemZRRIAddressMode::RegBase) {
497 if (!AM12.Base.Reg.getNode())
498 AM12.Base.Reg = CurDAG->getRegister(0, VT);
501 if (!AM12.IndexReg.getNode())
502 AM12.IndexReg = CurDAG->getRegister(0, VT);
504 getAddressOperands(AM12, Base, Disp, Index);
509 /// Returns true if the address can be represented by a base register plus
510 /// index register plus a signed 20-bit displacement [base + idx + imm].
511 bool SystemZDAGToDAGISel::SelectAddrRRI20(SDNode *Op, SDValue Addr,
512 SDValue &Base, SDValue &Disp, SDValue &Index) {
513 SystemZRRIAddressMode AM;
516 if (!Addr.hasOneUse()) {
517 unsigned Opcode = Addr.getOpcode();
518 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) {
519 // If we are able to fold N into addressing mode, then we'll allow it even
520 // if N has multiple uses. In general, addressing computation is used as
521 // addresses by all of its uses. But watch out for CopyToReg uses, that
522 // means the address computation is liveout. It will be computed by a LA
523 // so we want to avoid computing the address twice.
524 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
525 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
526 if (UI->getOpcode() == ISD::CopyToReg) {
527 MatchAddressBase(Addr, AM);
534 if (!Done && MatchAddress(Addr, AM, /* is12Bit */ false))
537 DEBUG(errs() << "MatchAddress (final): "; AM.dump());
539 EVT VT = Addr.getValueType();
540 if (AM.BaseType == SystemZRRIAddressMode::RegBase) {
541 if (!AM.Base.Reg.getNode())
542 AM.Base.Reg = CurDAG->getRegister(0, VT);
545 if (!AM.IndexReg.getNode())
546 AM.IndexReg = CurDAG->getRegister(0, VT);
548 getAddressOperands(AM, Base, Disp, Index);
553 /// SelectLAAddr - it calls SelectAddr and determines if the maximal addressing
554 /// mode it matches can be cost effectively emitted as an LA/LAY instruction.
555 bool SystemZDAGToDAGISel::SelectLAAddr(SDNode *Op, SDValue Addr,
556 SDValue &Base, SDValue &Disp, SDValue &Index) {
557 SystemZRRIAddressMode AM;
559 if (MatchAddress(Addr, AM, false))
562 EVT VT = Addr.getValueType();
563 unsigned Complexity = 0;
564 if (AM.BaseType == SystemZRRIAddressMode::RegBase)
565 if (AM.Base.Reg.getNode())
568 AM.Base.Reg = CurDAG->getRegister(0, VT);
569 else if (AM.BaseType == SystemZRRIAddressMode::FrameIndexBase)
572 if (AM.IndexReg.getNode())
575 AM.IndexReg = CurDAG->getRegister(0, VT);
577 if (AM.Disp && (AM.Base.Reg.getNode() || AM.IndexReg.getNode()))
580 if (Complexity > 2) {
581 getAddressOperands(AM, Base, Disp, Index);
588 bool SystemZDAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N,
589 SDValue &Base, SDValue &Disp, SDValue &Index) {
590 if (ISD::isNON_EXTLoad(N.getNode()) &&
591 IsLegalToFold(N, P, P))
592 return SelectAddrRRI20(P, N.getOperand(1), Base, Disp, Index);
596 SDNode *SystemZDAGToDAGISel::Select(SDNode *Node) {
597 EVT NVT = Node->getValueType(0);
598 DebugLoc dl = Node->getDebugLoc();
599 unsigned Opcode = Node->getOpcode();
601 // Dump information about the Node being selected
602 DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
604 // If we have a custom node, we already have selected!
605 if (Node->isMachineOpcode()) {
606 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
607 return NULL; // Already selected.
614 SDValue N0 = Node->getOperand(0);
615 SDValue N1 = Node->getOperand(1);
618 bool is32Bit = false;
619 switch (NVT.getSimpleVT().SimpleTy) {
620 default: assert(0 && "Unsupported VT!");
622 Opc = SystemZ::SDIVREM32r; MOpc = SystemZ::SDIVREM32m;
627 Opc = SystemZ::SDIVREM64r; MOpc = SystemZ::SDIVREM64m;
632 SDValue Tmp0, Tmp1, Tmp2;
633 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2);
635 // Prepare the dividend
638 Dividend = CurDAG->getMachineNode(SystemZ::MOVSX64rr32, dl, MVT::i64, N0);
640 Dividend = N0.getNode();
642 // Insert prepared dividend into suitable 'subreg'
643 SDNode *Tmp = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
646 CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, dl, ResVT,
647 SDValue(Tmp, 0), SDValue(Dividend, 0),
648 CurDAG->getTargetConstant(subreg_odd, MVT::i32));
651 SDValue DivVal = SDValue(Dividend, 0);
653 SDValue Ops[] = { DivVal, Tmp0, Tmp1, Tmp2, N1.getOperand(0) };
654 Result = CurDAG->getMachineNode(MOpc, dl, ResVT, MVT::Other,
655 Ops, array_lengthof(Ops));
657 ReplaceUses(N1.getValue(1), SDValue(Result, 1));
659 Result = CurDAG->getMachineNode(Opc, dl, ResVT, SDValue(Dividend, 0), N1);
662 // Copy the division (odd subreg) result, if it is needed.
663 if (!SDValue(Node, 0).use_empty()) {
664 unsigned SubRegIdx = (is32Bit ? subreg_odd32 : subreg_odd);
665 SDNode *Div = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
668 CurDAG->getTargetConstant(SubRegIdx,
671 ReplaceUses(SDValue(Node, 0), SDValue(Div, 0));
672 DEBUG(errs() << "=> "; Result->dump(CurDAG); errs() << "\n");
675 // Copy the remainder (even subreg) result, if it is needed.
676 if (!SDValue(Node, 1).use_empty()) {
677 unsigned SubRegIdx = (is32Bit ? subreg_even32 : subreg_even);
678 SDNode *Rem = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
681 CurDAG->getTargetConstant(SubRegIdx,
684 ReplaceUses(SDValue(Node, 1), SDValue(Rem, 0));
685 DEBUG(errs() << "=> "; Result->dump(CurDAG); errs() << "\n");
691 unsigned Opc, MOpc, ClrOpc;
692 SDValue N0 = Node->getOperand(0);
693 SDValue N1 = Node->getOperand(1);
696 bool is32Bit = false;
697 switch (NVT.getSimpleVT().SimpleTy) {
698 default: assert(0 && "Unsupported VT!");
700 Opc = SystemZ::UDIVREM32r; MOpc = SystemZ::UDIVREM32m;
701 ClrOpc = SystemZ::MOV64Pr0_even;
706 Opc = SystemZ::UDIVREM64r; MOpc = SystemZ::UDIVREM64m;
707 ClrOpc = SystemZ::MOV128r0_even;
712 SDValue Tmp0, Tmp1, Tmp2;
713 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2);
715 // Prepare the dividend
716 SDNode *Dividend = N0.getNode();
718 // Insert prepared dividend into suitable 'subreg'
719 SDNode *Tmp = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
722 unsigned SubRegIdx = (is32Bit ? subreg_odd32 : subreg_odd);
724 CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, dl, ResVT,
725 SDValue(Tmp, 0), SDValue(Dividend, 0),
726 CurDAG->getTargetConstant(SubRegIdx, MVT::i32));
729 // Zero out even subreg
730 Dividend = CurDAG->getMachineNode(ClrOpc, dl, ResVT, SDValue(Dividend, 0));
732 SDValue DivVal = SDValue(Dividend, 0);
735 SDValue Ops[] = { DivVal, Tmp0, Tmp1, Tmp2, N1.getOperand(0) };
736 Result = CurDAG->getMachineNode(MOpc, dl, ResVT, MVT::Other,
737 Ops, array_lengthof(Ops));
739 ReplaceUses(N1.getValue(1), SDValue(Result, 1));
741 Result = CurDAG->getMachineNode(Opc, dl, ResVT, DivVal, N1);
744 // Copy the division (odd subreg) result, if it is needed.
745 if (!SDValue(Node, 0).use_empty()) {
746 unsigned SubRegIdx = (is32Bit ? subreg_odd32 : subreg_odd);
747 SDNode *Div = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
750 CurDAG->getTargetConstant(SubRegIdx,
752 ReplaceUses(SDValue(Node, 0), SDValue(Div, 0));
753 DEBUG(errs() << "=> "; Result->dump(CurDAG); errs() << "\n");
756 // Copy the remainder (even subreg) result, if it is needed.
757 if (!SDValue(Node, 1).use_empty()) {
758 unsigned SubRegIdx = (is32Bit ? subreg_even32 : subreg_even);
759 SDNode *Rem = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
762 CurDAG->getTargetConstant(SubRegIdx,
764 ReplaceUses(SDValue(Node, 1), SDValue(Rem, 0));
765 DEBUG(errs() << "=> "; Result->dump(CurDAG); errs() << "\n");
772 // Select the default instruction
773 SDNode *ResNode = SelectCode(Node);
775 DEBUG(errs() << "=> ";
776 if (ResNode == NULL || ResNode == Node)
779 ResNode->dump(CurDAG);