1 //==-- SystemZISelDAGToDAG.cpp - A dag to dag inst selector for SystemZ ---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the SystemZ target.
12 //===----------------------------------------------------------------------===//
15 #include "SystemZTargetMachine.h"
16 #include "llvm/DerivedTypes.h"
17 #include "llvm/Function.h"
18 #include "llvm/Intrinsics.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/Target/TargetLowering.h"
28 #include "llvm/Support/Compiler.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/raw_ostream.h"
34 /// SystemZRRIAddressMode - This corresponds to rriaddr, but uses SDValue's
35 /// instead of register numbers for the leaves of the matched tree.
36 struct SystemZRRIAddressMode {
42 struct { // This is really a union, discriminated by BaseType!
51 SystemZRRIAddressMode(bool RI = false)
52 : BaseType(RegBase), IndexReg(), Disp(0), isRI(RI) {
56 errs() << "SystemZRRIAddressMode " << this << '\n';
57 if (BaseType == RegBase) {
58 errs() << "Base.Reg ";
59 if (Base.Reg.getNode() != 0)
60 Base.Reg.getNode()->dump();
65 errs() << " Base.FrameIndex " << Base.FrameIndex << '\n';
68 errs() << "IndexReg ";
69 if (IndexReg.getNode() != 0) IndexReg.getNode()->dump();
72 errs() << " Disp " << Disp << '\n';
77 /// SystemZDAGToDAGISel - SystemZ specific code to select SystemZ machine
78 /// instructions for SelectionDAG operations.
81 class SystemZDAGToDAGISel : public SelectionDAGISel {
82 const SystemZTargetLowering &Lowering;
83 const SystemZSubtarget &Subtarget;
85 void getAddressOperandsRI(const SystemZRRIAddressMode &AM,
86 SDValue &Base, SDValue &Disp);
87 void getAddressOperands(const SystemZRRIAddressMode &AM,
88 SDValue &Base, SDValue &Disp,
92 SystemZDAGToDAGISel(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel)
93 : SelectionDAGISel(TM, OptLevel),
94 Lowering(*TM.getTargetLowering()),
95 Subtarget(*TM.getSubtargetImpl()) { }
97 virtual const char *getPassName() const {
98 return "SystemZ DAG->DAG Pattern Instruction Selection";
101 /// getI8Imm - Return a target constant with the specified value, of type
103 inline SDValue getI8Imm(uint64_t Imm) {
104 return CurDAG->getTargetConstant(Imm, MVT::i8);
107 /// getI16Imm - Return a target constant with the specified value, of type
109 inline SDValue getI16Imm(uint64_t Imm) {
110 return CurDAG->getTargetConstant(Imm, MVT::i16);
113 /// getI32Imm - Return a target constant with the specified value, of type
115 inline SDValue getI32Imm(uint64_t Imm) {
116 return CurDAG->getTargetConstant(Imm, MVT::i32);
119 // Include the pieces autogenerated from the target description.
120 #include "SystemZGenDAGISel.inc"
123 bool SelectAddrRI12Only(SDNode *Op, SDValue& Addr,
124 SDValue &Base, SDValue &Disp);
125 bool SelectAddrRI12(SDNode *Op, SDValue& Addr,
126 SDValue &Base, SDValue &Disp,
127 bool is12BitOnly = false);
128 bool SelectAddrRI(SDNode *Op, SDValue& Addr,
129 SDValue &Base, SDValue &Disp);
130 bool SelectAddrRRI12(SDNode *Op, SDValue Addr,
131 SDValue &Base, SDValue &Disp, SDValue &Index);
132 bool SelectAddrRRI20(SDNode *Op, SDValue Addr,
133 SDValue &Base, SDValue &Disp, SDValue &Index);
134 bool SelectLAAddr(SDNode *Op, SDValue Addr,
135 SDValue &Base, SDValue &Disp, SDValue &Index);
137 SDNode *Select(SDNode *Node);
139 bool TryFoldLoad(SDNode *P, SDValue N,
140 SDValue &Base, SDValue &Disp, SDValue &Index);
142 bool MatchAddress(SDValue N, SystemZRRIAddressMode &AM,
143 bool is12Bit, unsigned Depth = 0);
144 bool MatchAddressBase(SDValue N, SystemZRRIAddressMode &AM);
146 } // end anonymous namespace
148 /// createSystemZISelDag - This pass converts a legalized DAG into a
149 /// SystemZ-specific DAG, ready for instruction scheduling.
151 FunctionPass *llvm::createSystemZISelDag(SystemZTargetMachine &TM,
152 CodeGenOpt::Level OptLevel) {
153 return new SystemZDAGToDAGISel(TM, OptLevel);
156 /// isImmSExt20 - This method tests to see if the node is either a 32-bit
157 /// or 64-bit immediate, and if the value can be accurately represented as a
158 /// sign extension from a 20-bit value. If so, this returns true and the
160 static bool isImmSExt20(int64_t Val, int64_t &Imm) {
161 if (Val >= -524288 && Val <= 524287) {
168 /// isImmZExt12 - This method tests to see if the node is either a 32-bit
169 /// or 64-bit immediate, and if the value can be accurately represented as a
170 /// zero extension from a 12-bit value. If so, this returns true and the
172 static bool isImmZExt12(int64_t Val, int64_t &Imm) {
173 if (Val >= 0 && Val <= 0xFFF) {
180 /// MatchAddress - Add the specified node to the specified addressing mode,
181 /// returning true if it cannot be done. This just pattern matches for the
183 bool SystemZDAGToDAGISel::MatchAddress(SDValue N, SystemZRRIAddressMode &AM,
184 bool is12Bit, unsigned Depth) {
185 DebugLoc dl = N.getDebugLoc();
186 DEBUG(errs() << "MatchAddress: "; AM.dump());
189 return MatchAddressBase(N, AM);
191 // FIXME: We can perform better here. If we have something like
192 // (shift (add A, imm), N), we can try to reassociate stuff and fold shift of
193 // imm into addressing mode.
194 switch (N.getOpcode()) {
196 case ISD::Constant: {
197 int64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
199 bool Match = (is12Bit ?
200 isImmZExt12(AM.Disp + Val, Imm) :
201 isImmSExt20(AM.Disp + Val, Imm));
209 case ISD::FrameIndex:
210 if (AM.BaseType == SystemZRRIAddressMode::RegBase &&
211 AM.Base.Reg.getNode() == 0) {
212 AM.BaseType = SystemZRRIAddressMode::FrameIndexBase;
213 AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
219 // Given A-B, if A can be completely folded into the address and
220 // the index field with the index field unused, use -B as the index.
221 // This is a win if a has multiple parts that can be folded into
222 // the address. Also, this saves a mov if the base register has
223 // other uses, since it avoids a two-address sub instruction, however
224 // it costs an additional mov if the index register has other uses.
226 // Test if the LHS of the sub can be folded.
227 SystemZRRIAddressMode Backup = AM;
228 if (MatchAddress(N.getNode()->getOperand(0), AM, is12Bit, Depth+1)) {
232 // Test if the index field is free for use.
233 if (AM.IndexReg.getNode() || AM.isRI) {
238 // If the base is a register with multiple uses, this transformation may
239 // save a mov. Otherwise it's probably better not to do it.
240 if (AM.BaseType == SystemZRRIAddressMode::RegBase &&
241 (!AM.Base.Reg.getNode() || AM.Base.Reg.getNode()->hasOneUse())) {
246 // Ok, the transformation is legal and appears profitable. Go for it.
247 SDValue RHS = N.getNode()->getOperand(1);
248 SDValue Zero = CurDAG->getConstant(0, N.getValueType());
249 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS);
252 // Insert the new nodes into the topological ordering.
253 if (Zero.getNode()->getNodeId() == -1 ||
254 Zero.getNode()->getNodeId() > N.getNode()->getNodeId()) {
255 CurDAG->RepositionNode(N.getNode(), Zero.getNode());
256 Zero.getNode()->setNodeId(N.getNode()->getNodeId());
258 if (Neg.getNode()->getNodeId() == -1 ||
259 Neg.getNode()->getNodeId() > N.getNode()->getNodeId()) {
260 CurDAG->RepositionNode(N.getNode(), Neg.getNode());
261 Neg.getNode()->setNodeId(N.getNode()->getNodeId());
267 SystemZRRIAddressMode Backup = AM;
268 if (!MatchAddress(N.getNode()->getOperand(0), AM, is12Bit, Depth+1) &&
269 !MatchAddress(N.getNode()->getOperand(1), AM, is12Bit, Depth+1))
272 if (!MatchAddress(N.getNode()->getOperand(1), AM, is12Bit, Depth+1) &&
273 !MatchAddress(N.getNode()->getOperand(0), AM, is12Bit, Depth+1))
277 // If we couldn't fold both operands into the address at the same time,
278 // see if we can just put each operand into a register and fold at least
281 AM.BaseType == SystemZRRIAddressMode::RegBase &&
282 !AM.Base.Reg.getNode() && !AM.IndexReg.getNode()) {
283 AM.Base.Reg = N.getNode()->getOperand(0);
284 AM.IndexReg = N.getNode()->getOperand(1);
291 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
292 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
293 SystemZRRIAddressMode Backup = AM;
294 int64_t Offset = CN->getSExtValue();
296 bool MatchOffset = (is12Bit ?
297 isImmZExt12(AM.Disp + Offset, Imm) :
298 isImmSExt20(AM.Disp + Offset, Imm));
299 // The resultant disp must fit in 12 or 20-bits.
301 // LHS should be an addr mode.
302 !MatchAddress(N.getOperand(0), AM, is12Bit, Depth+1) &&
303 // Check to see if the LHS & C is zero.
304 CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
313 return MatchAddressBase(N, AM);
316 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
317 /// specified addressing mode without any further recursion.
318 bool SystemZDAGToDAGISel::MatchAddressBase(SDValue N,
319 SystemZRRIAddressMode &AM) {
320 // Is the base register already occupied?
321 if (AM.BaseType != SystemZRRIAddressMode::RegBase || AM.Base.Reg.getNode()) {
322 // If so, check to see if the index register is set.
323 if (AM.IndexReg.getNode() == 0 && !AM.isRI) {
328 // Otherwise, we cannot select it.
332 // Default, generate it as a register.
333 AM.BaseType = SystemZRRIAddressMode::RegBase;
338 void SystemZDAGToDAGISel::getAddressOperandsRI(const SystemZRRIAddressMode &AM,
339 SDValue &Base, SDValue &Disp) {
340 if (AM.BaseType == SystemZRRIAddressMode::RegBase)
343 Base = CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy());
344 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i64);
347 void SystemZDAGToDAGISel::getAddressOperands(const SystemZRRIAddressMode &AM,
348 SDValue &Base, SDValue &Disp,
350 getAddressOperandsRI(AM, Base, Disp);
354 /// Returns true if the address can be represented by a base register plus
355 /// an unsigned 12-bit displacement [r+imm].
356 bool SystemZDAGToDAGISel::SelectAddrRI12Only(SDNode *Op, SDValue& Addr,
357 SDValue &Base, SDValue &Disp) {
358 return SelectAddrRI12(Op, Addr, Base, Disp, /*is12BitOnly*/true);
361 bool SystemZDAGToDAGISel::SelectAddrRI12(SDNode *Op, SDValue& Addr,
362 SDValue &Base, SDValue &Disp,
364 SystemZRRIAddressMode AM20(/*isRI*/true), AM12(/*isRI*/true);
367 if (!Addr.hasOneUse()) {
368 unsigned Opcode = Addr.getOpcode();
369 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) {
370 // If we are able to fold N into addressing mode, then we'll allow it even
371 // if N has multiple uses. In general, addressing computation is used as
372 // addresses by all of its uses. But watch out for CopyToReg uses, that
373 // means the address computation is liveout. It will be computed by a LA
374 // so we want to avoid computing the address twice.
375 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
376 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
377 if (UI->getOpcode() == ISD::CopyToReg) {
378 MatchAddressBase(Addr, AM12);
385 if (!Done && MatchAddress(Addr, AM12, /* is12Bit */ true))
388 // Check, whether we can match stuff using 20-bit displacements
389 if (!Done && !is12BitOnly &&
390 !MatchAddress(Addr, AM20, /* is12Bit */ false))
391 if (AM12.Disp == 0 && AM20.Disp != 0)
394 DEBUG(errs() << "MatchAddress (final): "; AM12.dump());
396 EVT VT = Addr.getValueType();
397 if (AM12.BaseType == SystemZRRIAddressMode::RegBase) {
398 if (!AM12.Base.Reg.getNode())
399 AM12.Base.Reg = CurDAG->getRegister(0, VT);
402 assert(AM12.IndexReg.getNode() == 0 && "Invalid reg-imm address mode!");
404 getAddressOperandsRI(AM12, Base, Disp);
409 /// Returns true if the address can be represented by a base register plus
410 /// a signed 20-bit displacement [r+imm].
411 bool SystemZDAGToDAGISel::SelectAddrRI(SDNode *Op, SDValue& Addr,
412 SDValue &Base, SDValue &Disp) {
413 SystemZRRIAddressMode AM(/*isRI*/true);
416 if (!Addr.hasOneUse()) {
417 unsigned Opcode = Addr.getOpcode();
418 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) {
419 // If we are able to fold N into addressing mode, then we'll allow it even
420 // if N has multiple uses. In general, addressing computation is used as
421 // addresses by all of its uses. But watch out for CopyToReg uses, that
422 // means the address computation is liveout. It will be computed by a LA
423 // so we want to avoid computing the address twice.
424 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
425 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
426 if (UI->getOpcode() == ISD::CopyToReg) {
427 MatchAddressBase(Addr, AM);
434 if (!Done && MatchAddress(Addr, AM, /* is12Bit */ false))
437 DEBUG(errs() << "MatchAddress (final): "; AM.dump());
439 EVT VT = Addr.getValueType();
440 if (AM.BaseType == SystemZRRIAddressMode::RegBase) {
441 if (!AM.Base.Reg.getNode())
442 AM.Base.Reg = CurDAG->getRegister(0, VT);
445 assert(AM.IndexReg.getNode() == 0 && "Invalid reg-imm address mode!");
447 getAddressOperandsRI(AM, Base, Disp);
452 /// Returns true if the address can be represented by a base register plus
453 /// index register plus an unsigned 12-bit displacement [base + idx + imm].
454 bool SystemZDAGToDAGISel::SelectAddrRRI12(SDNode *Op, SDValue Addr,
455 SDValue &Base, SDValue &Disp, SDValue &Index) {
456 SystemZRRIAddressMode AM20, AM12;
459 if (!Addr.hasOneUse()) {
460 unsigned Opcode = Addr.getOpcode();
461 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) {
462 // If we are able to fold N into addressing mode, then we'll allow it even
463 // if N has multiple uses. In general, addressing computation is used as
464 // addresses by all of its uses. But watch out for CopyToReg uses, that
465 // means the address computation is liveout. It will be computed by a LA
466 // so we want to avoid computing the address twice.
467 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
468 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
469 if (UI->getOpcode() == ISD::CopyToReg) {
470 MatchAddressBase(Addr, AM12);
477 if (!Done && MatchAddress(Addr, AM12, /* is12Bit */ true))
480 // Check, whether we can match stuff using 20-bit displacements
481 if (!Done && !MatchAddress(Addr, AM20, /* is12Bit */ false))
482 if (AM12.Disp == 0 && AM20.Disp != 0)
485 DEBUG(errs() << "MatchAddress (final): "; AM12.dump());
487 EVT VT = Addr.getValueType();
488 if (AM12.BaseType == SystemZRRIAddressMode::RegBase) {
489 if (!AM12.Base.Reg.getNode())
490 AM12.Base.Reg = CurDAG->getRegister(0, VT);
493 if (!AM12.IndexReg.getNode())
494 AM12.IndexReg = CurDAG->getRegister(0, VT);
496 getAddressOperands(AM12, Base, Disp, Index);
501 /// Returns true if the address can be represented by a base register plus
502 /// index register plus a signed 20-bit displacement [base + idx + imm].
503 bool SystemZDAGToDAGISel::SelectAddrRRI20(SDNode *Op, SDValue Addr,
504 SDValue &Base, SDValue &Disp, SDValue &Index) {
505 SystemZRRIAddressMode AM;
508 if (!Addr.hasOneUse()) {
509 unsigned Opcode = Addr.getOpcode();
510 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) {
511 // If we are able to fold N into addressing mode, then we'll allow it even
512 // if N has multiple uses. In general, addressing computation is used as
513 // addresses by all of its uses. But watch out for CopyToReg uses, that
514 // means the address computation is liveout. It will be computed by a LA
515 // so we want to avoid computing the address twice.
516 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
517 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
518 if (UI->getOpcode() == ISD::CopyToReg) {
519 MatchAddressBase(Addr, AM);
526 if (!Done && MatchAddress(Addr, AM, /* is12Bit */ false))
529 DEBUG(errs() << "MatchAddress (final): "; AM.dump());
531 EVT VT = Addr.getValueType();
532 if (AM.BaseType == SystemZRRIAddressMode::RegBase) {
533 if (!AM.Base.Reg.getNode())
534 AM.Base.Reg = CurDAG->getRegister(0, VT);
537 if (!AM.IndexReg.getNode())
538 AM.IndexReg = CurDAG->getRegister(0, VT);
540 getAddressOperands(AM, Base, Disp, Index);
545 /// SelectLAAddr - it calls SelectAddr and determines if the maximal addressing
546 /// mode it matches can be cost effectively emitted as an LA/LAY instruction.
547 bool SystemZDAGToDAGISel::SelectLAAddr(SDNode *Op, SDValue Addr,
548 SDValue &Base, SDValue &Disp, SDValue &Index) {
549 SystemZRRIAddressMode AM;
551 if (MatchAddress(Addr, AM, false))
554 EVT VT = Addr.getValueType();
555 unsigned Complexity = 0;
556 if (AM.BaseType == SystemZRRIAddressMode::RegBase)
557 if (AM.Base.Reg.getNode())
560 AM.Base.Reg = CurDAG->getRegister(0, VT);
561 else if (AM.BaseType == SystemZRRIAddressMode::FrameIndexBase)
564 if (AM.IndexReg.getNode())
567 AM.IndexReg = CurDAG->getRegister(0, VT);
569 if (AM.Disp && (AM.Base.Reg.getNode() || AM.IndexReg.getNode()))
572 if (Complexity > 2) {
573 getAddressOperands(AM, Base, Disp, Index);
580 bool SystemZDAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N,
581 SDValue &Base, SDValue &Disp, SDValue &Index) {
582 if (ISD::isNON_EXTLoad(N.getNode()) &&
583 IsLegalToFold(N, P, P, OptLevel))
584 return SelectAddrRRI20(P, N.getOperand(1), Base, Disp, Index);
588 SDNode *SystemZDAGToDAGISel::Select(SDNode *Node) {
589 EVT NVT = Node->getValueType(0);
590 DebugLoc dl = Node->getDebugLoc();
591 unsigned Opcode = Node->getOpcode();
593 // Dump information about the Node being selected
594 DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
596 // If we have a custom node, we already have selected!
597 if (Node->isMachineOpcode()) {
598 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
599 return NULL; // Already selected.
606 SDValue N0 = Node->getOperand(0);
607 SDValue N1 = Node->getOperand(1);
610 bool is32Bit = false;
611 switch (NVT.getSimpleVT().SimpleTy) {
612 default: assert(0 && "Unsupported VT!");
614 Opc = SystemZ::SDIVREM32r; MOpc = SystemZ::SDIVREM32m;
619 Opc = SystemZ::SDIVREM64r; MOpc = SystemZ::SDIVREM64m;
624 SDValue Tmp0, Tmp1, Tmp2;
625 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2);
627 // Prepare the dividend
630 Dividend = CurDAG->getMachineNode(SystemZ::MOVSX64rr32, dl, MVT::i64, N0);
632 Dividend = N0.getNode();
634 // Insert prepared dividend into suitable 'subreg'
635 SDNode *Tmp = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
638 CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, dl, ResVT,
639 SDValue(Tmp, 0), SDValue(Dividend, 0),
640 CurDAG->getTargetConstant(SystemZ::subreg_odd, MVT::i32));
643 SDValue DivVal = SDValue(Dividend, 0);
645 SDValue Ops[] = { DivVal, Tmp0, Tmp1, Tmp2, N1.getOperand(0) };
646 Result = CurDAG->getMachineNode(MOpc, dl, ResVT, MVT::Other,
647 Ops, array_lengthof(Ops));
649 ReplaceUses(N1.getValue(1), SDValue(Result, 1));
651 Result = CurDAG->getMachineNode(Opc, dl, ResVT, SDValue(Dividend, 0), N1);
654 // Copy the division (odd subreg) result, if it is needed.
655 if (!SDValue(Node, 0).use_empty()) {
656 unsigned SubRegIdx = (is32Bit ?
657 SystemZ::subreg_odd32 : SystemZ::subreg_odd);
658 SDNode *Div = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
661 CurDAG->getTargetConstant(SubRegIdx,
664 ReplaceUses(SDValue(Node, 0), SDValue(Div, 0));
665 DEBUG(errs() << "=> "; Result->dump(CurDAG); errs() << "\n");
668 // Copy the remainder (even subreg) result, if it is needed.
669 if (!SDValue(Node, 1).use_empty()) {
670 unsigned SubRegIdx = (is32Bit ?
671 SystemZ::subreg_32bit : SystemZ::subreg_even);
672 SDNode *Rem = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
675 CurDAG->getTargetConstant(SubRegIdx,
678 ReplaceUses(SDValue(Node, 1), SDValue(Rem, 0));
679 DEBUG(errs() << "=> "; Result->dump(CurDAG); errs() << "\n");
685 unsigned Opc, MOpc, ClrOpc;
686 SDValue N0 = Node->getOperand(0);
687 SDValue N1 = Node->getOperand(1);
690 bool is32Bit = false;
691 switch (NVT.getSimpleVT().SimpleTy) {
692 default: assert(0 && "Unsupported VT!");
694 Opc = SystemZ::UDIVREM32r; MOpc = SystemZ::UDIVREM32m;
695 ClrOpc = SystemZ::MOV64Pr0_even;
700 Opc = SystemZ::UDIVREM64r; MOpc = SystemZ::UDIVREM64m;
701 ClrOpc = SystemZ::MOV128r0_even;
706 SDValue Tmp0, Tmp1, Tmp2;
707 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2);
709 // Prepare the dividend
710 SDNode *Dividend = N0.getNode();
712 // Insert prepared dividend into suitable 'subreg'
713 SDNode *Tmp = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
716 unsigned SubRegIdx = (is32Bit ?
717 SystemZ::subreg_odd32 : SystemZ::subreg_odd);
719 CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, dl, ResVT,
720 SDValue(Tmp, 0), SDValue(Dividend, 0),
721 CurDAG->getTargetConstant(SubRegIdx, MVT::i32));
724 // Zero out even subreg
725 Dividend = CurDAG->getMachineNode(ClrOpc, dl, ResVT, SDValue(Dividend, 0));
727 SDValue DivVal = SDValue(Dividend, 0);
730 SDValue Ops[] = { DivVal, Tmp0, Tmp1, Tmp2, N1.getOperand(0) };
731 Result = CurDAG->getMachineNode(MOpc, dl, ResVT, MVT::Other,
732 Ops, array_lengthof(Ops));
734 ReplaceUses(N1.getValue(1), SDValue(Result, 1));
736 Result = CurDAG->getMachineNode(Opc, dl, ResVT, DivVal, N1);
739 // Copy the division (odd subreg) result, if it is needed.
740 if (!SDValue(Node, 0).use_empty()) {
741 unsigned SubRegIdx = (is32Bit ?
742 SystemZ::subreg_odd32 : SystemZ::subreg_odd);
743 SDNode *Div = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
746 CurDAG->getTargetConstant(SubRegIdx,
748 ReplaceUses(SDValue(Node, 0), SDValue(Div, 0));
749 DEBUG(errs() << "=> "; Result->dump(CurDAG); errs() << "\n");
752 // Copy the remainder (even subreg) result, if it is needed.
753 if (!SDValue(Node, 1).use_empty()) {
754 unsigned SubRegIdx = (is32Bit ?
755 SystemZ::subreg_32bit : SystemZ::subreg_even);
756 SDNode *Rem = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
759 CurDAG->getTargetConstant(SubRegIdx,
761 ReplaceUses(SDValue(Node, 1), SDValue(Rem, 0));
762 DEBUG(errs() << "=> "; Result->dump(CurDAG); errs() << "\n");
769 // Select the default instruction
770 SDNode *ResNode = SelectCode(Node);
772 DEBUG(errs() << "=> ";
773 if (ResNode == NULL || ResNode == Node)
776 ResNode->dump(CurDAG);