1 //==-- SystemZISelDAGToDAG.cpp - A dag to dag inst selector for SystemZ ---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the SystemZ target.
12 //===----------------------------------------------------------------------===//
15 #include "SystemZISelLowering.h"
16 #include "SystemZTargetMachine.h"
17 #include "llvm/DerivedTypes.h"
18 #include "llvm/Function.h"
19 #include "llvm/Intrinsics.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/SelectionDAGISel.h"
28 #include "llvm/Target/TargetLowering.h"
29 #include "llvm/Support/Compiler.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/raw_ostream.h"
34 static const unsigned subreg_even32 = 1;
35 static const unsigned subreg_odd32 = 2;
36 static const unsigned subreg_even = 3;
37 static const unsigned subreg_odd = 4;
40 /// SystemZRRIAddressMode - This corresponds to rriaddr, but uses SDValue's
41 /// instead of register numbers for the leaves of the matched tree.
42 struct SystemZRRIAddressMode {
48 struct { // This is really a union, discriminated by BaseType!
57 SystemZRRIAddressMode(bool RI = false)
58 : BaseType(RegBase), IndexReg(), Disp(0), isRI(RI) {
62 errs() << "SystemZRRIAddressMode " << this << '\n';
63 if (BaseType == RegBase) {
64 errs() << "Base.Reg ";
65 if (Base.Reg.getNode() != 0)
66 Base.Reg.getNode()->dump();
71 errs() << " Base.FrameIndex " << Base.FrameIndex << '\n';
74 errs() << "IndexReg ";
75 if (IndexReg.getNode() != 0) IndexReg.getNode()->dump();
78 errs() << " Disp " << Disp << '\n';
83 /// SystemZDAGToDAGISel - SystemZ specific code to select SystemZ machine
84 /// instructions for SelectionDAG operations.
87 class SystemZDAGToDAGISel : public SelectionDAGISel {
88 SystemZTargetLowering &Lowering;
89 const SystemZSubtarget &Subtarget;
91 void getAddressOperandsRI(const SystemZRRIAddressMode &AM,
92 SDValue &Base, SDValue &Disp);
93 void getAddressOperands(const SystemZRRIAddressMode &AM,
94 SDValue &Base, SDValue &Disp,
98 SystemZDAGToDAGISel(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel)
99 : SelectionDAGISel(TM, OptLevel),
100 Lowering(*TM.getTargetLowering()),
101 Subtarget(*TM.getSubtargetImpl()) { }
103 virtual void InstructionSelect();
105 virtual const char *getPassName() const {
106 return "SystemZ DAG->DAG Pattern Instruction Selection";
109 /// getI8Imm - Return a target constant with the specified value, of type
111 inline SDValue getI8Imm(uint64_t Imm) {
112 return CurDAG->getTargetConstant(Imm, MVT::i8);
115 /// getI16Imm - Return a target constant with the specified value, of type
117 inline SDValue getI16Imm(uint64_t Imm) {
118 return CurDAG->getTargetConstant(Imm, MVT::i16);
121 /// getI32Imm - Return a target constant with the specified value, of type
123 inline SDValue getI32Imm(uint64_t Imm) {
124 return CurDAG->getTargetConstant(Imm, MVT::i32);
127 // Include the pieces autogenerated from the target description.
128 #include "SystemZGenDAGISel.inc"
131 bool SelectAddrRI12Only(SDValue Op, SDValue& Addr,
132 SDValue &Base, SDValue &Disp);
133 bool SelectAddrRI12(SDValue Op, SDValue& Addr,
134 SDValue &Base, SDValue &Disp,
135 bool is12BitOnly = false);
136 bool SelectAddrRI(SDValue Op, SDValue& Addr,
137 SDValue &Base, SDValue &Disp);
138 bool SelectAddrRRI12(SDValue Op, SDValue Addr,
139 SDValue &Base, SDValue &Disp, SDValue &Index);
140 bool SelectAddrRRI20(SDValue Op, SDValue Addr,
141 SDValue &Base, SDValue &Disp, SDValue &Index);
142 bool SelectLAAddr(SDValue Op, SDValue Addr,
143 SDValue &Base, SDValue &Disp, SDValue &Index);
145 SDNode *Select(SDValue Op);
147 bool TryFoldLoad(SDValue P, SDValue N,
148 SDValue &Base, SDValue &Disp, SDValue &Index);
150 bool MatchAddress(SDValue N, SystemZRRIAddressMode &AM,
151 bool is12Bit, unsigned Depth = 0);
152 bool MatchAddressBase(SDValue N, SystemZRRIAddressMode &AM);
153 bool MatchAddressRI(SDValue N, SystemZRRIAddressMode &AM,
160 } // end anonymous namespace
162 /// createSystemZISelDag - This pass converts a legalized DAG into a
163 /// SystemZ-specific DAG, ready for instruction scheduling.
165 FunctionPass *llvm::createSystemZISelDag(SystemZTargetMachine &TM,
166 CodeGenOpt::Level OptLevel) {
167 return new SystemZDAGToDAGISel(TM, OptLevel);
170 /// isImmSExt20 - This method tests to see if the node is either a 32-bit
171 /// or 64-bit immediate, and if the value can be accurately represented as a
172 /// sign extension from a 20-bit value. If so, this returns true and the
174 static bool isImmSExt20(int64_t Val, int64_t &Imm) {
175 if (Val >= -524288 && Val <= 524287) {
182 /// isImmZExt12 - This method tests to see if the node is either a 32-bit
183 /// or 64-bit immediate, and if the value can be accurately represented as a
184 /// zero extension from a 12-bit value. If so, this returns true and the
186 static bool isImmZExt12(int64_t Val, int64_t &Imm) {
187 if (Val >= 0 && Val <= 0xFFF) {
194 /// MatchAddress - Add the specified node to the specified addressing mode,
195 /// returning true if it cannot be done. This just pattern matches for the
197 bool SystemZDAGToDAGISel::MatchAddress(SDValue N, SystemZRRIAddressMode &AM,
198 bool is12Bit, unsigned Depth) {
199 DebugLoc dl = N.getDebugLoc();
200 DEBUG(errs() << "MatchAddress: "; AM.dump());
203 return MatchAddressBase(N, AM);
205 // FIXME: We can perform better here. If we have something like
206 // (shift (add A, imm), N), we can try to reassociate stuff and fold shift of
207 // imm into addressing mode.
208 switch (N.getOpcode()) {
210 case ISD::Constant: {
211 int64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
213 bool Match = (is12Bit ?
214 isImmZExt12(AM.Disp + Val, Imm) :
215 isImmSExt20(AM.Disp + Val, Imm));
223 case ISD::FrameIndex:
224 if (AM.BaseType == SystemZRRIAddressMode::RegBase &&
225 AM.Base.Reg.getNode() == 0) {
226 AM.BaseType = SystemZRRIAddressMode::FrameIndexBase;
227 AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
233 // Given A-B, if A can be completely folded into the address and
234 // the index field with the index field unused, use -B as the index.
235 // This is a win if a has multiple parts that can be folded into
236 // the address. Also, this saves a mov if the base register has
237 // other uses, since it avoids a two-address sub instruction, however
238 // it costs an additional mov if the index register has other uses.
240 // Test if the LHS of the sub can be folded.
241 SystemZRRIAddressMode Backup = AM;
242 if (MatchAddress(N.getNode()->getOperand(0), AM, is12Bit, Depth+1)) {
246 // Test if the index field is free for use.
247 if (AM.IndexReg.getNode() || AM.isRI) {
252 // If the base is a register with multiple uses, this transformation may
253 // save a mov. Otherwise it's probably better not to do it.
254 if (AM.BaseType == SystemZRRIAddressMode::RegBase &&
255 (!AM.Base.Reg.getNode() || AM.Base.Reg.getNode()->hasOneUse())) {
260 // Ok, the transformation is legal and appears profitable. Go for it.
261 SDValue RHS = N.getNode()->getOperand(1);
262 SDValue Zero = CurDAG->getConstant(0, N.getValueType());
263 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS);
266 // Insert the new nodes into the topological ordering.
267 if (Zero.getNode()->getNodeId() == -1 ||
268 Zero.getNode()->getNodeId() > N.getNode()->getNodeId()) {
269 CurDAG->RepositionNode(N.getNode(), Zero.getNode());
270 Zero.getNode()->setNodeId(N.getNode()->getNodeId());
272 if (Neg.getNode()->getNodeId() == -1 ||
273 Neg.getNode()->getNodeId() > N.getNode()->getNodeId()) {
274 CurDAG->RepositionNode(N.getNode(), Neg.getNode());
275 Neg.getNode()->setNodeId(N.getNode()->getNodeId());
281 SystemZRRIAddressMode Backup = AM;
282 if (!MatchAddress(N.getNode()->getOperand(0), AM, is12Bit, Depth+1) &&
283 !MatchAddress(N.getNode()->getOperand(1), AM, is12Bit, Depth+1))
286 if (!MatchAddress(N.getNode()->getOperand(1), AM, is12Bit, Depth+1) &&
287 !MatchAddress(N.getNode()->getOperand(0), AM, is12Bit, Depth+1))
291 // If we couldn't fold both operands into the address at the same time,
292 // see if we can just put each operand into a register and fold at least
295 AM.BaseType == SystemZRRIAddressMode::RegBase &&
296 !AM.Base.Reg.getNode() && !AM.IndexReg.getNode()) {
297 AM.Base.Reg = N.getNode()->getOperand(0);
298 AM.IndexReg = N.getNode()->getOperand(1);
305 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
306 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
307 SystemZRRIAddressMode Backup = AM;
308 int64_t Offset = CN->getSExtValue();
310 bool MatchOffset = (is12Bit ?
311 isImmZExt12(AM.Disp + Offset, Imm) :
312 isImmSExt20(AM.Disp + Offset, Imm));
313 // The resultant disp must fit in 12 or 20-bits.
315 // LHS should be an addr mode.
316 !MatchAddress(N.getOperand(0), AM, is12Bit, Depth+1) &&
317 // Check to see if the LHS & C is zero.
318 CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
327 return MatchAddressBase(N, AM);
330 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
331 /// specified addressing mode without any further recursion.
332 bool SystemZDAGToDAGISel::MatchAddressBase(SDValue N,
333 SystemZRRIAddressMode &AM) {
334 // Is the base register already occupied?
335 if (AM.BaseType != SystemZRRIAddressMode::RegBase || AM.Base.Reg.getNode()) {
336 // If so, check to see if the index register is set.
337 if (AM.IndexReg.getNode() == 0 && !AM.isRI) {
342 // Otherwise, we cannot select it.
346 // Default, generate it as a register.
347 AM.BaseType = SystemZRRIAddressMode::RegBase;
352 void SystemZDAGToDAGISel::getAddressOperandsRI(const SystemZRRIAddressMode &AM,
353 SDValue &Base, SDValue &Disp) {
354 if (AM.BaseType == SystemZRRIAddressMode::RegBase)
357 Base = CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy());
358 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i64);
361 void SystemZDAGToDAGISel::getAddressOperands(const SystemZRRIAddressMode &AM,
362 SDValue &Base, SDValue &Disp,
364 getAddressOperandsRI(AM, Base, Disp);
368 /// Returns true if the address can be represented by a base register plus
369 /// an unsigned 12-bit displacement [r+imm].
370 bool SystemZDAGToDAGISel::SelectAddrRI12Only(SDValue Op, SDValue& Addr,
371 SDValue &Base, SDValue &Disp) {
372 return SelectAddrRI12(Op, Addr, Base, Disp, /*is12BitOnly*/true);
375 bool SystemZDAGToDAGISel::SelectAddrRI12(SDValue Op, SDValue& Addr,
376 SDValue &Base, SDValue &Disp,
378 SystemZRRIAddressMode AM20(/*isRI*/true), AM12(/*isRI*/true);
381 if (!Addr.hasOneUse()) {
382 unsigned Opcode = Addr.getOpcode();
383 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) {
384 // If we are able to fold N into addressing mode, then we'll allow it even
385 // if N has multiple uses. In general, addressing computation is used as
386 // addresses by all of its uses. But watch out for CopyToReg uses, that
387 // means the address computation is liveout. It will be computed by a LA
388 // so we want to avoid computing the address twice.
389 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
390 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
391 if (UI->getOpcode() == ISD::CopyToReg) {
392 MatchAddressBase(Addr, AM12);
399 if (!Done && MatchAddress(Addr, AM12, /* is12Bit */ true))
402 // Check, whether we can match stuff using 20-bit displacements
403 if (!Done && !is12BitOnly &&
404 !MatchAddress(Addr, AM20, /* is12Bit */ false))
405 if (AM12.Disp == 0 && AM20.Disp != 0)
408 DEBUG(errs() << "MatchAddress (final): "; AM12.dump());
410 EVT VT = Addr.getValueType();
411 if (AM12.BaseType == SystemZRRIAddressMode::RegBase) {
412 if (!AM12.Base.Reg.getNode())
413 AM12.Base.Reg = CurDAG->getRegister(0, VT);
416 assert(AM12.IndexReg.getNode() == 0 && "Invalid reg-imm address mode!");
418 getAddressOperandsRI(AM12, Base, Disp);
423 /// Returns true if the address can be represented by a base register plus
424 /// a signed 20-bit displacement [r+imm].
425 bool SystemZDAGToDAGISel::SelectAddrRI(SDValue Op, SDValue& Addr,
426 SDValue &Base, SDValue &Disp) {
427 SystemZRRIAddressMode AM(/*isRI*/true);
430 if (!Addr.hasOneUse()) {
431 unsigned Opcode = Addr.getOpcode();
432 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) {
433 // If we are able to fold N into addressing mode, then we'll allow it even
434 // if N has multiple uses. In general, addressing computation is used as
435 // addresses by all of its uses. But watch out for CopyToReg uses, that
436 // means the address computation is liveout. It will be computed by a LA
437 // so we want to avoid computing the address twice.
438 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
439 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
440 if (UI->getOpcode() == ISD::CopyToReg) {
441 MatchAddressBase(Addr, AM);
448 if (!Done && MatchAddress(Addr, AM, /* is12Bit */ false))
451 DEBUG(errs() << "MatchAddress (final): "; AM.dump());
453 EVT VT = Addr.getValueType();
454 if (AM.BaseType == SystemZRRIAddressMode::RegBase) {
455 if (!AM.Base.Reg.getNode())
456 AM.Base.Reg = CurDAG->getRegister(0, VT);
459 assert(AM.IndexReg.getNode() == 0 && "Invalid reg-imm address mode!");
461 getAddressOperandsRI(AM, Base, Disp);
466 /// Returns true if the address can be represented by a base register plus
467 /// index register plus an unsigned 12-bit displacement [base + idx + imm].
468 bool SystemZDAGToDAGISel::SelectAddrRRI12(SDValue Op, SDValue Addr,
469 SDValue &Base, SDValue &Disp, SDValue &Index) {
470 SystemZRRIAddressMode AM20, AM12;
473 if (!Addr.hasOneUse()) {
474 unsigned Opcode = Addr.getOpcode();
475 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) {
476 // If we are able to fold N into addressing mode, then we'll allow it even
477 // if N has multiple uses. In general, addressing computation is used as
478 // addresses by all of its uses. But watch out for CopyToReg uses, that
479 // means the address computation is liveout. It will be computed by a LA
480 // so we want to avoid computing the address twice.
481 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
482 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
483 if (UI->getOpcode() == ISD::CopyToReg) {
484 MatchAddressBase(Addr, AM12);
491 if (!Done && MatchAddress(Addr, AM12, /* is12Bit */ true))
494 // Check, whether we can match stuff using 20-bit displacements
495 if (!Done && !MatchAddress(Addr, AM20, /* is12Bit */ false))
496 if (AM12.Disp == 0 && AM20.Disp != 0)
499 DEBUG(errs() << "MatchAddress (final): "; AM12.dump());
501 EVT VT = Addr.getValueType();
502 if (AM12.BaseType == SystemZRRIAddressMode::RegBase) {
503 if (!AM12.Base.Reg.getNode())
504 AM12.Base.Reg = CurDAG->getRegister(0, VT);
507 if (!AM12.IndexReg.getNode())
508 AM12.IndexReg = CurDAG->getRegister(0, VT);
510 getAddressOperands(AM12, Base, Disp, Index);
515 /// Returns true if the address can be represented by a base register plus
516 /// index register plus a signed 20-bit displacement [base + idx + imm].
517 bool SystemZDAGToDAGISel::SelectAddrRRI20(SDValue Op, SDValue Addr,
518 SDValue &Base, SDValue &Disp, SDValue &Index) {
519 SystemZRRIAddressMode AM;
522 if (!Addr.hasOneUse()) {
523 unsigned Opcode = Addr.getOpcode();
524 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) {
525 // If we are able to fold N into addressing mode, then we'll allow it even
526 // if N has multiple uses. In general, addressing computation is used as
527 // addresses by all of its uses. But watch out for CopyToReg uses, that
528 // means the address computation is liveout. It will be computed by a LA
529 // so we want to avoid computing the address twice.
530 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
531 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
532 if (UI->getOpcode() == ISD::CopyToReg) {
533 MatchAddressBase(Addr, AM);
540 if (!Done && MatchAddress(Addr, AM, /* is12Bit */ false))
543 DEBUG(errs() << "MatchAddress (final): "; AM.dump());
545 EVT VT = Addr.getValueType();
546 if (AM.BaseType == SystemZRRIAddressMode::RegBase) {
547 if (!AM.Base.Reg.getNode())
548 AM.Base.Reg = CurDAG->getRegister(0, VT);
551 if (!AM.IndexReg.getNode())
552 AM.IndexReg = CurDAG->getRegister(0, VT);
554 getAddressOperands(AM, Base, Disp, Index);
559 /// SelectLAAddr - it calls SelectAddr and determines if the maximal addressing
560 /// mode it matches can be cost effectively emitted as an LA/LAY instruction.
561 bool SystemZDAGToDAGISel::SelectLAAddr(SDValue Op, SDValue Addr,
562 SDValue &Base, SDValue &Disp, SDValue &Index) {
563 SystemZRRIAddressMode AM;
565 if (MatchAddress(Addr, AM, false))
568 EVT VT = Addr.getValueType();
569 unsigned Complexity = 0;
570 if (AM.BaseType == SystemZRRIAddressMode::RegBase)
571 if (AM.Base.Reg.getNode())
574 AM.Base.Reg = CurDAG->getRegister(0, VT);
575 else if (AM.BaseType == SystemZRRIAddressMode::FrameIndexBase)
578 if (AM.IndexReg.getNode())
581 AM.IndexReg = CurDAG->getRegister(0, VT);
583 if (AM.Disp && (AM.Base.Reg.getNode() || AM.IndexReg.getNode()))
586 if (Complexity > 2) {
587 getAddressOperands(AM, Base, Disp, Index);
594 bool SystemZDAGToDAGISel::TryFoldLoad(SDValue P, SDValue N,
595 SDValue &Base, SDValue &Disp, SDValue &Index) {
596 if (ISD::isNON_EXTLoad(N.getNode()) &&
598 IsLegalAndProfitableToFold(N.getNode(), P.getNode(), P.getNode()))
599 return SelectAddrRRI20(P, N.getOperand(1), Base, Disp, Index);
603 /// InstructionSelect - This callback is invoked by
604 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
605 void SystemZDAGToDAGISel::InstructionSelect() {
606 // Codegen the basic block.
607 DEBUG(errs() << "===== Instruction selection begins:\n");
610 DEBUG(errs() << "===== Instruction selection ends:\n");
612 CurDAG->RemoveDeadNodes();
615 SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
616 SDNode *Node = Op.getNode();
617 EVT NVT = Node->getValueType(0);
618 DebugLoc dl = Op.getDebugLoc();
619 unsigned Opcode = Node->getOpcode();
621 // Dump information about the Node being selected
622 DEBUG(errs().indent(Indent) << "Selecting: ";
627 // If we have a custom node, we already have selected!
628 if (Node->isMachineOpcode()) {
629 DEBUG(errs().indent(Indent-2) << "== ";
633 return NULL; // Already selected.
640 SDValue N0 = Node->getOperand(0);
641 SDValue N1 = Node->getOperand(1);
644 bool is32Bit = false;
645 switch (NVT.getSimpleVT().SimpleTy) {
646 default: assert(0 && "Unsupported VT!");
648 Opc = SystemZ::SDIVREM32r; MOpc = SystemZ::SDIVREM32m;
653 Opc = SystemZ::SDIVREM64r; MOpc = SystemZ::SDIVREM64m;
658 SDValue Tmp0, Tmp1, Tmp2;
659 bool foldedLoad = TryFoldLoad(Op, N1, Tmp0, Tmp1, Tmp2);
661 // Prepare the dividend
664 Dividend = CurDAG->getMachineNode(SystemZ::MOVSX64rr32, dl, MVT::i64, N0);
666 Dividend = N0.getNode();
668 // Insert prepared dividend into suitable 'subreg'
669 SDNode *Tmp = CurDAG->getMachineNode(TargetInstrInfo::IMPLICIT_DEF,
672 CurDAG->getMachineNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT,
673 SDValue(Tmp, 0), SDValue(Dividend, 0),
674 CurDAG->getTargetConstant(subreg_odd, MVT::i32));
677 SDValue DivVal = SDValue(Dividend, 0);
679 SDValue Ops[] = { DivVal, Tmp0, Tmp1, Tmp2, N1.getOperand(0) };
680 Result = CurDAG->getMachineNode(MOpc, dl, ResVT,
681 Ops, array_lengthof(Ops));
683 ReplaceUses(N1.getValue(1), SDValue(Result, 0));
685 Result = CurDAG->getMachineNode(Opc, dl, ResVT, SDValue(Dividend, 0), N1);
688 // Copy the division (odd subreg) result, if it is needed.
689 if (!Op.getValue(0).use_empty()) {
690 unsigned SubRegIdx = (is32Bit ? subreg_odd32 : subreg_odd);
691 SDNode *Div = CurDAG->getMachineNode(TargetInstrInfo::EXTRACT_SUBREG,
694 CurDAG->getTargetConstant(SubRegIdx,
697 ReplaceUses(Op.getValue(0), SDValue(Div, 0));
698 DEBUG(errs().indent(Indent-2) << "=> ";
699 Result->dump(CurDAG);
703 // Copy the remainder (even subreg) result, if it is needed.
704 if (!Op.getValue(1).use_empty()) {
705 unsigned SubRegIdx = (is32Bit ? subreg_even32 : subreg_even);
706 SDNode *Rem = CurDAG->getMachineNode(TargetInstrInfo::EXTRACT_SUBREG,
709 CurDAG->getTargetConstant(SubRegIdx,
712 ReplaceUses(Op.getValue(1), SDValue(Rem, 0));
713 DEBUG(errs().indent(Indent-2) << "=> ";
714 Result->dump(CurDAG);
725 unsigned Opc, MOpc, ClrOpc;
726 SDValue N0 = Node->getOperand(0);
727 SDValue N1 = Node->getOperand(1);
730 bool is32Bit = false;
731 switch (NVT.getSimpleVT().SimpleTy) {
732 default: assert(0 && "Unsupported VT!");
734 Opc = SystemZ::UDIVREM32r; MOpc = SystemZ::UDIVREM32m;
735 ClrOpc = SystemZ::MOV64Pr0_even;
740 Opc = SystemZ::UDIVREM64r; MOpc = SystemZ::UDIVREM64m;
741 ClrOpc = SystemZ::MOV128r0_even;
746 SDValue Tmp0, Tmp1, Tmp2;
747 bool foldedLoad = TryFoldLoad(Op, N1, Tmp0, Tmp1, Tmp2);
749 // Prepare the dividend
750 SDNode *Dividend = N0.getNode();
752 // Insert prepared dividend into suitable 'subreg'
753 SDNode *Tmp = CurDAG->getMachineNode(TargetInstrInfo::IMPLICIT_DEF,
756 unsigned SubRegIdx = (is32Bit ? subreg_odd32 : subreg_odd);
758 CurDAG->getMachineNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT,
759 SDValue(Tmp, 0), SDValue(Dividend, 0),
760 CurDAG->getTargetConstant(SubRegIdx, MVT::i32));
763 // Zero out even subreg
764 Dividend = CurDAG->getMachineNode(ClrOpc, dl, ResVT, SDValue(Dividend, 0));
766 SDValue DivVal = SDValue(Dividend, 0);
769 SDValue Ops[] = { DivVal, Tmp0, Tmp1, Tmp2, N1.getOperand(0) };
770 Result = CurDAG->getMachineNode(MOpc, dl,ResVT,
771 Ops, array_lengthof(Ops));
773 ReplaceUses(N1.getValue(1), SDValue(Result, 0));
775 Result = CurDAG->getMachineNode(Opc, dl, ResVT, DivVal, N1);
778 // Copy the division (odd subreg) result, if it is needed.
779 if (!Op.getValue(0).use_empty()) {
780 unsigned SubRegIdx = (is32Bit ? subreg_odd32 : subreg_odd);
781 SDNode *Div = CurDAG->getMachineNode(TargetInstrInfo::EXTRACT_SUBREG,
784 CurDAG->getTargetConstant(SubRegIdx,
786 ReplaceUses(Op.getValue(0), SDValue(Div, 0));
787 DEBUG(errs().indent(Indent-2) << "=> ";
788 Result->dump(CurDAG);
792 // Copy the remainder (even subreg) result, if it is needed.
793 if (!Op.getValue(1).use_empty()) {
794 unsigned SubRegIdx = (is32Bit ? subreg_even32 : subreg_even);
795 SDNode *Rem = CurDAG->getMachineNode(TargetInstrInfo::EXTRACT_SUBREG,
798 CurDAG->getTargetConstant(SubRegIdx,
800 ReplaceUses(Op.getValue(1), SDValue(Rem, 0));
801 DEBUG(errs().indent(Indent-2) << "=> ";
802 Result->dump(CurDAG);
814 // Select the default instruction
815 SDNode *ResNode = SelectCode(Op);
817 DEBUG(errs().indent(Indent-2) << "=> ";
818 if (ResNode == NULL || ResNode == Op.getNode())
819 Op.getNode()->dump(CurDAG);
821 ResNode->dump(CurDAG);