1 //===-- SystemZISelDAGToDAG.cpp - A dag to dag inst selector for SystemZ --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the SystemZ target.
12 //===----------------------------------------------------------------------===//
14 #include "SystemZTargetMachine.h"
15 #include "llvm/Analysis/AliasAnalysis.h"
16 #include "llvm/CodeGen/SelectionDAGISel.h"
17 #include "llvm/Support/Debug.h"
18 #include "llvm/Support/raw_ostream.h"
23 // Used to build addressing modes.
24 struct SystemZAddressingMode {
25 // The shape of the address.
30 // base+displacement+index for load and store operands
33 // base+displacement+index for load address operands
36 // base+displacement+index+ADJDYNALLOC
41 // The type of displacement. The enum names here correspond directly
42 // to the definitions in SystemZOperand.td. We could split them into
43 // flags -- single/pair, 128-bit, etc. -- but it hardly seems worth it.
53 // The parts of the address. The address is equivalent to:
55 // Base + Disp + Index + (IncludesDynAlloc ? ADJDYNALLOC : 0)
59 bool IncludesDynAlloc;
61 SystemZAddressingMode(AddrForm form, DispRange dr)
62 : Form(form), DR(dr), Base(), Disp(0), Index(),
63 IncludesDynAlloc(false) {}
65 // True if the address can have an index register.
66 bool hasIndexField() { return Form != FormBD; }
68 // True if the address can (and must) include ADJDYNALLOC.
69 bool isDynAlloc() { return Form == FormBDXDynAlloc; }
72 errs() << "SystemZAddressingMode " << this << '\n';
75 if (Base.getNode() != 0)
76 Base.getNode()->dump();
80 if (hasIndexField()) {
82 if (Index.getNode() != 0)
83 Index.getNode()->dump();
88 errs() << " Disp " << Disp;
90 errs() << " + ADJDYNALLOC";
95 // Return a mask with Count low bits set.
96 static uint64_t allOnes(unsigned int Count) {
97 return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1;
100 // Represents operands 2 to 5 of the ROTATE AND ... SELECTED BITS operation
101 // given by Opcode. The operands are: Input (R2), Start (I3), End (I4) and
102 // Rotate (I5). The combined operand value is effectively:
104 // (or (rotl Input, Rotate), ~Mask)
108 // (and (rotl Input, Rotate), Mask)
110 // otherwise. The output value has BitSize bits, although Input may be
111 // narrower (in which case the upper bits are don't care).
112 struct RxSBGOperands {
113 RxSBGOperands(unsigned Op, SDValue N)
114 : Opcode(Op), BitSize(N.getValueType().getSizeInBits()),
115 Mask(allOnes(BitSize)), Input(N), Start(64 - BitSize), End(63),
127 class SystemZDAGToDAGISel : public SelectionDAGISel {
128 const SystemZTargetLowering &Lowering;
129 const SystemZSubtarget &Subtarget;
131 // Used by SystemZOperands.td to create integer constants.
132 inline SDValue getImm(const SDNode *Node, uint64_t Imm) const {
133 return CurDAG->getTargetConstant(Imm, Node->getValueType(0));
136 const SystemZTargetMachine &getTargetMachine() const {
137 return static_cast<const SystemZTargetMachine &>(TM);
140 const SystemZInstrInfo *getInstrInfo() const {
141 return getTargetMachine().getInstrInfo();
144 // Try to fold more of the base or index of AM into AM, where IsBase
145 // selects between the base and index.
146 bool expandAddress(SystemZAddressingMode &AM, bool IsBase) const;
148 // Try to describe N in AM, returning true on success.
149 bool selectAddress(SDValue N, SystemZAddressingMode &AM) const;
151 // Extract individual target operands from matched address AM.
152 void getAddressOperands(const SystemZAddressingMode &AM, EVT VT,
153 SDValue &Base, SDValue &Disp) const;
154 void getAddressOperands(const SystemZAddressingMode &AM, EVT VT,
155 SDValue &Base, SDValue &Disp, SDValue &Index) const;
157 // Try to match Addr as a FormBD address with displacement type DR.
158 // Return true on success, storing the base and displacement in
159 // Base and Disp respectively.
160 bool selectBDAddr(SystemZAddressingMode::DispRange DR, SDValue Addr,
161 SDValue &Base, SDValue &Disp) const;
163 // Try to match Addr as a FormBDX address with displacement type DR.
164 // Return true on success and if the result had no index. Store the
165 // base and displacement in Base and Disp respectively.
166 bool selectMVIAddr(SystemZAddressingMode::DispRange DR, SDValue Addr,
167 SDValue &Base, SDValue &Disp) const;
169 // Try to match Addr as a FormBDX* address of form Form with
170 // displacement type DR. Return true on success, storing the base,
171 // displacement and index in Base, Disp and Index respectively.
172 bool selectBDXAddr(SystemZAddressingMode::AddrForm Form,
173 SystemZAddressingMode::DispRange DR, SDValue Addr,
174 SDValue &Base, SDValue &Disp, SDValue &Index) const;
176 // PC-relative address matching routines used by SystemZOperands.td.
177 bool selectPCRelAddress(SDValue Addr, SDValue &Target) const {
178 if (SystemZISD::isPCREL(Addr.getOpcode())) {
179 Target = Addr.getOperand(0);
185 // BD matching routines used by SystemZOperands.td.
186 bool selectBDAddr12Only(SDValue Addr, SDValue &Base, SDValue &Disp) const {
187 return selectBDAddr(SystemZAddressingMode::Disp12Only, Addr, Base, Disp);
189 bool selectBDAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp) const {
190 return selectBDAddr(SystemZAddressingMode::Disp12Pair, Addr, Base, Disp);
192 bool selectBDAddr20Only(SDValue Addr, SDValue &Base, SDValue &Disp) const {
193 return selectBDAddr(SystemZAddressingMode::Disp20Only, Addr, Base, Disp);
195 bool selectBDAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp) const {
196 return selectBDAddr(SystemZAddressingMode::Disp20Pair, Addr, Base, Disp);
199 // MVI matching routines used by SystemZOperands.td.
200 bool selectMVIAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp) const {
201 return selectMVIAddr(SystemZAddressingMode::Disp12Pair, Addr, Base, Disp);
203 bool selectMVIAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp) const {
204 return selectMVIAddr(SystemZAddressingMode::Disp20Pair, Addr, Base, Disp);
207 // BDX matching routines used by SystemZOperands.td.
208 bool selectBDXAddr12Only(SDValue Addr, SDValue &Base, SDValue &Disp,
209 SDValue &Index) const {
210 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal,
211 SystemZAddressingMode::Disp12Only,
212 Addr, Base, Disp, Index);
214 bool selectBDXAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp,
215 SDValue &Index) const {
216 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal,
217 SystemZAddressingMode::Disp12Pair,
218 Addr, Base, Disp, Index);
220 bool selectDynAlloc12Only(SDValue Addr, SDValue &Base, SDValue &Disp,
221 SDValue &Index) const {
222 return selectBDXAddr(SystemZAddressingMode::FormBDXDynAlloc,
223 SystemZAddressingMode::Disp12Only,
224 Addr, Base, Disp, Index);
226 bool selectBDXAddr20Only(SDValue Addr, SDValue &Base, SDValue &Disp,
227 SDValue &Index) const {
228 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal,
229 SystemZAddressingMode::Disp20Only,
230 Addr, Base, Disp, Index);
232 bool selectBDXAddr20Only128(SDValue Addr, SDValue &Base, SDValue &Disp,
233 SDValue &Index) const {
234 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal,
235 SystemZAddressingMode::Disp20Only128,
236 Addr, Base, Disp, Index);
238 bool selectBDXAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp,
239 SDValue &Index) const {
240 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal,
241 SystemZAddressingMode::Disp20Pair,
242 Addr, Base, Disp, Index);
244 bool selectLAAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp,
245 SDValue &Index) const {
246 return selectBDXAddr(SystemZAddressingMode::FormBDXLA,
247 SystemZAddressingMode::Disp12Pair,
248 Addr, Base, Disp, Index);
250 bool selectLAAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp,
251 SDValue &Index) const {
252 return selectBDXAddr(SystemZAddressingMode::FormBDXLA,
253 SystemZAddressingMode::Disp20Pair,
254 Addr, Base, Disp, Index);
257 // Check whether (or Op (and X InsertMask)) is effectively an insertion
258 // of X into bits InsertMask of some Y != Op. Return true if so and
260 bool detectOrAndInsertion(SDValue &Op, uint64_t InsertMask) const;
262 // Try to update RxSBG so that only the bits of RxSBG.Input in Mask are used.
263 // Return true on success.
264 bool refineRxSBGMask(RxSBGOperands &RxSBG, uint64_t Mask) const;
266 // Try to fold some of RxSBG.Input into other fields of RxSBG.
267 // Return true on success.
268 bool expandRxSBG(RxSBGOperands &RxSBG) const;
270 // Return an undefined value of type VT.
271 SDValue getUNDEF(SDLoc DL, EVT VT) const;
273 // Convert N to VT, if it isn't already.
274 SDValue convertTo(SDLoc DL, EVT VT, SDValue N) const;
276 // Try to implement AND or shift node N using RISBG with the zero flag set.
277 // Return the selected node on success, otherwise return null.
278 SDNode *tryRISBGZero(SDNode *N);
280 // Try to use RISBG or Opcode to implement OR or XOR node N.
281 // Return the selected node on success, otherwise return null.
282 SDNode *tryRxSBG(SDNode *N, unsigned Opcode);
284 // If Op0 is null, then Node is a constant that can be loaded using:
286 // (Opcode UpperVal LowerVal)
288 // If Op0 is nonnull, then Node can be implemented using:
290 // (Opcode (Opcode Op0 UpperVal) LowerVal)
291 SDNode *splitLargeImmediate(unsigned Opcode, SDNode *Node, SDValue Op0,
292 uint64_t UpperVal, uint64_t LowerVal);
294 // Return true if Load and Store are loads and stores of the same size
295 // and are guaranteed not to overlap. Such operations can be implemented
296 // using block (SS-format) instructions.
298 // Partial overlap would lead to incorrect code, since the block operations
299 // are logically bytewise, even though they have a fast path for the
300 // non-overlapping case. We also need to avoid full overlap (i.e. two
301 // addresses that might be equal at run time) because although that case
302 // would be handled correctly, it might be implemented by millicode.
303 bool canUseBlockOperation(StoreSDNode *Store, LoadSDNode *Load) const;
305 // N is a (store (load Y), X) pattern. Return true if it can use an MVC
307 bool storeLoadCanUseMVC(SDNode *N) const;
309 // N is a (store (op (load A[0]), (load A[1])), X) pattern. Return true
310 // if A[1 - I] == X and if N can use a block operation like NC from A[I]
312 bool storeLoadCanUseBlockBinary(SDNode *N, unsigned I) const;
315 SystemZDAGToDAGISel(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel)
316 : SelectionDAGISel(TM, OptLevel),
317 Lowering(*TM.getTargetLowering()),
318 Subtarget(*TM.getSubtargetImpl()) { }
320 // Override MachineFunctionPass.
321 const char *getPassName() const override {
322 return "SystemZ DAG->DAG Pattern Instruction Selection";
325 // Override SelectionDAGISel.
326 SDNode *Select(SDNode *Node) override;
327 bool SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
328 std::vector<SDValue> &OutOps) override;
330 // Include the pieces autogenerated from the target description.
331 #include "SystemZGenDAGISel.inc"
333 } // end anonymous namespace
335 FunctionPass *llvm::createSystemZISelDag(SystemZTargetMachine &TM,
336 CodeGenOpt::Level OptLevel) {
337 return new SystemZDAGToDAGISel(TM, OptLevel);
340 // Return true if Val should be selected as a displacement for an address
341 // with range DR. Here we're interested in the range of both the instruction
342 // described by DR and of any pairing instruction.
343 static bool selectDisp(SystemZAddressingMode::DispRange DR, int64_t Val) {
345 case SystemZAddressingMode::Disp12Only:
346 return isUInt<12>(Val);
348 case SystemZAddressingMode::Disp12Pair:
349 case SystemZAddressingMode::Disp20Only:
350 case SystemZAddressingMode::Disp20Pair:
351 return isInt<20>(Val);
353 case SystemZAddressingMode::Disp20Only128:
354 return isInt<20>(Val) && isInt<20>(Val + 8);
356 llvm_unreachable("Unhandled displacement range");
359 // Change the base or index in AM to Value, where IsBase selects
360 // between the base and index.
361 static void changeComponent(SystemZAddressingMode &AM, bool IsBase,
369 // The base or index of AM is equivalent to Value + ADJDYNALLOC,
370 // where IsBase selects between the base and index. Try to fold the
371 // ADJDYNALLOC into AM.
372 static bool expandAdjDynAlloc(SystemZAddressingMode &AM, bool IsBase,
374 if (AM.isDynAlloc() && !AM.IncludesDynAlloc) {
375 changeComponent(AM, IsBase, Value);
376 AM.IncludesDynAlloc = true;
382 // The base of AM is equivalent to Base + Index. Try to use Index as
383 // the index register.
384 static bool expandIndex(SystemZAddressingMode &AM, SDValue Base,
386 if (AM.hasIndexField() && !AM.Index.getNode()) {
394 // The base or index of AM is equivalent to Op0 + Op1, where IsBase selects
395 // between the base and index. Try to fold Op1 into AM's displacement.
396 static bool expandDisp(SystemZAddressingMode &AM, bool IsBase,
397 SDValue Op0, uint64_t Op1) {
398 // First try adjusting the displacement.
399 int64_t TestDisp = AM.Disp + Op1;
400 if (selectDisp(AM.DR, TestDisp)) {
401 changeComponent(AM, IsBase, Op0);
406 // We could consider forcing the displacement into a register and
407 // using it as an index, but it would need to be carefully tuned.
411 bool SystemZDAGToDAGISel::expandAddress(SystemZAddressingMode &AM,
413 SDValue N = IsBase ? AM.Base : AM.Index;
414 unsigned Opcode = N.getOpcode();
415 if (Opcode == ISD::TRUNCATE) {
417 Opcode = N.getOpcode();
419 if (Opcode == ISD::ADD || CurDAG->isBaseWithConstantOffset(N)) {
420 SDValue Op0 = N.getOperand(0);
421 SDValue Op1 = N.getOperand(1);
423 unsigned Op0Code = Op0->getOpcode();
424 unsigned Op1Code = Op1->getOpcode();
426 if (Op0Code == SystemZISD::ADJDYNALLOC)
427 return expandAdjDynAlloc(AM, IsBase, Op1);
428 if (Op1Code == SystemZISD::ADJDYNALLOC)
429 return expandAdjDynAlloc(AM, IsBase, Op0);
431 if (Op0Code == ISD::Constant)
432 return expandDisp(AM, IsBase, Op1,
433 cast<ConstantSDNode>(Op0)->getSExtValue());
434 if (Op1Code == ISD::Constant)
435 return expandDisp(AM, IsBase, Op0,
436 cast<ConstantSDNode>(Op1)->getSExtValue());
438 if (IsBase && expandIndex(AM, Op0, Op1))
441 if (Opcode == SystemZISD::PCREL_OFFSET) {
442 SDValue Full = N.getOperand(0);
443 SDValue Base = N.getOperand(1);
444 SDValue Anchor = Base.getOperand(0);
445 uint64_t Offset = (cast<GlobalAddressSDNode>(Full)->getOffset() -
446 cast<GlobalAddressSDNode>(Anchor)->getOffset());
447 return expandDisp(AM, IsBase, Base, Offset);
452 // Return true if an instruction with displacement range DR should be
453 // used for displacement value Val. selectDisp(DR, Val) must already hold.
454 static bool isValidDisp(SystemZAddressingMode::DispRange DR, int64_t Val) {
455 assert(selectDisp(DR, Val) && "Invalid displacement");
457 case SystemZAddressingMode::Disp12Only:
458 case SystemZAddressingMode::Disp20Only:
459 case SystemZAddressingMode::Disp20Only128:
462 case SystemZAddressingMode::Disp12Pair:
463 // Use the other instruction if the displacement is too large.
464 return isUInt<12>(Val);
466 case SystemZAddressingMode::Disp20Pair:
467 // Use the other instruction if the displacement is small enough.
468 return !isUInt<12>(Val);
470 llvm_unreachable("Unhandled displacement range");
473 // Return true if Base + Disp + Index should be performed by LA(Y).
474 static bool shouldUseLA(SDNode *Base, int64_t Disp, SDNode *Index) {
475 // Don't use LA(Y) for constants.
479 // Always use LA(Y) for frame addresses, since we know that the destination
480 // register is almost always (perhaps always) going to be different from
481 // the frame register.
482 if (Base->getOpcode() == ISD::FrameIndex)
486 // Always use LA(Y) if there is a base, displacement and index.
490 // Always use LA if the displacement is small enough. It should always
491 // be no worse than AGHI (and better if it avoids a move).
492 if (isUInt<12>(Disp))
495 // For similar reasons, always use LAY if the constant is too big for AGHI.
496 // LAY should be no worse than AGFI.
497 if (!isInt<16>(Disp))
500 // Don't use LA for plain registers.
504 // Don't use LA for plain addition if the index operand is only used
505 // once. It should be a natural two-operand addition in that case.
506 if (Index->hasOneUse())
509 // Prefer addition if the second operation is sign-extended, in the
510 // hope of using AGF.
511 unsigned IndexOpcode = Index->getOpcode();
512 if (IndexOpcode == ISD::SIGN_EXTEND ||
513 IndexOpcode == ISD::SIGN_EXTEND_INREG)
517 // Don't use LA for two-operand addition if either operand is only
518 // used once. The addition instructions are better in that case.
519 if (Base->hasOneUse())
525 // Return true if Addr is suitable for AM, updating AM if so.
526 bool SystemZDAGToDAGISel::selectAddress(SDValue Addr,
527 SystemZAddressingMode &AM) const {
528 // Start out assuming that the address will need to be loaded separately,
529 // then try to extend it as much as we can.
532 // First try treating the address as a constant.
533 if (Addr.getOpcode() == ISD::Constant &&
534 expandDisp(AM, true, SDValue(),
535 cast<ConstantSDNode>(Addr)->getSExtValue()))
538 // Otherwise try expanding each component.
539 while (expandAddress(AM, true) ||
540 (AM.Index.getNode() && expandAddress(AM, false)))
543 // Reject cases where it isn't profitable to use LA(Y).
544 if (AM.Form == SystemZAddressingMode::FormBDXLA &&
545 !shouldUseLA(AM.Base.getNode(), AM.Disp, AM.Index.getNode()))
548 // Reject cases where the other instruction in a pair should be used.
549 if (!isValidDisp(AM.DR, AM.Disp))
552 // Make sure that ADJDYNALLOC is included where necessary.
553 if (AM.isDynAlloc() && !AM.IncludesDynAlloc)
560 // Insert a node into the DAG at least before Pos. This will reposition
561 // the node as needed, and will assign it a node ID that is <= Pos's ID.
562 // Note that this does *not* preserve the uniqueness of node IDs!
563 // The selection DAG must no longer depend on their uniqueness when this
565 static void insertDAGNode(SelectionDAG *DAG, SDNode *Pos, SDValue N) {
566 if (N.getNode()->getNodeId() == -1 ||
567 N.getNode()->getNodeId() > Pos->getNodeId()) {
568 DAG->RepositionNode(Pos, N.getNode());
569 N.getNode()->setNodeId(Pos->getNodeId());
573 void SystemZDAGToDAGISel::getAddressOperands(const SystemZAddressingMode &AM,
574 EVT VT, SDValue &Base,
575 SDValue &Disp) const {
578 // Register 0 means "no base". This is mostly useful for shifts.
579 Base = CurDAG->getRegister(0, VT);
580 else if (Base.getOpcode() == ISD::FrameIndex) {
581 // Lower a FrameIndex to a TargetFrameIndex.
582 int64_t FrameIndex = cast<FrameIndexSDNode>(Base)->getIndex();
583 Base = CurDAG->getTargetFrameIndex(FrameIndex, VT);
584 } else if (Base.getValueType() != VT) {
585 // Truncate values from i64 to i32, for shifts.
586 assert(VT == MVT::i32 && Base.getValueType() == MVT::i64 &&
587 "Unexpected truncation");
589 SDValue Trunc = CurDAG->getNode(ISD::TRUNCATE, DL, VT, Base);
590 insertDAGNode(CurDAG, Base.getNode(), Trunc);
594 // Lower the displacement to a TargetConstant.
595 Disp = CurDAG->getTargetConstant(AM.Disp, VT);
598 void SystemZDAGToDAGISel::getAddressOperands(const SystemZAddressingMode &AM,
599 EVT VT, SDValue &Base,
601 SDValue &Index) const {
602 getAddressOperands(AM, VT, Base, Disp);
605 if (!Index.getNode())
606 // Register 0 means "no index".
607 Index = CurDAG->getRegister(0, VT);
610 bool SystemZDAGToDAGISel::selectBDAddr(SystemZAddressingMode::DispRange DR,
611 SDValue Addr, SDValue &Base,
612 SDValue &Disp) const {
613 SystemZAddressingMode AM(SystemZAddressingMode::FormBD, DR);
614 if (!selectAddress(Addr, AM))
617 getAddressOperands(AM, Addr.getValueType(), Base, Disp);
621 bool SystemZDAGToDAGISel::selectMVIAddr(SystemZAddressingMode::DispRange DR,
622 SDValue Addr, SDValue &Base,
623 SDValue &Disp) const {
624 SystemZAddressingMode AM(SystemZAddressingMode::FormBDXNormal, DR);
625 if (!selectAddress(Addr, AM) || AM.Index.getNode())
628 getAddressOperands(AM, Addr.getValueType(), Base, Disp);
632 bool SystemZDAGToDAGISel::selectBDXAddr(SystemZAddressingMode::AddrForm Form,
633 SystemZAddressingMode::DispRange DR,
634 SDValue Addr, SDValue &Base,
635 SDValue &Disp, SDValue &Index) const {
636 SystemZAddressingMode AM(Form, DR);
637 if (!selectAddress(Addr, AM))
640 getAddressOperands(AM, Addr.getValueType(), Base, Disp, Index);
644 bool SystemZDAGToDAGISel::detectOrAndInsertion(SDValue &Op,
645 uint64_t InsertMask) const {
646 // We're only interested in cases where the insertion is into some operand
647 // of Op, rather than into Op itself. The only useful case is an AND.
648 if (Op.getOpcode() != ISD::AND)
651 // We need a constant mask.
652 auto *MaskNode = dyn_cast<ConstantSDNode>(Op.getOperand(1).getNode());
656 // It's not an insertion of Op.getOperand(0) if the two masks overlap.
657 uint64_t AndMask = MaskNode->getZExtValue();
658 if (InsertMask & AndMask)
661 // It's only an insertion if all bits are covered or are known to be zero.
662 // The inner check covers all cases but is more expensive.
663 uint64_t Used = allOnes(Op.getValueType().getSizeInBits());
664 if (Used != (AndMask | InsertMask)) {
665 APInt KnownZero, KnownOne;
666 CurDAG->ComputeMaskedBits(Op.getOperand(0), KnownZero, KnownOne);
667 if (Used != (AndMask | InsertMask | KnownZero.getZExtValue()))
671 Op = Op.getOperand(0);
675 bool SystemZDAGToDAGISel::refineRxSBGMask(RxSBGOperands &RxSBG,
676 uint64_t Mask) const {
677 const SystemZInstrInfo *TII = getInstrInfo();
678 if (RxSBG.Rotate != 0)
679 Mask = (Mask << RxSBG.Rotate) | (Mask >> (64 - RxSBG.Rotate));
681 if (TII->isRxSBGMask(Mask, RxSBG.BitSize, RxSBG.Start, RxSBG.End)) {
688 // Return true if any bits of (RxSBG.Input & Mask) are significant.
689 static bool maskMatters(RxSBGOperands &RxSBG, uint64_t Mask) {
690 // Rotate the mask in the same way as RxSBG.Input is rotated.
691 if (RxSBG.Rotate != 0)
692 Mask = ((Mask << RxSBG.Rotate) | (Mask >> (64 - RxSBG.Rotate)));
693 return (Mask & RxSBG.Mask) != 0;
696 bool SystemZDAGToDAGISel::expandRxSBG(RxSBGOperands &RxSBG) const {
697 SDValue N = RxSBG.Input;
698 unsigned Opcode = N.getOpcode();
701 if (RxSBG.Opcode == SystemZ::RNSBG)
704 auto *MaskNode = dyn_cast<ConstantSDNode>(N.getOperand(1).getNode());
708 SDValue Input = N.getOperand(0);
709 uint64_t Mask = MaskNode->getZExtValue();
710 if (!refineRxSBGMask(RxSBG, Mask)) {
711 // If some bits of Input are already known zeros, those bits will have
712 // been removed from the mask. See if adding them back in makes the
714 APInt KnownZero, KnownOne;
715 CurDAG->ComputeMaskedBits(Input, KnownZero, KnownOne);
716 Mask |= KnownZero.getZExtValue();
717 if (!refineRxSBGMask(RxSBG, Mask))
725 if (RxSBG.Opcode != SystemZ::RNSBG)
728 auto *MaskNode = dyn_cast<ConstantSDNode>(N.getOperand(1).getNode());
732 SDValue Input = N.getOperand(0);
733 uint64_t Mask = ~MaskNode->getZExtValue();
734 if (!refineRxSBGMask(RxSBG, Mask)) {
735 // If some bits of Input are already known ones, those bits will have
736 // been removed from the mask. See if adding them back in makes the
738 APInt KnownZero, KnownOne;
739 CurDAG->ComputeMaskedBits(Input, KnownZero, KnownOne);
740 Mask &= ~KnownOne.getZExtValue();
741 if (!refineRxSBGMask(RxSBG, Mask))
749 // Any 64-bit rotate left can be merged into the RxSBG.
750 if (RxSBG.BitSize != 64 || N.getValueType() != MVT::i64)
752 auto *CountNode = dyn_cast<ConstantSDNode>(N.getOperand(1).getNode());
756 RxSBG.Rotate = (RxSBG.Rotate + CountNode->getZExtValue()) & 63;
757 RxSBG.Input = N.getOperand(0);
761 case ISD::ANY_EXTEND:
762 // Bits above the extended operand are don't-care.
763 RxSBG.Input = N.getOperand(0);
766 case ISD::ZERO_EXTEND:
767 if (RxSBG.Opcode != SystemZ::RNSBG) {
768 // Restrict the mask to the extended operand.
769 unsigned InnerBitSize = N.getOperand(0).getValueType().getSizeInBits();
770 if (!refineRxSBGMask(RxSBG, allOnes(InnerBitSize)))
773 RxSBG.Input = N.getOperand(0);
778 case ISD::SIGN_EXTEND: {
779 // Check that the extension bits are don't-care (i.e. are masked out
780 // by the final mask).
781 unsigned InnerBitSize = N.getOperand(0).getValueType().getSizeInBits();
782 if (maskMatters(RxSBG, allOnes(RxSBG.BitSize) - allOnes(InnerBitSize)))
785 RxSBG.Input = N.getOperand(0);
790 auto *CountNode = dyn_cast<ConstantSDNode>(N.getOperand(1).getNode());
794 uint64_t Count = CountNode->getZExtValue();
795 unsigned BitSize = N.getValueType().getSizeInBits();
796 if (Count < 1 || Count >= BitSize)
799 if (RxSBG.Opcode == SystemZ::RNSBG) {
800 // Treat (shl X, count) as (rotl X, size-count) as long as the bottom
801 // count bits from RxSBG.Input are ignored.
802 if (maskMatters(RxSBG, allOnes(Count)))
805 // Treat (shl X, count) as (and (rotl X, count), ~0<<count).
806 if (!refineRxSBGMask(RxSBG, allOnes(BitSize - Count) << Count))
810 RxSBG.Rotate = (RxSBG.Rotate + Count) & 63;
811 RxSBG.Input = N.getOperand(0);
817 auto *CountNode = dyn_cast<ConstantSDNode>(N.getOperand(1).getNode());
821 uint64_t Count = CountNode->getZExtValue();
822 unsigned BitSize = N.getValueType().getSizeInBits();
823 if (Count < 1 || Count >= BitSize)
826 if (RxSBG.Opcode == SystemZ::RNSBG || Opcode == ISD::SRA) {
827 // Treat (srl|sra X, count) as (rotl X, size-count) as long as the top
828 // count bits from RxSBG.Input are ignored.
829 if (maskMatters(RxSBG, allOnes(Count) << (BitSize - Count)))
832 // Treat (srl X, count), mask) as (and (rotl X, size-count), ~0>>count),
833 // which is similar to SLL above.
834 if (!refineRxSBGMask(RxSBG, allOnes(BitSize - Count)))
838 RxSBG.Rotate = (RxSBG.Rotate - Count) & 63;
839 RxSBG.Input = N.getOperand(0);
847 SDValue SystemZDAGToDAGISel::getUNDEF(SDLoc DL, EVT VT) const {
848 SDNode *N = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, VT);
849 return SDValue(N, 0);
852 SDValue SystemZDAGToDAGISel::convertTo(SDLoc DL, EVT VT, SDValue N) const {
853 if (N.getValueType() == MVT::i32 && VT == MVT::i64)
854 return CurDAG->getTargetInsertSubreg(SystemZ::subreg_l32,
855 DL, VT, getUNDEF(DL, MVT::i64), N);
856 if (N.getValueType() == MVT::i64 && VT == MVT::i32)
857 return CurDAG->getTargetExtractSubreg(SystemZ::subreg_l32, DL, VT, N);
858 assert(N.getValueType() == VT && "Unexpected value types");
862 SDNode *SystemZDAGToDAGISel::tryRISBGZero(SDNode *N) {
863 EVT VT = N->getValueType(0);
864 RxSBGOperands RISBG(SystemZ::RISBG, SDValue(N, 0));
866 while (expandRxSBG(RISBG))
867 if (RISBG.Input.getOpcode() != ISD::ANY_EXTEND)
872 // Prefer to use normal shift instructions over RISBG, since they can handle
873 // all cases and are sometimes shorter.
874 if (N->getOpcode() != ISD::AND)
877 // Prefer register extensions like LLC over RISBG. Also prefer to start
878 // out with normal ANDs if one instruction would be enough. We can convert
879 // these ANDs into an RISBG later if a three-address instruction is useful.
880 if (VT == MVT::i32 ||
881 RISBG.Mask == 0xff ||
882 RISBG.Mask == 0xffff ||
883 SystemZ::isImmLF(~RISBG.Mask) ||
884 SystemZ::isImmHF(~RISBG.Mask)) {
885 // Force the new mask into the DAG, since it may include known-one bits.
886 auto *MaskN = cast<ConstantSDNode>(N->getOperand(1).getNode());
887 if (MaskN->getZExtValue() != RISBG.Mask) {
888 SDValue NewMask = CurDAG->getConstant(RISBG.Mask, VT);
889 N = CurDAG->UpdateNodeOperands(N, N->getOperand(0), NewMask);
890 return SelectCode(N);
896 unsigned Opcode = SystemZ::RISBG;
897 EVT OpcodeVT = MVT::i64;
898 if (VT == MVT::i32 && Subtarget.hasHighWord()) {
899 Opcode = SystemZ::RISBMux;
905 getUNDEF(SDLoc(N), OpcodeVT),
906 convertTo(SDLoc(N), OpcodeVT, RISBG.Input),
907 CurDAG->getTargetConstant(RISBG.Start, MVT::i32),
908 CurDAG->getTargetConstant(RISBG.End | 128, MVT::i32),
909 CurDAG->getTargetConstant(RISBG.Rotate, MVT::i32)
911 N = CurDAG->getMachineNode(Opcode, SDLoc(N), OpcodeVT, Ops);
912 return convertTo(SDLoc(N), VT, SDValue(N, 0)).getNode();
915 SDNode *SystemZDAGToDAGISel::tryRxSBG(SDNode *N, unsigned Opcode) {
916 // Try treating each operand of N as the second operand of the RxSBG
917 // and see which goes deepest.
918 RxSBGOperands RxSBG[] = {
919 RxSBGOperands(Opcode, N->getOperand(0)),
920 RxSBGOperands(Opcode, N->getOperand(1))
922 unsigned Count[] = { 0, 0 };
923 for (unsigned I = 0; I < 2; ++I)
924 while (expandRxSBG(RxSBG[I]))
925 if (RxSBG[I].Input.getOpcode() != ISD::ANY_EXTEND)
928 // Do nothing if neither operand is suitable.
929 if (Count[0] == 0 && Count[1] == 0)
932 // Pick the deepest second operand.
933 unsigned I = Count[0] > Count[1] ? 0 : 1;
934 SDValue Op0 = N->getOperand(I ^ 1);
936 // Prefer IC for character insertions from memory.
937 if (Opcode == SystemZ::ROSBG && (RxSBG[I].Mask & 0xff) == 0)
938 if (auto *Load = dyn_cast<LoadSDNode>(Op0.getNode()))
939 if (Load->getMemoryVT() == MVT::i8)
942 // See whether we can avoid an AND in the first operand by converting
944 if (Opcode == SystemZ::ROSBG && detectOrAndInsertion(Op0, RxSBG[I].Mask))
945 Opcode = SystemZ::RISBG;
947 EVT VT = N->getValueType(0);
949 convertTo(SDLoc(N), MVT::i64, Op0),
950 convertTo(SDLoc(N), MVT::i64, RxSBG[I].Input),
951 CurDAG->getTargetConstant(RxSBG[I].Start, MVT::i32),
952 CurDAG->getTargetConstant(RxSBG[I].End, MVT::i32),
953 CurDAG->getTargetConstant(RxSBG[I].Rotate, MVT::i32)
955 N = CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i64, Ops);
956 return convertTo(SDLoc(N), VT, SDValue(N, 0)).getNode();
959 SDNode *SystemZDAGToDAGISel::splitLargeImmediate(unsigned Opcode, SDNode *Node,
960 SDValue Op0, uint64_t UpperVal,
962 EVT VT = Node->getValueType(0);
964 SDValue Upper = CurDAG->getConstant(UpperVal, VT);
966 Upper = CurDAG->getNode(Opcode, DL, VT, Op0, Upper);
967 Upper = SDValue(Select(Upper.getNode()), 0);
969 SDValue Lower = CurDAG->getConstant(LowerVal, VT);
970 SDValue Or = CurDAG->getNode(Opcode, DL, VT, Upper, Lower);
974 bool SystemZDAGToDAGISel::canUseBlockOperation(StoreSDNode *Store,
975 LoadSDNode *Load) const {
976 // Check that the two memory operands have the same size.
977 if (Load->getMemoryVT() != Store->getMemoryVT())
980 // Volatility stops an access from being decomposed.
981 if (Load->isVolatile() || Store->isVolatile())
984 // There's no chance of overlap if the load is invariant.
985 if (Load->isInvariant())
988 // Otherwise we need to check whether there's an alias.
989 const Value *V1 = Load->getSrcValue();
990 const Value *V2 = Store->getSrcValue();
995 uint64_t Size = Load->getMemoryVT().getStoreSize();
996 int64_t End1 = Load->getSrcValueOffset() + Size;
997 int64_t End2 = Store->getSrcValueOffset() + Size;
998 if (V1 == V2 && End1 == End2)
1001 return !AA->alias(AliasAnalysis::Location(V1, End1, Load->getTBAAInfo()),
1002 AliasAnalysis::Location(V2, End2, Store->getTBAAInfo()));
1005 bool SystemZDAGToDAGISel::storeLoadCanUseMVC(SDNode *N) const {
1006 auto *Store = cast<StoreSDNode>(N);
1007 auto *Load = cast<LoadSDNode>(Store->getValue());
1009 // Prefer not to use MVC if either address can use ... RELATIVE LONG
1011 uint64_t Size = Load->getMemoryVT().getStoreSize();
1012 if (Size > 1 && Size <= 8) {
1013 // Prefer LHRL, LRL and LGRL.
1014 if (SystemZISD::isPCREL(Load->getBasePtr().getOpcode()))
1016 // Prefer STHRL, STRL and STGRL.
1017 if (SystemZISD::isPCREL(Store->getBasePtr().getOpcode()))
1021 return canUseBlockOperation(Store, Load);
1024 bool SystemZDAGToDAGISel::storeLoadCanUseBlockBinary(SDNode *N,
1026 auto *StoreA = cast<StoreSDNode>(N);
1027 auto *LoadA = cast<LoadSDNode>(StoreA->getValue().getOperand(1 - I));
1028 auto *LoadB = cast<LoadSDNode>(StoreA->getValue().getOperand(I));
1029 return !LoadA->isVolatile() && canUseBlockOperation(StoreA, LoadB);
1032 SDNode *SystemZDAGToDAGISel::Select(SDNode *Node) {
1033 // Dump information about the Node being selected
1034 DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
1036 // If we have a custom node, we already have selected!
1037 if (Node->isMachineOpcode()) {
1038 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
1039 Node->setNodeId(-1);
1043 unsigned Opcode = Node->getOpcode();
1044 SDNode *ResNode = 0;
1047 if (Node->getOperand(1).getOpcode() != ISD::Constant)
1048 ResNode = tryRxSBG(Node, SystemZ::ROSBG);
1052 if (Node->getOperand(1).getOpcode() != ISD::Constant)
1053 ResNode = tryRxSBG(Node, SystemZ::RXSBG);
1056 // If this is a 64-bit operation in which both 32-bit halves are nonzero,
1057 // split the operation into two.
1058 if (!ResNode && Node->getValueType(0) == MVT::i64)
1059 if (auto *Op1 = dyn_cast<ConstantSDNode>(Node->getOperand(1))) {
1060 uint64_t Val = Op1->getZExtValue();
1061 if (!SystemZ::isImmLF(Val) && !SystemZ::isImmHF(Val))
1062 Node = splitLargeImmediate(Opcode, Node, Node->getOperand(0),
1063 Val - uint32_t(Val), uint32_t(Val));
1068 if (Node->getOperand(1).getOpcode() != ISD::Constant)
1069 ResNode = tryRxSBG(Node, SystemZ::RNSBG);
1074 case ISD::ZERO_EXTEND:
1076 ResNode = tryRISBGZero(Node);
1080 // If this is a 64-bit constant that is out of the range of LLILF,
1081 // LLIHF and LGFI, split it into two 32-bit pieces.
1082 if (Node->getValueType(0) == MVT::i64) {
1083 uint64_t Val = cast<ConstantSDNode>(Node)->getZExtValue();
1084 if (!SystemZ::isImmLF(Val) && !SystemZ::isImmHF(Val) && !isInt<32>(Val))
1085 Node = splitLargeImmediate(ISD::OR, Node, SDValue(),
1086 Val - uint32_t(Val), uint32_t(Val));
1090 case SystemZISD::SELECT_CCMASK: {
1091 SDValue Op0 = Node->getOperand(0);
1092 SDValue Op1 = Node->getOperand(1);
1093 // Prefer to put any load first, so that it can be matched as a
1094 // conditional load.
1095 if (Op1.getOpcode() == ISD::LOAD && Op0.getOpcode() != ISD::LOAD) {
1096 SDValue CCValid = Node->getOperand(2);
1097 SDValue CCMask = Node->getOperand(3);
1098 uint64_t ConstCCValid =
1099 cast<ConstantSDNode>(CCValid.getNode())->getZExtValue();
1100 uint64_t ConstCCMask =
1101 cast<ConstantSDNode>(CCMask.getNode())->getZExtValue();
1102 // Invert the condition.
1103 CCMask = CurDAG->getConstant(ConstCCValid ^ ConstCCMask,
1104 CCMask.getValueType());
1105 SDValue Op4 = Node->getOperand(4);
1106 Node = CurDAG->UpdateNodeOperands(Node, Op1, Op0, CCValid, CCMask, Op4);
1112 // Select the default instruction
1114 ResNode = SelectCode(Node);
1116 DEBUG(errs() << "=> ";
1117 if (ResNode == NULL || ResNode == Node)
1120 ResNode->dump(CurDAG);
1126 bool SystemZDAGToDAGISel::
1127 SelectInlineAsmMemoryOperand(const SDValue &Op,
1128 char ConstraintCode,
1129 std::vector<SDValue> &OutOps) {
1130 assert(ConstraintCode == 'm' && "Unexpected constraint code");
1131 // Accept addresses with short displacements, which are compatible
1132 // with Q, R, S and T. But keep the index operand for future expansion.
1133 SDValue Base, Disp, Index;
1134 if (!selectBDXAddr(SystemZAddressingMode::FormBD,
1135 SystemZAddressingMode::Disp12Only,
1136 Op, Base, Disp, Index))
1138 OutOps.push_back(Base);
1139 OutOps.push_back(Disp);
1140 OutOps.push_back(Index);