1 //==-- SystemZISelDAGToDAG.cpp - A dag to dag inst selector for SystemZ ---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the SystemZ target.
12 //===----------------------------------------------------------------------===//
15 #include "SystemZTargetMachine.h"
16 #include "llvm/DerivedTypes.h"
17 #include "llvm/Function.h"
18 #include "llvm/Intrinsics.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/Target/TargetLowering.h"
28 #include "llvm/Support/Compiler.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/raw_ostream.h"
33 static const unsigned subreg_even32 = 1;
34 static const unsigned subreg_odd32 = 2;
35 static const unsigned subreg_even = 3;
36 static const unsigned subreg_odd = 4;
39 /// SystemZRRIAddressMode - This corresponds to rriaddr, but uses SDValue's
40 /// instead of register numbers for the leaves of the matched tree.
41 struct SystemZRRIAddressMode {
47 struct { // This is really a union, discriminated by BaseType!
56 SystemZRRIAddressMode(bool RI = false)
57 : BaseType(RegBase), IndexReg(), Disp(0), isRI(RI) {
61 errs() << "SystemZRRIAddressMode " << this << '\n';
62 if (BaseType == RegBase) {
63 errs() << "Base.Reg ";
64 if (Base.Reg.getNode() != 0)
65 Base.Reg.getNode()->dump();
70 errs() << " Base.FrameIndex " << Base.FrameIndex << '\n';
73 errs() << "IndexReg ";
74 if (IndexReg.getNode() != 0) IndexReg.getNode()->dump();
77 errs() << " Disp " << Disp << '\n';
82 /// SystemZDAGToDAGISel - SystemZ specific code to select SystemZ machine
83 /// instructions for SelectionDAG operations.
86 class SystemZDAGToDAGISel : public SelectionDAGISel {
87 const SystemZTargetLowering &Lowering;
88 const SystemZSubtarget &Subtarget;
90 void getAddressOperandsRI(const SystemZRRIAddressMode &AM,
91 SDValue &Base, SDValue &Disp);
92 void getAddressOperands(const SystemZRRIAddressMode &AM,
93 SDValue &Base, SDValue &Disp,
97 SystemZDAGToDAGISel(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel)
98 : SelectionDAGISel(TM, OptLevel),
99 Lowering(*TM.getTargetLowering()),
100 Subtarget(*TM.getSubtargetImpl()) { }
102 virtual const char *getPassName() const {
103 return "SystemZ DAG->DAG Pattern Instruction Selection";
106 /// getI8Imm - Return a target constant with the specified value, of type
108 inline SDValue getI8Imm(uint64_t Imm) {
109 return CurDAG->getTargetConstant(Imm, MVT::i8);
112 /// getI16Imm - Return a target constant with the specified value, of type
114 inline SDValue getI16Imm(uint64_t Imm) {
115 return CurDAG->getTargetConstant(Imm, MVT::i16);
118 /// getI32Imm - Return a target constant with the specified value, of type
120 inline SDValue getI32Imm(uint64_t Imm) {
121 return CurDAG->getTargetConstant(Imm, MVT::i32);
124 // Include the pieces autogenerated from the target description.
125 #include "SystemZGenDAGISel.inc"
128 bool SelectAddrRI12Only(SDNode *Op, SDValue& Addr,
129 SDValue &Base, SDValue &Disp);
130 bool SelectAddrRI12(SDNode *Op, SDValue& Addr,
131 SDValue &Base, SDValue &Disp,
132 bool is12BitOnly = false);
133 bool SelectAddrRI(SDNode *Op, SDValue& Addr,
134 SDValue &Base, SDValue &Disp);
135 bool SelectAddrRRI12(SDNode *Op, SDValue Addr,
136 SDValue &Base, SDValue &Disp, SDValue &Index);
137 bool SelectAddrRRI20(SDNode *Op, SDValue Addr,
138 SDValue &Base, SDValue &Disp, SDValue &Index);
139 bool SelectLAAddr(SDNode *Op, SDValue Addr,
140 SDValue &Base, SDValue &Disp, SDValue &Index);
142 SDNode *Select(SDNode *Node);
144 bool TryFoldLoad(SDNode *P, SDValue N,
145 SDValue &Base, SDValue &Disp, SDValue &Index);
147 bool MatchAddress(SDValue N, SystemZRRIAddressMode &AM,
148 bool is12Bit, unsigned Depth = 0);
149 bool MatchAddressBase(SDValue N, SystemZRRIAddressMode &AM);
150 bool MatchAddressRI(SDValue N, SystemZRRIAddressMode &AM,
153 } // end anonymous namespace
155 /// createSystemZISelDag - This pass converts a legalized DAG into a
156 /// SystemZ-specific DAG, ready for instruction scheduling.
158 FunctionPass *llvm::createSystemZISelDag(SystemZTargetMachine &TM,
159 CodeGenOpt::Level OptLevel) {
160 return new SystemZDAGToDAGISel(TM, OptLevel);
163 /// isImmSExt20 - This method tests to see if the node is either a 32-bit
164 /// or 64-bit immediate, and if the value can be accurately represented as a
165 /// sign extension from a 20-bit value. If so, this returns true and the
167 static bool isImmSExt20(int64_t Val, int64_t &Imm) {
168 if (Val >= -524288 && Val <= 524287) {
175 /// isImmZExt12 - This method tests to see if the node is either a 32-bit
176 /// or 64-bit immediate, and if the value can be accurately represented as a
177 /// zero extension from a 12-bit value. If so, this returns true and the
179 static bool isImmZExt12(int64_t Val, int64_t &Imm) {
180 if (Val >= 0 && Val <= 0xFFF) {
187 /// MatchAddress - Add the specified node to the specified addressing mode,
188 /// returning true if it cannot be done. This just pattern matches for the
190 bool SystemZDAGToDAGISel::MatchAddress(SDValue N, SystemZRRIAddressMode &AM,
191 bool is12Bit, unsigned Depth) {
192 DebugLoc dl = N.getDebugLoc();
193 DEBUG(errs() << "MatchAddress: "; AM.dump());
196 return MatchAddressBase(N, AM);
198 // FIXME: We can perform better here. If we have something like
199 // (shift (add A, imm), N), we can try to reassociate stuff and fold shift of
200 // imm into addressing mode.
201 switch (N.getOpcode()) {
203 case ISD::Constant: {
204 int64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
206 bool Match = (is12Bit ?
207 isImmZExt12(AM.Disp + Val, Imm) :
208 isImmSExt20(AM.Disp + Val, Imm));
216 case ISD::FrameIndex:
217 if (AM.BaseType == SystemZRRIAddressMode::RegBase &&
218 AM.Base.Reg.getNode() == 0) {
219 AM.BaseType = SystemZRRIAddressMode::FrameIndexBase;
220 AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
226 // Given A-B, if A can be completely folded into the address and
227 // the index field with the index field unused, use -B as the index.
228 // This is a win if a has multiple parts that can be folded into
229 // the address. Also, this saves a mov if the base register has
230 // other uses, since it avoids a two-address sub instruction, however
231 // it costs an additional mov if the index register has other uses.
233 // Test if the LHS of the sub can be folded.
234 SystemZRRIAddressMode Backup = AM;
235 if (MatchAddress(N.getNode()->getOperand(0), AM, is12Bit, Depth+1)) {
239 // Test if the index field is free for use.
240 if (AM.IndexReg.getNode() || AM.isRI) {
245 // If the base is a register with multiple uses, this transformation may
246 // save a mov. Otherwise it's probably better not to do it.
247 if (AM.BaseType == SystemZRRIAddressMode::RegBase &&
248 (!AM.Base.Reg.getNode() || AM.Base.Reg.getNode()->hasOneUse())) {
253 // Ok, the transformation is legal and appears profitable. Go for it.
254 SDValue RHS = N.getNode()->getOperand(1);
255 SDValue Zero = CurDAG->getConstant(0, N.getValueType());
256 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS);
259 // Insert the new nodes into the topological ordering.
260 if (Zero.getNode()->getNodeId() == -1 ||
261 Zero.getNode()->getNodeId() > N.getNode()->getNodeId()) {
262 CurDAG->RepositionNode(N.getNode(), Zero.getNode());
263 Zero.getNode()->setNodeId(N.getNode()->getNodeId());
265 if (Neg.getNode()->getNodeId() == -1 ||
266 Neg.getNode()->getNodeId() > N.getNode()->getNodeId()) {
267 CurDAG->RepositionNode(N.getNode(), Neg.getNode());
268 Neg.getNode()->setNodeId(N.getNode()->getNodeId());
274 SystemZRRIAddressMode Backup = AM;
275 if (!MatchAddress(N.getNode()->getOperand(0), AM, is12Bit, Depth+1) &&
276 !MatchAddress(N.getNode()->getOperand(1), AM, is12Bit, Depth+1))
279 if (!MatchAddress(N.getNode()->getOperand(1), AM, is12Bit, Depth+1) &&
280 !MatchAddress(N.getNode()->getOperand(0), AM, is12Bit, Depth+1))
284 // If we couldn't fold both operands into the address at the same time,
285 // see if we can just put each operand into a register and fold at least
288 AM.BaseType == SystemZRRIAddressMode::RegBase &&
289 !AM.Base.Reg.getNode() && !AM.IndexReg.getNode()) {
290 AM.Base.Reg = N.getNode()->getOperand(0);
291 AM.IndexReg = N.getNode()->getOperand(1);
298 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
299 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
300 SystemZRRIAddressMode Backup = AM;
301 int64_t Offset = CN->getSExtValue();
303 bool MatchOffset = (is12Bit ?
304 isImmZExt12(AM.Disp + Offset, Imm) :
305 isImmSExt20(AM.Disp + Offset, Imm));
306 // The resultant disp must fit in 12 or 20-bits.
308 // LHS should be an addr mode.
309 !MatchAddress(N.getOperand(0), AM, is12Bit, Depth+1) &&
310 // Check to see if the LHS & C is zero.
311 CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
320 return MatchAddressBase(N, AM);
323 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
324 /// specified addressing mode without any further recursion.
325 bool SystemZDAGToDAGISel::MatchAddressBase(SDValue N,
326 SystemZRRIAddressMode &AM) {
327 // Is the base register already occupied?
328 if (AM.BaseType != SystemZRRIAddressMode::RegBase || AM.Base.Reg.getNode()) {
329 // If so, check to see if the index register is set.
330 if (AM.IndexReg.getNode() == 0 && !AM.isRI) {
335 // Otherwise, we cannot select it.
339 // Default, generate it as a register.
340 AM.BaseType = SystemZRRIAddressMode::RegBase;
345 void SystemZDAGToDAGISel::getAddressOperandsRI(const SystemZRRIAddressMode &AM,
346 SDValue &Base, SDValue &Disp) {
347 if (AM.BaseType == SystemZRRIAddressMode::RegBase)
350 Base = CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy());
351 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i64);
354 void SystemZDAGToDAGISel::getAddressOperands(const SystemZRRIAddressMode &AM,
355 SDValue &Base, SDValue &Disp,
357 getAddressOperandsRI(AM, Base, Disp);
361 /// Returns true if the address can be represented by a base register plus
362 /// an unsigned 12-bit displacement [r+imm].
363 bool SystemZDAGToDAGISel::SelectAddrRI12Only(SDNode *Op, SDValue& Addr,
364 SDValue &Base, SDValue &Disp) {
365 return SelectAddrRI12(Op, Addr, Base, Disp, /*is12BitOnly*/true);
368 bool SystemZDAGToDAGISel::SelectAddrRI12(SDNode *Op, SDValue& Addr,
369 SDValue &Base, SDValue &Disp,
371 SystemZRRIAddressMode AM20(/*isRI*/true), AM12(/*isRI*/true);
374 if (!Addr.hasOneUse()) {
375 unsigned Opcode = Addr.getOpcode();
376 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) {
377 // If we are able to fold N into addressing mode, then we'll allow it even
378 // if N has multiple uses. In general, addressing computation is used as
379 // addresses by all of its uses. But watch out for CopyToReg uses, that
380 // means the address computation is liveout. It will be computed by a LA
381 // so we want to avoid computing the address twice.
382 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
383 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
384 if (UI->getOpcode() == ISD::CopyToReg) {
385 MatchAddressBase(Addr, AM12);
392 if (!Done && MatchAddress(Addr, AM12, /* is12Bit */ true))
395 // Check, whether we can match stuff using 20-bit displacements
396 if (!Done && !is12BitOnly &&
397 !MatchAddress(Addr, AM20, /* is12Bit */ false))
398 if (AM12.Disp == 0 && AM20.Disp != 0)
401 DEBUG(errs() << "MatchAddress (final): "; AM12.dump());
403 EVT VT = Addr.getValueType();
404 if (AM12.BaseType == SystemZRRIAddressMode::RegBase) {
405 if (!AM12.Base.Reg.getNode())
406 AM12.Base.Reg = CurDAG->getRegister(0, VT);
409 assert(AM12.IndexReg.getNode() == 0 && "Invalid reg-imm address mode!");
411 getAddressOperandsRI(AM12, Base, Disp);
416 /// Returns true if the address can be represented by a base register plus
417 /// a signed 20-bit displacement [r+imm].
418 bool SystemZDAGToDAGISel::SelectAddrRI(SDNode *Op, SDValue& Addr,
419 SDValue &Base, SDValue &Disp) {
420 SystemZRRIAddressMode AM(/*isRI*/true);
423 if (!Addr.hasOneUse()) {
424 unsigned Opcode = Addr.getOpcode();
425 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) {
426 // If we are able to fold N into addressing mode, then we'll allow it even
427 // if N has multiple uses. In general, addressing computation is used as
428 // addresses by all of its uses. But watch out for CopyToReg uses, that
429 // means the address computation is liveout. It will be computed by a LA
430 // so we want to avoid computing the address twice.
431 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
432 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
433 if (UI->getOpcode() == ISD::CopyToReg) {
434 MatchAddressBase(Addr, AM);
441 if (!Done && MatchAddress(Addr, AM, /* is12Bit */ false))
444 DEBUG(errs() << "MatchAddress (final): "; AM.dump());
446 EVT VT = Addr.getValueType();
447 if (AM.BaseType == SystemZRRIAddressMode::RegBase) {
448 if (!AM.Base.Reg.getNode())
449 AM.Base.Reg = CurDAG->getRegister(0, VT);
452 assert(AM.IndexReg.getNode() == 0 && "Invalid reg-imm address mode!");
454 getAddressOperandsRI(AM, Base, Disp);
459 /// Returns true if the address can be represented by a base register plus
460 /// index register plus an unsigned 12-bit displacement [base + idx + imm].
461 bool SystemZDAGToDAGISel::SelectAddrRRI12(SDNode *Op, SDValue Addr,
462 SDValue &Base, SDValue &Disp, SDValue &Index) {
463 SystemZRRIAddressMode AM20, AM12;
466 if (!Addr.hasOneUse()) {
467 unsigned Opcode = Addr.getOpcode();
468 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) {
469 // If we are able to fold N into addressing mode, then we'll allow it even
470 // if N has multiple uses. In general, addressing computation is used as
471 // addresses by all of its uses. But watch out for CopyToReg uses, that
472 // means the address computation is liveout. It will be computed by a LA
473 // so we want to avoid computing the address twice.
474 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
475 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
476 if (UI->getOpcode() == ISD::CopyToReg) {
477 MatchAddressBase(Addr, AM12);
484 if (!Done && MatchAddress(Addr, AM12, /* is12Bit */ true))
487 // Check, whether we can match stuff using 20-bit displacements
488 if (!Done && !MatchAddress(Addr, AM20, /* is12Bit */ false))
489 if (AM12.Disp == 0 && AM20.Disp != 0)
492 DEBUG(errs() << "MatchAddress (final): "; AM12.dump());
494 EVT VT = Addr.getValueType();
495 if (AM12.BaseType == SystemZRRIAddressMode::RegBase) {
496 if (!AM12.Base.Reg.getNode())
497 AM12.Base.Reg = CurDAG->getRegister(0, VT);
500 if (!AM12.IndexReg.getNode())
501 AM12.IndexReg = CurDAG->getRegister(0, VT);
503 getAddressOperands(AM12, Base, Disp, Index);
508 /// Returns true if the address can be represented by a base register plus
509 /// index register plus a signed 20-bit displacement [base + idx + imm].
510 bool SystemZDAGToDAGISel::SelectAddrRRI20(SDNode *Op, SDValue Addr,
511 SDValue &Base, SDValue &Disp, SDValue &Index) {
512 SystemZRRIAddressMode AM;
515 if (!Addr.hasOneUse()) {
516 unsigned Opcode = Addr.getOpcode();
517 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) {
518 // If we are able to fold N into addressing mode, then we'll allow it even
519 // if N has multiple uses. In general, addressing computation is used as
520 // addresses by all of its uses. But watch out for CopyToReg uses, that
521 // means the address computation is liveout. It will be computed by a LA
522 // so we want to avoid computing the address twice.
523 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
524 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
525 if (UI->getOpcode() == ISD::CopyToReg) {
526 MatchAddressBase(Addr, AM);
533 if (!Done && MatchAddress(Addr, AM, /* is12Bit */ false))
536 DEBUG(errs() << "MatchAddress (final): "; AM.dump());
538 EVT VT = Addr.getValueType();
539 if (AM.BaseType == SystemZRRIAddressMode::RegBase) {
540 if (!AM.Base.Reg.getNode())
541 AM.Base.Reg = CurDAG->getRegister(0, VT);
544 if (!AM.IndexReg.getNode())
545 AM.IndexReg = CurDAG->getRegister(0, VT);
547 getAddressOperands(AM, Base, Disp, Index);
552 /// SelectLAAddr - it calls SelectAddr and determines if the maximal addressing
553 /// mode it matches can be cost effectively emitted as an LA/LAY instruction.
554 bool SystemZDAGToDAGISel::SelectLAAddr(SDNode *Op, SDValue Addr,
555 SDValue &Base, SDValue &Disp, SDValue &Index) {
556 SystemZRRIAddressMode AM;
558 if (MatchAddress(Addr, AM, false))
561 EVT VT = Addr.getValueType();
562 unsigned Complexity = 0;
563 if (AM.BaseType == SystemZRRIAddressMode::RegBase)
564 if (AM.Base.Reg.getNode())
567 AM.Base.Reg = CurDAG->getRegister(0, VT);
568 else if (AM.BaseType == SystemZRRIAddressMode::FrameIndexBase)
571 if (AM.IndexReg.getNode())
574 AM.IndexReg = CurDAG->getRegister(0, VT);
576 if (AM.Disp && (AM.Base.Reg.getNode() || AM.IndexReg.getNode()))
579 if (Complexity > 2) {
580 getAddressOperands(AM, Base, Disp, Index);
587 bool SystemZDAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N,
588 SDValue &Base, SDValue &Disp, SDValue &Index) {
589 if (ISD::isNON_EXTLoad(N.getNode()) &&
590 IsLegalToFold(N, P, P, OptLevel))
591 return SelectAddrRRI20(P, N.getOperand(1), Base, Disp, Index);
595 SDNode *SystemZDAGToDAGISel::Select(SDNode *Node) {
596 EVT NVT = Node->getValueType(0);
597 DebugLoc dl = Node->getDebugLoc();
598 unsigned Opcode = Node->getOpcode();
600 // Dump information about the Node being selected
601 DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
603 // If we have a custom node, we already have selected!
604 if (Node->isMachineOpcode()) {
605 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
606 return NULL; // Already selected.
613 SDValue N0 = Node->getOperand(0);
614 SDValue N1 = Node->getOperand(1);
617 bool is32Bit = false;
618 switch (NVT.getSimpleVT().SimpleTy) {
619 default: assert(0 && "Unsupported VT!");
621 Opc = SystemZ::SDIVREM32r; MOpc = SystemZ::SDIVREM32m;
626 Opc = SystemZ::SDIVREM64r; MOpc = SystemZ::SDIVREM64m;
631 SDValue Tmp0, Tmp1, Tmp2;
632 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2);
634 // Prepare the dividend
637 Dividend = CurDAG->getMachineNode(SystemZ::MOVSX64rr32, dl, MVT::i64, N0);
639 Dividend = N0.getNode();
641 // Insert prepared dividend into suitable 'subreg'
642 SDNode *Tmp = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
645 CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, dl, ResVT,
646 SDValue(Tmp, 0), SDValue(Dividend, 0),
647 CurDAG->getTargetConstant(subreg_odd, MVT::i32));
650 SDValue DivVal = SDValue(Dividend, 0);
652 SDValue Ops[] = { DivVal, Tmp0, Tmp1, Tmp2, N1.getOperand(0) };
653 Result = CurDAG->getMachineNode(MOpc, dl, ResVT, MVT::Other,
654 Ops, array_lengthof(Ops));
656 ReplaceUses(N1.getValue(1), SDValue(Result, 1));
658 Result = CurDAG->getMachineNode(Opc, dl, ResVT, SDValue(Dividend, 0), N1);
661 // Copy the division (odd subreg) result, if it is needed.
662 if (!SDValue(Node, 0).use_empty()) {
663 unsigned SubRegIdx = (is32Bit ? subreg_odd32 : subreg_odd);
664 SDNode *Div = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
667 CurDAG->getTargetConstant(SubRegIdx,
670 ReplaceUses(SDValue(Node, 0), SDValue(Div, 0));
671 DEBUG(errs() << "=> "; Result->dump(CurDAG); errs() << "\n");
674 // Copy the remainder (even subreg) result, if it is needed.
675 if (!SDValue(Node, 1).use_empty()) {
676 unsigned SubRegIdx = (is32Bit ? subreg_even32 : subreg_even);
677 SDNode *Rem = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
680 CurDAG->getTargetConstant(SubRegIdx,
683 ReplaceUses(SDValue(Node, 1), SDValue(Rem, 0));
684 DEBUG(errs() << "=> "; Result->dump(CurDAG); errs() << "\n");
690 unsigned Opc, MOpc, ClrOpc;
691 SDValue N0 = Node->getOperand(0);
692 SDValue N1 = Node->getOperand(1);
695 bool is32Bit = false;
696 switch (NVT.getSimpleVT().SimpleTy) {
697 default: assert(0 && "Unsupported VT!");
699 Opc = SystemZ::UDIVREM32r; MOpc = SystemZ::UDIVREM32m;
700 ClrOpc = SystemZ::MOV64Pr0_even;
705 Opc = SystemZ::UDIVREM64r; MOpc = SystemZ::UDIVREM64m;
706 ClrOpc = SystemZ::MOV128r0_even;
711 SDValue Tmp0, Tmp1, Tmp2;
712 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2);
714 // Prepare the dividend
715 SDNode *Dividend = N0.getNode();
717 // Insert prepared dividend into suitable 'subreg'
718 SDNode *Tmp = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
721 unsigned SubRegIdx = (is32Bit ? subreg_odd32 : subreg_odd);
723 CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, dl, ResVT,
724 SDValue(Tmp, 0), SDValue(Dividend, 0),
725 CurDAG->getTargetConstant(SubRegIdx, MVT::i32));
728 // Zero out even subreg
729 Dividend = CurDAG->getMachineNode(ClrOpc, dl, ResVT, SDValue(Dividend, 0));
731 SDValue DivVal = SDValue(Dividend, 0);
734 SDValue Ops[] = { DivVal, Tmp0, Tmp1, Tmp2, N1.getOperand(0) };
735 Result = CurDAG->getMachineNode(MOpc, dl, ResVT, MVT::Other,
736 Ops, array_lengthof(Ops));
738 ReplaceUses(N1.getValue(1), SDValue(Result, 1));
740 Result = CurDAG->getMachineNode(Opc, dl, ResVT, DivVal, N1);
743 // Copy the division (odd subreg) result, if it is needed.
744 if (!SDValue(Node, 0).use_empty()) {
745 unsigned SubRegIdx = (is32Bit ? subreg_odd32 : subreg_odd);
746 SDNode *Div = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
749 CurDAG->getTargetConstant(SubRegIdx,
751 ReplaceUses(SDValue(Node, 0), SDValue(Div, 0));
752 DEBUG(errs() << "=> "; Result->dump(CurDAG); errs() << "\n");
755 // Copy the remainder (even subreg) result, if it is needed.
756 if (!SDValue(Node, 1).use_empty()) {
757 unsigned SubRegIdx = (is32Bit ? subreg_even32 : subreg_even);
758 SDNode *Rem = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
761 CurDAG->getTargetConstant(SubRegIdx,
763 ReplaceUses(SDValue(Node, 1), SDValue(Rem, 0));
764 DEBUG(errs() << "=> "; Result->dump(CurDAG); errs() << "\n");
771 // Select the default instruction
772 SDNode *ResNode = SelectCode(Node);
774 DEBUG(errs() << "=> ";
775 if (ResNode == NULL || ResNode == Node)
778 ResNode->dump(CurDAG);