1 //===-- SystemZISelLowering.cpp - SystemZ DAG Lowering Implementation -----==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SystemZTargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "systemz-lower"
16 #include "SystemZISelLowering.h"
18 #include "SystemZTargetMachine.h"
19 #include "SystemZSubtarget.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/PseudoSourceValue.h"
32 #include "llvm/CodeGen/SelectionDAGISel.h"
33 #include "llvm/CodeGen/ValueTypes.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Target/TargetOptions.h"
36 #include "llvm/ADT/VectorExtras.h"
39 SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
40 TargetLowering(tm), Subtarget(*tm.getSubtargetImpl()), TM(tm) {
42 RegInfo = TM.getRegisterInfo();
44 // Set up the register classes.
45 addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass);
46 addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass);
47 addRegisterClass(MVT::v2i32,SystemZ::GR64PRegisterClass);
48 addRegisterClass(MVT::i128, SystemZ::GR128RegisterClass);
49 addRegisterClass(MVT::v2i64,SystemZ::GR128RegisterClass);
52 addRegisterClass(MVT::f32, SystemZ::FP32RegisterClass);
53 addRegisterClass(MVT::f64, SystemZ::FP64RegisterClass);
55 addLegalFPImmediate(APFloat(+0.0)); // lzer
56 addLegalFPImmediate(APFloat(+0.0f)); // lzdr
57 addLegalFPImmediate(APFloat(-0.0)); // lzer + lner
58 addLegalFPImmediate(APFloat(-0.0f)); // lzdr + lndr
61 // Compute derived properties from the register classes
62 computeRegisterProperties();
64 // Set shifts properties
65 setShiftAmountFlavor(Extend);
66 setShiftAmountType(MVT::i64);
68 // Provide all sorts of operation actions
69 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
70 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
71 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
73 setLoadExtAction(ISD::SEXTLOAD, MVT::f32, Expand);
74 setLoadExtAction(ISD::ZEXTLOAD, MVT::f32, Expand);
75 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
77 setLoadExtAction(ISD::SEXTLOAD, MVT::f64, Expand);
78 setLoadExtAction(ISD::ZEXTLOAD, MVT::f64, Expand);
79 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
81 setStackPointerRegisterToSaveRestore(SystemZ::R15D);
82 setSchedulingPreference(SchedulingForLatency);
84 setOperationAction(ISD::RET, MVT::Other, Custom);
86 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
87 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
88 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
89 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
90 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
91 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
92 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
93 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
94 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
95 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
96 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
98 setOperationAction(ISD::SDIV, MVT::i32, Expand);
99 setOperationAction(ISD::UDIV, MVT::i32, Expand);
100 setOperationAction(ISD::SDIV, MVT::i64, Expand);
101 setOperationAction(ISD::UDIV, MVT::i64, Expand);
102 setOperationAction(ISD::SREM, MVT::i32, Expand);
103 setOperationAction(ISD::UREM, MVT::i32, Expand);
104 setOperationAction(ISD::SREM, MVT::i64, Expand);
105 setOperationAction(ISD::UREM, MVT::i64, Expand);
107 // FIXME: Can we lower these 2 efficiently?
108 setOperationAction(ISD::SETCC, MVT::i32, Expand);
109 setOperationAction(ISD::SETCC, MVT::i64, Expand);
110 setOperationAction(ISD::SETCC, MVT::f32, Expand);
111 setOperationAction(ISD::SETCC, MVT::f64, Expand);
112 setOperationAction(ISD::SELECT, MVT::i32, Expand);
113 setOperationAction(ISD::SELECT, MVT::i64, Expand);
114 setOperationAction(ISD::SELECT, MVT::f32, Expand);
115 setOperationAction(ISD::SELECT, MVT::f64, Expand);
116 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
117 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
118 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
119 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
121 // Funny enough: we don't have 64-bit signed versions of these stuff, but have
123 setOperationAction(ISD::MULHS, MVT::i64, Expand);
124 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
126 setOperationAction(ISD::FSIN, MVT::f32, Expand);
127 setOperationAction(ISD::FSIN, MVT::f64, Expand);
128 setOperationAction(ISD::FCOS, MVT::f32, Expand);
129 setOperationAction(ISD::FCOS, MVT::f64, Expand);
132 SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
133 switch (Op.getOpcode()) {
134 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
135 case ISD::RET: return LowerRET(Op, DAG);
136 case ISD::CALL: return LowerCALL(Op, DAG);
137 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
138 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
139 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
140 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
141 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
143 assert(0 && "unimplemented operand");
148 //===----------------------------------------------------------------------===//
149 // Calling Convention Implementation
150 //===----------------------------------------------------------------------===//
152 #include "SystemZGenCallingConv.inc"
154 SDValue SystemZTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
156 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
159 assert(0 && "Unsupported calling convention");
161 case CallingConv::Fast:
162 return LowerCCCArguments(Op, DAG);
166 SDValue SystemZTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
167 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
168 unsigned CallingConv = TheCall->getCallingConv();
169 switch (CallingConv) {
171 assert(0 && "Unsupported calling convention");
172 case CallingConv::Fast:
174 return LowerCCCCallTo(Op, DAG, CallingConv);
178 /// LowerCCCArguments - transform physical registers into virtual registers and
179 /// generate load operations for arguments places on the stack.
180 // FIXME: struct return stuff
182 SDValue SystemZTargetLowering::LowerCCCArguments(SDValue Op,
184 MachineFunction &MF = DAG.getMachineFunction();
185 MachineFrameInfo *MFI = MF.getFrameInfo();
186 MachineRegisterInfo &RegInfo = MF.getRegInfo();
187 SDValue Root = Op.getOperand(0);
188 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
189 unsigned CC = MF.getFunction()->getCallingConv();
190 DebugLoc dl = Op.getDebugLoc();
192 // Assign locations to all of the incoming arguments.
193 SmallVector<CCValAssign, 16> ArgLocs;
194 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
195 CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_SystemZ);
197 assert(!isVarArg && "Varargs not supported yet");
199 SmallVector<SDValue, 16> ArgValues;
200 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
201 CCValAssign &VA = ArgLocs[i];
203 // Arguments passed in registers
204 MVT RegVT = VA.getLocVT();
205 TargetRegisterClass *RC;
206 switch (RegVT.getSimpleVT()) {
208 cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
209 << RegVT.getSimpleVT()
213 RC = SystemZ::GR64RegisterClass;
216 RC = SystemZ::FP32RegisterClass;
219 RC = SystemZ::FP64RegisterClass;
223 unsigned VReg = RegInfo.createVirtualRegister(RC);
224 RegInfo.addLiveIn(VA.getLocReg(), VReg);
225 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, VReg, RegVT);
227 // If this is an 8/16/32-bit value, it is really passed promoted to 64
228 // bits. Insert an assert[sz]ext to capture this, then truncate to the
230 if (VA.getLocInfo() == CCValAssign::SExt)
231 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
232 DAG.getValueType(VA.getValVT()));
233 else if (VA.getLocInfo() == CCValAssign::ZExt)
234 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
235 DAG.getValueType(VA.getValVT()));
237 if (VA.getLocInfo() != CCValAssign::Full)
238 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
240 ArgValues.push_back(ArgValue);
243 assert(VA.isMemLoc());
245 // Create the nodes corresponding to a load from this parameter slot.
246 // Create the frame index object for this incoming parameter...
247 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
248 VA.getLocMemOffset());
250 // Create the SelectionDAG nodes corresponding to a load
251 //from this parameter
252 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
253 ArgValues.push_back(DAG.getLoad(VA.getValVT(), dl, Root, FIN,
254 PseudoSourceValue::getFixedStack(FI), 0));
258 ArgValues.push_back(Root);
260 // Return the new list of results.
261 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
262 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
265 /// LowerCCCCallTo - functions arguments are copied from virtual regs to
266 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
268 SDValue SystemZTargetLowering::LowerCCCCallTo(SDValue Op, SelectionDAG &DAG,
270 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
271 SDValue Chain = TheCall->getChain();
272 SDValue Callee = TheCall->getCallee();
273 bool isVarArg = TheCall->isVarArg();
274 DebugLoc dl = Op.getDebugLoc();
275 MachineFunction &MF = DAG.getMachineFunction();
277 // Offset to first argument stack slot.
278 const unsigned FirstArgOffset = 160;
280 // Analyze operands of the call, assigning locations to each operand.
281 SmallVector<CCValAssign, 16> ArgLocs;
282 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
284 CCInfo.AnalyzeCallOperands(TheCall, CC_SystemZ);
286 // Get a count of how many bytes are to be pushed on the stack.
287 unsigned NumBytes = CCInfo.getNextStackOffset();
289 Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
290 getPointerTy(), true));
292 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
293 SmallVector<SDValue, 12> MemOpChains;
296 // Walk the register/memloc assignments, inserting copies/loads.
297 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
298 CCValAssign &VA = ArgLocs[i];
300 // Arguments start after the 5 first operands of ISD::CALL
301 SDValue Arg = TheCall->getArg(i);
303 // Promote the value if needed.
304 switch (VA.getLocInfo()) {
305 default: assert(0 && "Unknown loc info!");
306 case CCValAssign::Full: break;
307 case CCValAssign::SExt:
308 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
310 case CCValAssign::ZExt:
311 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
313 case CCValAssign::AExt:
314 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
318 // Arguments that can be passed on register must be kept at RegsToPass
321 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
323 assert(VA.isMemLoc());
325 if (StackPtr.getNode() == 0)
327 DAG.getCopyFromReg(Chain, dl,
328 (RegInfo->hasFP(MF) ?
329 SystemZ::R11D : SystemZ::R15D),
332 unsigned Offset = FirstArgOffset + VA.getLocMemOffset();
333 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
335 DAG.getIntPtrConstant(Offset));
337 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
338 PseudoSourceValue::getStack(), Offset));
342 // Transform all store nodes into one single node because all store nodes are
343 // independent of each other.
344 if (!MemOpChains.empty())
345 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
346 &MemOpChains[0], MemOpChains.size());
348 // Build a sequence of copy-to-reg nodes chained together with token chain and
349 // flag operands which copy the outgoing args into registers. The InFlag in
350 // necessary since all emited instructions must be stuck together.
352 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
353 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
354 RegsToPass[i].second, InFlag);
355 InFlag = Chain.getValue(1);
358 // If the callee is a GlobalAddress node (quite common, every direct call is)
359 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
360 // Likewise ExternalSymbol -> TargetExternalSymbol.
361 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
362 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
363 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
364 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy());
366 // Returns a chain & a flag for retval copy to use.
367 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
368 SmallVector<SDValue, 8> Ops;
369 Ops.push_back(Chain);
370 Ops.push_back(Callee);
372 // Add argument registers to the end of the list so that they are
373 // known live into the call.
374 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
375 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
376 RegsToPass[i].second.getValueType()));
378 if (InFlag.getNode())
379 Ops.push_back(InFlag);
381 Chain = DAG.getNode(SystemZISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
382 InFlag = Chain.getValue(1);
384 // Create the CALLSEQ_END node.
385 Chain = DAG.getCALLSEQ_END(Chain,
386 DAG.getConstant(NumBytes, getPointerTy(), true),
387 DAG.getConstant(0, getPointerTy(), true),
389 InFlag = Chain.getValue(1);
391 // Handle result values, copying them out of physregs into vregs that we
393 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
397 /// LowerCallResult - Lower the result values of an ISD::CALL into the
398 /// appropriate copies out of appropriate physical registers. This assumes that
399 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
400 /// being lowered. Returns a SDNode with the same number of values as the
403 SystemZTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
405 unsigned CallingConv,
407 bool isVarArg = TheCall->isVarArg();
408 DebugLoc dl = TheCall->getDebugLoc();
410 // Assign locations to each value returned by this call.
411 SmallVector<CCValAssign, 16> RVLocs;
412 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
414 CCInfo.AnalyzeCallResult(TheCall, RetCC_SystemZ);
415 SmallVector<SDValue, 8> ResultVals;
417 // Copy all of the result registers out of their specified physreg.
418 for (unsigned i = 0; i != RVLocs.size(); ++i) {
419 CCValAssign &VA = RVLocs[i];
421 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
422 VA.getLocVT(), InFlag).getValue(1);
423 SDValue RetValue = Chain.getValue(0);
424 InFlag = Chain.getValue(2);
426 // If this is an 8/16/32-bit value, it is really passed promoted to 64
427 // bits. Insert an assert[sz]ext to capture this, then truncate to the
429 if (VA.getLocInfo() == CCValAssign::SExt)
430 RetValue = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), RetValue,
431 DAG.getValueType(VA.getValVT()));
432 else if (VA.getLocInfo() == CCValAssign::ZExt)
433 RetValue = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), RetValue,
434 DAG.getValueType(VA.getValVT()));
436 if (VA.getLocInfo() != CCValAssign::Full)
437 RetValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), RetValue);
439 ResultVals.push_back(RetValue);
442 ResultVals.push_back(Chain);
444 // Merge everything together with a MERGE_VALUES node.
445 return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
446 &ResultVals[0], ResultVals.size()).getNode();
450 SDValue SystemZTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
451 // CCValAssign - represent the assignment of the return value to a location
452 SmallVector<CCValAssign, 16> RVLocs;
453 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
454 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
455 DebugLoc dl = Op.getDebugLoc();
457 // CCState - Info about the registers and stack slot.
458 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
460 // Analize return values of ISD::RET
461 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_SystemZ);
463 // If this is the first return lowered for this function, add the regs to the
464 // liveout set for the function.
465 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
466 for (unsigned i = 0; i != RVLocs.size(); ++i)
467 if (RVLocs[i].isRegLoc())
468 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
471 // The chain is always operand #0
472 SDValue Chain = Op.getOperand(0);
475 // Copy the result values into the output registers.
476 for (unsigned i = 0; i != RVLocs.size(); ++i) {
477 CCValAssign &VA = RVLocs[i];
478 SDValue ResValue = Op.getOperand(i*2+1);
479 assert(VA.isRegLoc() && "Can only return in registers!");
481 // If this is an 8/16/32-bit value, it is really should be passed promoted
483 if (VA.getLocInfo() == CCValAssign::SExt)
484 ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue);
485 else if (VA.getLocInfo() == CCValAssign::ZExt)
486 ResValue = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ResValue);
487 else if (VA.getLocInfo() == CCValAssign::AExt)
488 ResValue = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ResValue);
490 // ISD::RET => ret chain, (regnum1,val1), ...
491 // So i*2+1 index only the regnums
492 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ResValue, Flag);
494 // Guarantee that all emitted copies are stuck together,
495 // avoiding something bad.
496 Flag = Chain.getValue(1);
500 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
503 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain);
506 SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS,
507 ISD::CondCode CC, SDValue &SystemZCC,
509 // FIXME: Emit a test if RHS is zero
511 bool isUnsigned = false;
512 SystemZCC::CondCodes TCC;
514 default: assert(0 && "Invalid integer condition!");
520 TCC = SystemZCC::NLH;
536 if (LHS.getValueType().isFloatingPoint()) {
540 isUnsigned = true; // FALLTHROUGH
546 if (LHS.getValueType().isFloatingPoint()) {
550 isUnsigned = true; // FALLTHROUGH
556 if (LHS.getValueType().isFloatingPoint()) {
557 TCC = SystemZCC::NLE;
560 isUnsigned = true; // FALLTHROUGH
566 if (LHS.getValueType().isFloatingPoint()) {
567 TCC = SystemZCC::NHE;
570 isUnsigned = true; // FALLTHROUGH
577 SystemZCC = DAG.getConstant(TCC, MVT::i32);
579 DebugLoc dl = LHS.getDebugLoc();
580 return DAG.getNode((isUnsigned ? SystemZISD::UCMP : SystemZISD::CMP),
581 dl, MVT::Flag, LHS, RHS);
585 SDValue SystemZTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
586 SDValue Chain = Op.getOperand(0);
587 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
588 SDValue LHS = Op.getOperand(2);
589 SDValue RHS = Op.getOperand(3);
590 SDValue Dest = Op.getOperand(4);
591 DebugLoc dl = Op.getDebugLoc();
594 SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG);
595 return DAG.getNode(SystemZISD::BRCOND, dl, Op.getValueType(),
596 Chain, Dest, SystemZCC, Flag);
599 SDValue SystemZTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
600 SDValue LHS = Op.getOperand(0);
601 SDValue RHS = Op.getOperand(1);
602 SDValue TrueV = Op.getOperand(2);
603 SDValue FalseV = Op.getOperand(3);
604 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
605 DebugLoc dl = Op.getDebugLoc();
608 SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG);
610 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
611 SmallVector<SDValue, 4> Ops;
612 Ops.push_back(TrueV);
613 Ops.push_back(FalseV);
614 Ops.push_back(SystemZCC);
617 return DAG.getNode(SystemZISD::SELECT, dl, VTs, &Ops[0], Ops.size());
620 SDValue SystemZTargetLowering::LowerGlobalAddress(SDValue Op,
622 DebugLoc dl = Op.getDebugLoc();
623 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
624 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
626 bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_;
627 bool ExtraLoadRequired =
628 Subtarget.GVRequiresExtraLoad(GV, getTargetMachine(), false);
631 if (!IsPic && !ExtraLoadRequired) {
632 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
635 unsigned char OpFlags = 0;
636 if (ExtraLoadRequired)
637 OpFlags = SystemZII::MO_GOTENT;
639 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
642 Result = DAG.getNode(SystemZISD::PCRelativeWrapper, dl,
643 getPointerTy(), Result);
645 if (ExtraLoadRequired)
646 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
647 PseudoSourceValue::getGOT(), 0);
649 // If there was a non-zero offset that we didn't fold, create an explicit
652 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
653 DAG.getConstant(Offset, getPointerTy()));
659 SDValue SystemZTargetLowering::LowerJumpTable(SDValue Op,
661 DebugLoc dl = Op.getDebugLoc();
662 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
663 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
665 return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result);
670 // FIXME: This is just dirty hack. We need to lower cpool properly
671 SDValue SystemZTargetLowering::LowerConstantPool(SDValue Op,
673 DebugLoc dl = Op.getDebugLoc();
674 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
676 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
680 return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result);
683 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
685 case SystemZISD::RET_FLAG: return "SystemZISD::RET_FLAG";
686 case SystemZISD::CALL: return "SystemZISD::CALL";
687 case SystemZISD::BRCOND: return "SystemZISD::BRCOND";
688 case SystemZISD::CMP: return "SystemZISD::CMP";
689 case SystemZISD::UCMP: return "SystemZISD::UCMP";
690 case SystemZISD::SELECT: return "SystemZISD::SELECT";
691 case SystemZISD::PCRelativeWrapper: return "SystemZISD::PCRelativeWrapper";
692 default: return NULL;
696 //===----------------------------------------------------------------------===//
697 // Other Lowering Code
698 //===----------------------------------------------------------------------===//
701 SystemZTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
702 MachineBasicBlock *BB) const {
703 const SystemZInstrInfo &TII = *TM.getInstrInfo();
704 DebugLoc dl = MI->getDebugLoc();
705 assert((MI->getOpcode() == SystemZ::Select32 ||
706 MI->getOpcode() == SystemZ::SelectF32 ||
707 MI->getOpcode() == SystemZ::Select64 ||
708 MI->getOpcode() == SystemZ::SelectF64) &&
709 "Unexpected instr type to insert");
711 // To "insert" a SELECT instruction, we actually have to insert the diamond
712 // control-flow pattern. The incoming instruction knows the destination vreg
713 // to set, the condition code register to branch on, the true/false values to
714 // select between, and a branch opcode to use.
715 const BasicBlock *LLVM_BB = BB->getBasicBlock();
716 MachineFunction::iterator I = BB;
724 // fallthrough --> copy0MBB
725 MachineBasicBlock *thisMBB = BB;
726 MachineFunction *F = BB->getParent();
727 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
728 MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
729 SystemZCC::CondCodes CC = (SystemZCC::CondCodes)MI->getOperand(3).getImm();
730 BuildMI(BB, dl, TII.getBrCond(CC)).addMBB(copy1MBB);
731 F->insert(I, copy0MBB);
732 F->insert(I, copy1MBB);
733 // Update machine-CFG edges by transferring all successors of the current
734 // block to the new block which will contain the Phi node for the select.
735 copy1MBB->transferSuccessors(BB);
736 // Next, add the true and fallthrough blocks as its successors.
737 BB->addSuccessor(copy0MBB);
738 BB->addSuccessor(copy1MBB);
742 // # fallthrough to copy1MBB
745 // Update machine-CFG edges
746 BB->addSuccessor(copy1MBB);
749 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
752 BuildMI(BB, dl, TII.get(SystemZ::PHI),
753 MI->getOperand(0).getReg())
754 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
755 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
757 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.