1 //===-- SystemZISelLowering.cpp - SystemZ DAG lowering implementation -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SystemZTargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "systemz-lower"
16 #include "SystemZISelLowering.h"
17 #include "SystemZCallingConv.h"
18 #include "SystemZConstantPoolValue.h"
19 #include "SystemZMachineFunctionInfo.h"
20 #include "SystemZTargetMachine.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
31 // Represents a sequence for extracting a 0/1 value from an IPM result:
32 // (((X ^ XORValue) + AddValue) >> Bit)
33 struct IPMConversion {
34 IPMConversion(unsigned xorValue, int64_t addValue, unsigned bit)
35 : XORValue(xorValue), AddValue(addValue), Bit(bit) {}
43 // Classify VT as either 32 or 64 bit.
44 static bool is32Bit(EVT VT) {
45 switch (VT.getSimpleVT().SimpleTy) {
51 llvm_unreachable("Unsupported type");
55 // Return a version of MachineOperand that can be safely used before the
57 static MachineOperand earlyUseOperand(MachineOperand Op) {
63 SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm)
64 : TargetLowering(tm, new TargetLoweringObjectFileELF()),
65 Subtarget(*tm.getSubtargetImpl()), TM(tm) {
66 MVT PtrVT = getPointerTy();
68 // Set up the register classes.
69 if (Subtarget.hasHighWord())
70 addRegisterClass(MVT::i32, &SystemZ::GRX32BitRegClass);
72 addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass);
73 addRegisterClass(MVT::i64, &SystemZ::GR64BitRegClass);
74 addRegisterClass(MVT::f32, &SystemZ::FP32BitRegClass);
75 addRegisterClass(MVT::f64, &SystemZ::FP64BitRegClass);
76 addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass);
78 // Compute derived properties from the register classes
79 computeRegisterProperties();
81 // Set up special registers.
82 setExceptionPointerRegister(SystemZ::R6D);
83 setExceptionSelectorRegister(SystemZ::R7D);
84 setStackPointerRegisterToSaveRestore(SystemZ::R15D);
86 // TODO: It may be better to default to latency-oriented scheduling, however
87 // LLVM's current latency-oriented scheduler can't handle physreg definitions
88 // such as SystemZ has with CC, so set this to the register-pressure
89 // scheduler, because it can.
90 setSchedulingPreference(Sched::RegPressure);
92 setBooleanContents(ZeroOrOneBooleanContent);
93 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
95 // Instructions are strings of 2-byte aligned 2-byte values.
96 setMinFunctionAlignment(2);
98 // Handle operations that are handled in a similar way for all types.
99 for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
100 I <= MVT::LAST_FP_VALUETYPE;
102 MVT VT = MVT::SimpleValueType(I);
103 if (isTypeLegal(VT)) {
104 // Lower SET_CC into an IPM-based sequence.
105 setOperationAction(ISD::SETCC, VT, Custom);
107 // Expand SELECT(C, A, B) into SELECT_CC(X, 0, A, B, NE).
108 setOperationAction(ISD::SELECT, VT, Expand);
110 // Lower SELECT_CC and BR_CC into separate comparisons and branches.
111 setOperationAction(ISD::SELECT_CC, VT, Custom);
112 setOperationAction(ISD::BR_CC, VT, Custom);
116 // Expand jump table branches as address arithmetic followed by an
118 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
120 // Expand BRCOND into a BR_CC (see above).
121 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
123 // Handle integer types.
124 for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
125 I <= MVT::LAST_INTEGER_VALUETYPE;
127 MVT VT = MVT::SimpleValueType(I);
128 if (isTypeLegal(VT)) {
129 // Expand individual DIV and REMs into DIVREMs.
130 setOperationAction(ISD::SDIV, VT, Expand);
131 setOperationAction(ISD::UDIV, VT, Expand);
132 setOperationAction(ISD::SREM, VT, Expand);
133 setOperationAction(ISD::UREM, VT, Expand);
134 setOperationAction(ISD::SDIVREM, VT, Custom);
135 setOperationAction(ISD::UDIVREM, VT, Custom);
137 // Expand ATOMIC_LOAD and ATOMIC_STORE using ATOMIC_CMP_SWAP.
138 // FIXME: probably much too conservative.
139 setOperationAction(ISD::ATOMIC_LOAD, VT, Expand);
140 setOperationAction(ISD::ATOMIC_STORE, VT, Expand);
142 // No special instructions for these.
143 setOperationAction(ISD::CTPOP, VT, Expand);
144 setOperationAction(ISD::CTTZ, VT, Expand);
145 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
146 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
147 setOperationAction(ISD::ROTR, VT, Expand);
149 // Use *MUL_LOHI where possible instead of MULH*.
150 setOperationAction(ISD::MULHS, VT, Expand);
151 setOperationAction(ISD::MULHU, VT, Expand);
152 setOperationAction(ISD::SMUL_LOHI, VT, Custom);
153 setOperationAction(ISD::UMUL_LOHI, VT, Custom);
155 // We have instructions for signed but not unsigned FP conversion.
156 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
160 // Type legalization will convert 8- and 16-bit atomic operations into
161 // forms that operate on i32s (but still keeping the original memory VT).
162 // Lower them into full i32 operations.
163 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Custom);
164 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Custom);
165 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
166 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Custom);
167 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Custom);
168 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Custom);
169 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Custom);
170 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Custom);
171 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Custom);
172 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Custom);
173 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Custom);
174 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
176 // We have instructions for signed but not unsigned FP conversion.
177 // Handle unsigned 32-bit types as signed 64-bit types.
178 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote);
179 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
181 // We have native support for a 64-bit CTLZ, via FLOGR.
182 setOperationAction(ISD::CTLZ, MVT::i32, Promote);
183 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
185 // Give LowerOperation the chance to replace 64-bit ORs with subregs.
186 setOperationAction(ISD::OR, MVT::i64, Custom);
188 // FIXME: Can we support these natively?
189 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
190 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
191 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
193 // We have native instructions for i8, i16 and i32 extensions, but not i1.
194 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
195 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
196 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
197 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
199 // Handle the various types of symbolic address.
200 setOperationAction(ISD::ConstantPool, PtrVT, Custom);
201 setOperationAction(ISD::GlobalAddress, PtrVT, Custom);
202 setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom);
203 setOperationAction(ISD::BlockAddress, PtrVT, Custom);
204 setOperationAction(ISD::JumpTable, PtrVT, Custom);
206 // We need to handle dynamic allocations specially because of the
207 // 160-byte area at the bottom of the stack.
208 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
210 // Use custom expanders so that we can force the function to use
212 setOperationAction(ISD::STACKSAVE, MVT::Other, Custom);
213 setOperationAction(ISD::STACKRESTORE, MVT::Other, Custom);
215 // Handle prefetches with PFD or PFDRL.
216 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
218 // Handle floating-point types.
219 for (unsigned I = MVT::FIRST_FP_VALUETYPE;
220 I <= MVT::LAST_FP_VALUETYPE;
222 MVT VT = MVT::SimpleValueType(I);
223 if (isTypeLegal(VT)) {
224 // We can use FI for FRINT.
225 setOperationAction(ISD::FRINT, VT, Legal);
227 // We can use the extended form of FI for other rounding operations.
228 if (Subtarget.hasFPExtension()) {
229 setOperationAction(ISD::FNEARBYINT, VT, Legal);
230 setOperationAction(ISD::FFLOOR, VT, Legal);
231 setOperationAction(ISD::FCEIL, VT, Legal);
232 setOperationAction(ISD::FTRUNC, VT, Legal);
233 setOperationAction(ISD::FROUND, VT, Legal);
236 // No special instructions for these.
237 setOperationAction(ISD::FSIN, VT, Expand);
238 setOperationAction(ISD::FCOS, VT, Expand);
239 setOperationAction(ISD::FREM, VT, Expand);
243 // We have fused multiply-addition for f32 and f64 but not f128.
244 setOperationAction(ISD::FMA, MVT::f32, Legal);
245 setOperationAction(ISD::FMA, MVT::f64, Legal);
246 setOperationAction(ISD::FMA, MVT::f128, Expand);
248 // Needed so that we don't try to implement f128 constant loads using
249 // a load-and-extend of a f80 constant (in cases where the constant
250 // would fit in an f80).
251 setLoadExtAction(ISD::EXTLOAD, MVT::f80, Expand);
253 // Floating-point truncation and stores need to be done separately.
254 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
255 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
256 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
258 // We have 64-bit FPR<->GPR moves, but need special handling for
260 setOperationAction(ISD::BITCAST, MVT::i32, Custom);
261 setOperationAction(ISD::BITCAST, MVT::f32, Custom);
263 // VASTART and VACOPY need to deal with the SystemZ-specific varargs
264 // structure, but VAEND is a no-op.
265 setOperationAction(ISD::VASTART, MVT::Other, Custom);
266 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
267 setOperationAction(ISD::VAEND, MVT::Other, Expand);
269 // We want to use MVC in preference to even a single load/store pair.
270 MaxStoresPerMemcpy = 0;
271 MaxStoresPerMemcpyOptSize = 0;
273 // The main memset sequence is a byte store followed by an MVC.
274 // Two STC or MV..I stores win over that, but the kind of fused stores
275 // generated by target-independent code don't when the byte value is
276 // variable. E.g. "STC <reg>;MHI <reg>,257;STH <reg>" is not better
277 // than "STC;MVC". Handle the choice in target-specific code instead.
278 MaxStoresPerMemset = 0;
279 MaxStoresPerMemsetOptSize = 0;
282 EVT SystemZTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
285 return VT.changeVectorElementTypeToInteger();
288 bool SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
289 VT = VT.getScalarType();
294 switch (VT.getSimpleVT().SimpleTy) {
307 bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
308 // We can load zero using LZ?R and negative zero using LZ?R;LC?BR.
309 return Imm.isZero() || Imm.isNegZero();
312 bool SystemZTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
314 // Unaligned accesses should never be slower than the expanded version.
315 // We check specifically for aligned accesses in the few cases where
316 // they are required.
322 bool SystemZTargetLowering::isLegalAddressingMode(const AddrMode &AM,
324 // Punt on globals for now, although they can be used in limited
325 // RELATIVE LONG cases.
329 // Require a 20-bit signed offset.
330 if (!isInt<20>(AM.BaseOffs))
333 // Indexing is OK but no scale factor can be applied.
334 return AM.Scale == 0 || AM.Scale == 1;
337 bool SystemZTargetLowering::isTruncateFree(Type *FromType, Type *ToType) const {
338 if (!FromType->isIntegerTy() || !ToType->isIntegerTy())
340 unsigned FromBits = FromType->getPrimitiveSizeInBits();
341 unsigned ToBits = ToType->getPrimitiveSizeInBits();
342 return FromBits > ToBits;
345 bool SystemZTargetLowering::isTruncateFree(EVT FromVT, EVT ToVT) const {
346 if (!FromVT.isInteger() || !ToVT.isInteger())
348 unsigned FromBits = FromVT.getSizeInBits();
349 unsigned ToBits = ToVT.getSizeInBits();
350 return FromBits > ToBits;
353 //===----------------------------------------------------------------------===//
354 // Inline asm support
355 //===----------------------------------------------------------------------===//
357 TargetLowering::ConstraintType
358 SystemZTargetLowering::getConstraintType(const std::string &Constraint) const {
359 if (Constraint.size() == 1) {
360 switch (Constraint[0]) {
361 case 'a': // Address register
362 case 'd': // Data register (equivalent to 'r')
363 case 'f': // Floating-point register
364 case 'h': // High-part register
365 case 'r': // General-purpose register
366 return C_RegisterClass;
368 case 'Q': // Memory with base and unsigned 12-bit displacement
369 case 'R': // Likewise, plus an index
370 case 'S': // Memory with base and signed 20-bit displacement
371 case 'T': // Likewise, plus an index
372 case 'm': // Equivalent to 'T'.
375 case 'I': // Unsigned 8-bit constant
376 case 'J': // Unsigned 12-bit constant
377 case 'K': // Signed 16-bit constant
378 case 'L': // Signed 20-bit displacement (on all targets we support)
379 case 'M': // 0x7fffffff
386 return TargetLowering::getConstraintType(Constraint);
389 TargetLowering::ConstraintWeight SystemZTargetLowering::
390 getSingleConstraintMatchWeight(AsmOperandInfo &info,
391 const char *constraint) const {
392 ConstraintWeight weight = CW_Invalid;
393 Value *CallOperandVal = info.CallOperandVal;
394 // If we don't have a value, we can't do a match,
395 // but allow it at the lowest weight.
396 if (CallOperandVal == NULL)
398 Type *type = CallOperandVal->getType();
399 // Look at the constraint type.
400 switch (*constraint) {
402 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
405 case 'a': // Address register
406 case 'd': // Data register (equivalent to 'r')
407 case 'h': // High-part register
408 case 'r': // General-purpose register
409 if (CallOperandVal->getType()->isIntegerTy())
410 weight = CW_Register;
413 case 'f': // Floating-point register
414 if (type->isFloatingPointTy())
415 weight = CW_Register;
418 case 'I': // Unsigned 8-bit constant
419 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
420 if (isUInt<8>(C->getZExtValue()))
421 weight = CW_Constant;
424 case 'J': // Unsigned 12-bit constant
425 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
426 if (isUInt<12>(C->getZExtValue()))
427 weight = CW_Constant;
430 case 'K': // Signed 16-bit constant
431 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
432 if (isInt<16>(C->getSExtValue()))
433 weight = CW_Constant;
436 case 'L': // Signed 20-bit displacement (on all targets we support)
437 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
438 if (isInt<20>(C->getSExtValue()))
439 weight = CW_Constant;
442 case 'M': // 0x7fffffff
443 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
444 if (C->getZExtValue() == 0x7fffffff)
445 weight = CW_Constant;
451 // Parse a "{tNNN}" register constraint for which the register type "t"
452 // has already been verified. MC is the class associated with "t" and
453 // Map maps 0-based register numbers to LLVM register numbers.
454 static std::pair<unsigned, const TargetRegisterClass *>
455 parseRegisterNumber(const std::string &Constraint,
456 const TargetRegisterClass *RC, const unsigned *Map) {
457 assert(*(Constraint.end()-1) == '}' && "Missing '}'");
458 if (isdigit(Constraint[2])) {
459 std::string Suffix(Constraint.data() + 2, Constraint.size() - 2);
460 unsigned Index = atoi(Suffix.c_str());
461 if (Index < 16 && Map[Index])
462 return std::make_pair(Map[Index], RC);
464 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
467 std::pair<unsigned, const TargetRegisterClass *> SystemZTargetLowering::
468 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const {
469 if (Constraint.size() == 1) {
470 // GCC Constraint Letters
471 switch (Constraint[0]) {
473 case 'd': // Data register (equivalent to 'r')
474 case 'r': // General-purpose register
476 return std::make_pair(0U, &SystemZ::GR64BitRegClass);
477 else if (VT == MVT::i128)
478 return std::make_pair(0U, &SystemZ::GR128BitRegClass);
479 return std::make_pair(0U, &SystemZ::GR32BitRegClass);
481 case 'a': // Address register
483 return std::make_pair(0U, &SystemZ::ADDR64BitRegClass);
484 else if (VT == MVT::i128)
485 return std::make_pair(0U, &SystemZ::ADDR128BitRegClass);
486 return std::make_pair(0U, &SystemZ::ADDR32BitRegClass);
488 case 'h': // High-part register (an LLVM extension)
489 return std::make_pair(0U, &SystemZ::GRH32BitRegClass);
491 case 'f': // Floating-point register
493 return std::make_pair(0U, &SystemZ::FP64BitRegClass);
494 else if (VT == MVT::f128)
495 return std::make_pair(0U, &SystemZ::FP128BitRegClass);
496 return std::make_pair(0U, &SystemZ::FP32BitRegClass);
499 if (Constraint[0] == '{') {
500 // We need to override the default register parsing for GPRs and FPRs
501 // because the interpretation depends on VT. The internal names of
502 // the registers are also different from the external names
503 // (F0D and F0S instead of F0, etc.).
504 if (Constraint[1] == 'r') {
506 return parseRegisterNumber(Constraint, &SystemZ::GR32BitRegClass,
507 SystemZMC::GR32Regs);
509 return parseRegisterNumber(Constraint, &SystemZ::GR128BitRegClass,
510 SystemZMC::GR128Regs);
511 return parseRegisterNumber(Constraint, &SystemZ::GR64BitRegClass,
512 SystemZMC::GR64Regs);
514 if (Constraint[1] == 'f') {
516 return parseRegisterNumber(Constraint, &SystemZ::FP32BitRegClass,
517 SystemZMC::FP32Regs);
519 return parseRegisterNumber(Constraint, &SystemZ::FP128BitRegClass,
520 SystemZMC::FP128Regs);
521 return parseRegisterNumber(Constraint, &SystemZ::FP64BitRegClass,
522 SystemZMC::FP64Regs);
525 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
528 void SystemZTargetLowering::
529 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
530 std::vector<SDValue> &Ops,
531 SelectionDAG &DAG) const {
532 // Only support length 1 constraints for now.
533 if (Constraint.length() == 1) {
534 switch (Constraint[0]) {
535 case 'I': // Unsigned 8-bit constant
536 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
537 if (isUInt<8>(C->getZExtValue()))
538 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
542 case 'J': // Unsigned 12-bit constant
543 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
544 if (isUInt<12>(C->getZExtValue()))
545 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
549 case 'K': // Signed 16-bit constant
550 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
551 if (isInt<16>(C->getSExtValue()))
552 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
556 case 'L': // Signed 20-bit displacement (on all targets we support)
557 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
558 if (isInt<20>(C->getSExtValue()))
559 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
563 case 'M': // 0x7fffffff
564 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
565 if (C->getZExtValue() == 0x7fffffff)
566 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
571 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
574 //===----------------------------------------------------------------------===//
575 // Calling conventions
576 //===----------------------------------------------------------------------===//
578 #include "SystemZGenCallingConv.inc"
580 bool SystemZTargetLowering::allowTruncateForTailCall(Type *FromType,
581 Type *ToType) const {
582 return isTruncateFree(FromType, ToType);
585 bool SystemZTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
586 if (!CI->isTailCall())
591 // Value is a value that has been passed to us in the location described by VA
592 // (and so has type VA.getLocVT()). Convert Value to VA.getValVT(), chaining
593 // any loads onto Chain.
594 static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDLoc DL,
595 CCValAssign &VA, SDValue Chain,
597 // If the argument has been promoted from a smaller type, insert an
598 // assertion to capture this.
599 if (VA.getLocInfo() == CCValAssign::SExt)
600 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value,
601 DAG.getValueType(VA.getValVT()));
602 else if (VA.getLocInfo() == CCValAssign::ZExt)
603 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value,
604 DAG.getValueType(VA.getValVT()));
607 Value = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Value);
608 else if (VA.getLocInfo() == CCValAssign::Indirect)
609 Value = DAG.getLoad(VA.getValVT(), DL, Chain, Value,
610 MachinePointerInfo(), false, false, false, 0);
612 assert(VA.getLocInfo() == CCValAssign::Full && "Unsupported getLocInfo");
616 // Value is a value of type VA.getValVT() that we need to copy into
617 // the location described by VA. Return a copy of Value converted to
618 // VA.getValVT(). The caller is responsible for handling indirect values.
619 static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDLoc DL,
620 CCValAssign &VA, SDValue Value) {
621 switch (VA.getLocInfo()) {
622 case CCValAssign::SExt:
623 return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value);
624 case CCValAssign::ZExt:
625 return DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Value);
626 case CCValAssign::AExt:
627 return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value);
628 case CCValAssign::Full:
631 llvm_unreachable("Unhandled getLocInfo()");
635 SDValue SystemZTargetLowering::
636 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
637 const SmallVectorImpl<ISD::InputArg> &Ins,
638 SDLoc DL, SelectionDAG &DAG,
639 SmallVectorImpl<SDValue> &InVals) const {
640 MachineFunction &MF = DAG.getMachineFunction();
641 MachineFrameInfo *MFI = MF.getFrameInfo();
642 MachineRegisterInfo &MRI = MF.getRegInfo();
643 SystemZMachineFunctionInfo *FuncInfo =
644 MF.getInfo<SystemZMachineFunctionInfo>();
645 const SystemZFrameLowering *TFL =
646 static_cast<const SystemZFrameLowering *>(TM.getFrameLowering());
648 // Assign locations to all of the incoming arguments.
649 SmallVector<CCValAssign, 16> ArgLocs;
650 CCState CCInfo(CallConv, IsVarArg, MF, TM, ArgLocs, *DAG.getContext());
651 CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ);
653 unsigned NumFixedGPRs = 0;
654 unsigned NumFixedFPRs = 0;
655 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
657 CCValAssign &VA = ArgLocs[I];
658 EVT LocVT = VA.getLocVT();
660 // Arguments passed in registers
661 const TargetRegisterClass *RC;
662 switch (LocVT.getSimpleVT().SimpleTy) {
664 // Integers smaller than i64 should be promoted to i64.
665 llvm_unreachable("Unexpected argument type");
668 RC = &SystemZ::GR32BitRegClass;
672 RC = &SystemZ::GR64BitRegClass;
676 RC = &SystemZ::FP32BitRegClass;
680 RC = &SystemZ::FP64BitRegClass;
684 unsigned VReg = MRI.createVirtualRegister(RC);
685 MRI.addLiveIn(VA.getLocReg(), VReg);
686 ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
688 assert(VA.isMemLoc() && "Argument not register or memory");
690 // Create the frame index object for this incoming parameter.
691 int FI = MFI->CreateFixedObject(LocVT.getSizeInBits() / 8,
692 VA.getLocMemOffset(), true);
694 // Create the SelectionDAG nodes corresponding to a load
695 // from this parameter. Unpromoted ints and floats are
696 // passed as right-justified 8-byte values.
697 EVT PtrVT = getPointerTy();
698 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
699 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
700 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4));
701 ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN,
702 MachinePointerInfo::getFixedStack(FI),
703 false, false, false, 0);
706 // Convert the value of the argument register into the value that's
708 InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, ArgValue));
712 // Save the number of non-varargs registers for later use by va_start, etc.
713 FuncInfo->setVarArgsFirstGPR(NumFixedGPRs);
714 FuncInfo->setVarArgsFirstFPR(NumFixedFPRs);
716 // Likewise the address (in the form of a frame index) of where the
717 // first stack vararg would be. The 1-byte size here is arbitrary.
718 int64_t StackSize = CCInfo.getNextStackOffset();
719 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize, true));
721 // ...and a similar frame index for the caller-allocated save area
722 // that will be used to store the incoming registers.
723 int64_t RegSaveOffset = TFL->getOffsetOfLocalArea();
724 unsigned RegSaveIndex = MFI->CreateFixedObject(1, RegSaveOffset, true);
725 FuncInfo->setRegSaveFrameIndex(RegSaveIndex);
727 // Store the FPR varargs in the reserved frame slots. (We store the
728 // GPRs as part of the prologue.)
729 if (NumFixedFPRs < SystemZ::NumArgFPRs) {
730 SDValue MemOps[SystemZ::NumArgFPRs];
731 for (unsigned I = NumFixedFPRs; I < SystemZ::NumArgFPRs; ++I) {
732 unsigned Offset = TFL->getRegSpillOffset(SystemZ::ArgFPRs[I]);
733 int FI = MFI->CreateFixedObject(8, RegSaveOffset + Offset, true);
734 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
735 unsigned VReg = MF.addLiveIn(SystemZ::ArgFPRs[I],
736 &SystemZ::FP64BitRegClass);
737 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f64);
738 MemOps[I] = DAG.getStore(ArgValue.getValue(1), DL, ArgValue, FIN,
739 MachinePointerInfo::getFixedStack(FI),
743 // Join the stores, which are independent of one another.
744 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
745 &MemOps[NumFixedFPRs],
746 SystemZ::NumArgFPRs - NumFixedFPRs);
753 static bool canUseSiblingCall(CCState ArgCCInfo,
754 SmallVectorImpl<CCValAssign> &ArgLocs) {
755 // Punt if there are any indirect or stack arguments, or if the call
756 // needs the call-saved argument register R6.
757 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
758 CCValAssign &VA = ArgLocs[I];
759 if (VA.getLocInfo() == CCValAssign::Indirect)
763 unsigned Reg = VA.getLocReg();
764 if (Reg == SystemZ::R6H || Reg == SystemZ::R6L || Reg == SystemZ::R6D)
771 SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
772 SmallVectorImpl<SDValue> &InVals) const {
773 SelectionDAG &DAG = CLI.DAG;
775 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
776 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
777 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
778 SDValue Chain = CLI.Chain;
779 SDValue Callee = CLI.Callee;
780 bool &IsTailCall = CLI.IsTailCall;
781 CallingConv::ID CallConv = CLI.CallConv;
782 bool IsVarArg = CLI.IsVarArg;
783 MachineFunction &MF = DAG.getMachineFunction();
784 EVT PtrVT = getPointerTy();
786 // Analyze the operands of the call, assigning locations to each operand.
787 SmallVector<CCValAssign, 16> ArgLocs;
788 CCState ArgCCInfo(CallConv, IsVarArg, MF, TM, ArgLocs, *DAG.getContext());
789 ArgCCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
791 // We don't support GuaranteedTailCallOpt, only automatically-detected
793 if (IsTailCall && !canUseSiblingCall(ArgCCInfo, ArgLocs))
796 // Get a count of how many bytes are to be pushed on the stack.
797 unsigned NumBytes = ArgCCInfo.getNextStackOffset();
799 // Mark the start of the call.
801 Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes, PtrVT, true),
804 // Copy argument values to their designated locations.
805 SmallVector<std::pair<unsigned, SDValue>, 9> RegsToPass;
806 SmallVector<SDValue, 8> MemOpChains;
808 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
809 CCValAssign &VA = ArgLocs[I];
810 SDValue ArgValue = OutVals[I];
812 if (VA.getLocInfo() == CCValAssign::Indirect) {
813 // Store the argument in a stack slot and pass its address.
814 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
815 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
816 MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, SpillSlot,
817 MachinePointerInfo::getFixedStack(FI),
819 ArgValue = SpillSlot;
821 ArgValue = convertValVTToLocVT(DAG, DL, VA, ArgValue);
824 // Queue up the argument copies and emit them at the end.
825 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));
827 assert(VA.isMemLoc() && "Argument not register or memory");
829 // Work out the address of the stack slot. Unpromoted ints and
830 // floats are passed as right-justified 8-byte values.
831 if (!StackPtr.getNode())
832 StackPtr = DAG.getCopyFromReg(Chain, DL, SystemZ::R15D, PtrVT);
833 unsigned Offset = SystemZMC::CallFrameSize + VA.getLocMemOffset();
834 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
836 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
837 DAG.getIntPtrConstant(Offset));
840 MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, Address,
841 MachinePointerInfo(),
846 // Join the stores, which are independent of one another.
847 if (!MemOpChains.empty())
848 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
849 &MemOpChains[0], MemOpChains.size());
851 // Accept direct calls by converting symbolic call addresses to the
852 // associated Target* opcodes. Force %r1 to be used for indirect
855 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
856 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT);
857 Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
858 } else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
859 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT);
860 Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
861 } else if (IsTailCall) {
862 Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R1D, Callee, Glue);
863 Glue = Chain.getValue(1);
864 Callee = DAG.getRegister(SystemZ::R1D, Callee.getValueType());
867 // Build a sequence of copy-to-reg nodes, chained and glued together.
868 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {
869 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
870 RegsToPass[I].second, Glue);
871 Glue = Chain.getValue(1);
874 // The first call operand is the chain and the second is the target address.
875 SmallVector<SDValue, 8> Ops;
876 Ops.push_back(Chain);
877 Ops.push_back(Callee);
879 // Add argument registers to the end of the list so that they are
880 // known live into the call.
881 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I)
882 Ops.push_back(DAG.getRegister(RegsToPass[I].first,
883 RegsToPass[I].second.getValueType()));
885 // Glue the call to the argument copies, if any.
890 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
892 return DAG.getNode(SystemZISD::SIBCALL, DL, NodeTys, &Ops[0], Ops.size());
893 Chain = DAG.getNode(SystemZISD::CALL, DL, NodeTys, &Ops[0], Ops.size());
894 Glue = Chain.getValue(1);
896 // Mark the end of the call, which is glued to the call itself.
897 Chain = DAG.getCALLSEQ_END(Chain,
898 DAG.getConstant(NumBytes, PtrVT, true),
899 DAG.getConstant(0, PtrVT, true),
901 Glue = Chain.getValue(1);
903 // Assign locations to each value returned by this call.
904 SmallVector<CCValAssign, 16> RetLocs;
905 CCState RetCCInfo(CallConv, IsVarArg, MF, TM, RetLocs, *DAG.getContext());
906 RetCCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ);
908 // Copy all of the result registers out of their specified physreg.
909 for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
910 CCValAssign &VA = RetLocs[I];
912 // Copy the value out, gluing the copy to the end of the call sequence.
913 SDValue RetValue = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(),
914 VA.getLocVT(), Glue);
915 Chain = RetValue.getValue(1);
916 Glue = RetValue.getValue(2);
918 // Convert the value of the return register into the value that's
920 InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, RetValue));
927 SystemZTargetLowering::LowerReturn(SDValue Chain,
928 CallingConv::ID CallConv, bool IsVarArg,
929 const SmallVectorImpl<ISD::OutputArg> &Outs,
930 const SmallVectorImpl<SDValue> &OutVals,
931 SDLoc DL, SelectionDAG &DAG) const {
932 MachineFunction &MF = DAG.getMachineFunction();
934 // Assign locations to each returned value.
935 SmallVector<CCValAssign, 16> RetLocs;
936 CCState RetCCInfo(CallConv, IsVarArg, MF, TM, RetLocs, *DAG.getContext());
937 RetCCInfo.AnalyzeReturn(Outs, RetCC_SystemZ);
939 // Quick exit for void returns
941 return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, Chain);
943 // Copy the result values into the output registers.
945 SmallVector<SDValue, 4> RetOps;
946 RetOps.push_back(Chain);
947 for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
948 CCValAssign &VA = RetLocs[I];
949 SDValue RetValue = OutVals[I];
951 // Make the return register live on exit.
952 assert(VA.isRegLoc() && "Can only return in registers!");
954 // Promote the value as required.
955 RetValue = convertValVTToLocVT(DAG, DL, VA, RetValue);
957 // Chain and glue the copies together.
958 unsigned Reg = VA.getLocReg();
959 Chain = DAG.getCopyToReg(Chain, DL, Reg, RetValue, Glue);
960 Glue = Chain.getValue(1);
961 RetOps.push_back(DAG.getRegister(Reg, VA.getLocVT()));
964 // Update chain and glue.
967 RetOps.push_back(Glue);
969 return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other,
970 RetOps.data(), RetOps.size());
973 // CC is a comparison that will be implemented using an integer or
974 // floating-point comparison. Return the condition code mask for
975 // a branch on true. In the integer case, CCMASK_CMP_UO is set for
976 // unsigned comparisons and clear for signed ones. In the floating-point
977 // case, CCMASK_CMP_UO has its normal mask meaning (unordered).
978 static unsigned CCMaskForCondCode(ISD::CondCode CC) {
980 case ISD::SET##X: return SystemZ::CCMASK_CMP_##X; \
981 case ISD::SETO##X: return SystemZ::CCMASK_CMP_##X; \
982 case ISD::SETU##X: return SystemZ::CCMASK_CMP_UO | SystemZ::CCMASK_CMP_##X
986 llvm_unreachable("Invalid integer condition!");
995 case ISD::SETO: return SystemZ::CCMASK_CMP_O;
996 case ISD::SETUO: return SystemZ::CCMASK_CMP_UO;
1001 // Return a sequence for getting a 1 from an IPM result when CC has a
1002 // value in CCMask and a 0 when CC has a value in CCValid & ~CCMask.
1003 // The handling of CC values outside CCValid doesn't matter.
1004 static IPMConversion getIPMConversion(unsigned CCValid, unsigned CCMask) {
1005 // Deal with cases where the result can be taken directly from a bit
1006 // of the IPM result.
1007 if (CCMask == (CCValid & (SystemZ::CCMASK_1 | SystemZ::CCMASK_3)))
1008 return IPMConversion(0, 0, SystemZ::IPM_CC);
1009 if (CCMask == (CCValid & (SystemZ::CCMASK_2 | SystemZ::CCMASK_3)))
1010 return IPMConversion(0, 0, SystemZ::IPM_CC + 1);
1012 // Deal with cases where we can add a value to force the sign bit
1013 // to contain the right value. Putting the bit in 31 means we can
1014 // use SRL rather than RISBG(L), and also makes it easier to get a
1015 // 0/-1 value, so it has priority over the other tests below.
1017 // These sequences rely on the fact that the upper two bits of the
1018 // IPM result are zero.
1019 uint64_t TopBit = uint64_t(1) << 31;
1020 if (CCMask == (CCValid & SystemZ::CCMASK_0))
1021 return IPMConversion(0, -(1 << SystemZ::IPM_CC), 31);
1022 if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_1)))
1023 return IPMConversion(0, -(2 << SystemZ::IPM_CC), 31);
1024 if (CCMask == (CCValid & (SystemZ::CCMASK_0
1026 | SystemZ::CCMASK_2)))
1027 return IPMConversion(0, -(3 << SystemZ::IPM_CC), 31);
1028 if (CCMask == (CCValid & SystemZ::CCMASK_3))
1029 return IPMConversion(0, TopBit - (3 << SystemZ::IPM_CC), 31);
1030 if (CCMask == (CCValid & (SystemZ::CCMASK_1
1032 | SystemZ::CCMASK_3)))
1033 return IPMConversion(0, TopBit - (1 << SystemZ::IPM_CC), 31);
1035 // Next try inverting the value and testing a bit. 0/1 could be
1036 // handled this way too, but we dealt with that case above.
1037 if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_2)))
1038 return IPMConversion(-1, 0, SystemZ::IPM_CC);
1040 // Handle cases where adding a value forces a non-sign bit to contain
1042 if (CCMask == (CCValid & (SystemZ::CCMASK_1 | SystemZ::CCMASK_2)))
1043 return IPMConversion(0, 1 << SystemZ::IPM_CC, SystemZ::IPM_CC + 1);
1044 if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_3)))
1045 return IPMConversion(0, -(1 << SystemZ::IPM_CC), SystemZ::IPM_CC + 1);
1047 // The remaing cases are 1, 2, 0/1/3 and 0/2/3. All these are
1048 // can be done by inverting the low CC bit and applying one of the
1049 // sign-based extractions above.
1050 if (CCMask == (CCValid & SystemZ::CCMASK_1))
1051 return IPMConversion(1 << SystemZ::IPM_CC, -(1 << SystemZ::IPM_CC), 31);
1052 if (CCMask == (CCValid & SystemZ::CCMASK_2))
1053 return IPMConversion(1 << SystemZ::IPM_CC,
1054 TopBit - (3 << SystemZ::IPM_CC), 31);
1055 if (CCMask == (CCValid & (SystemZ::CCMASK_0
1057 | SystemZ::CCMASK_3)))
1058 return IPMConversion(1 << SystemZ::IPM_CC, -(3 << SystemZ::IPM_CC), 31);
1059 if (CCMask == (CCValid & (SystemZ::CCMASK_0
1061 | SystemZ::CCMASK_3)))
1062 return IPMConversion(1 << SystemZ::IPM_CC,
1063 TopBit - (1 << SystemZ::IPM_CC), 31);
1065 llvm_unreachable("Unexpected CC combination");
1068 // If a comparison described by IsUnsigned, CCMask, CmpOp0 and CmpOp1
1069 // can be converted to a comparison against zero, adjust the operands
1071 static void adjustZeroCmp(SelectionDAG &DAG, bool &IsUnsigned,
1072 SDValue &CmpOp0, SDValue &CmpOp1,
1077 ConstantSDNode *ConstOp1 = dyn_cast<ConstantSDNode>(CmpOp1.getNode());
1081 int64_t Value = ConstOp1->getSExtValue();
1082 if ((Value == -1 && CCMask == SystemZ::CCMASK_CMP_GT) ||
1083 (Value == -1 && CCMask == SystemZ::CCMASK_CMP_LE) ||
1084 (Value == 1 && CCMask == SystemZ::CCMASK_CMP_LT) ||
1085 (Value == 1 && CCMask == SystemZ::CCMASK_CMP_GE)) {
1086 CCMask ^= SystemZ::CCMASK_CMP_EQ;
1087 CmpOp1 = DAG.getConstant(0, CmpOp1.getValueType());
1091 // If a comparison described by IsUnsigned, CCMask, CmpOp0 and CmpOp1
1092 // is suitable for CLI(Y), CHHSI or CLHHSI, adjust the operands as necessary.
1093 static void adjustSubwordCmp(SelectionDAG &DAG, bool &IsUnsigned,
1094 SDValue &CmpOp0, SDValue &CmpOp1,
1096 // For us to make any changes, it must a comparison between a single-use
1097 // load and a constant.
1098 if (!CmpOp0.hasOneUse() ||
1099 CmpOp0.getOpcode() != ISD::LOAD ||
1100 CmpOp1.getOpcode() != ISD::Constant)
1103 // We must have an 8- or 16-bit load.
1104 LoadSDNode *Load = cast<LoadSDNode>(CmpOp0);
1105 unsigned NumBits = Load->getMemoryVT().getStoreSizeInBits();
1106 if (NumBits != 8 && NumBits != 16)
1109 // The load must be an extending one and the constant must be within the
1110 // range of the unextended value.
1111 ConstantSDNode *Constant = cast<ConstantSDNode>(CmpOp1);
1112 uint64_t Value = Constant->getZExtValue();
1113 uint64_t Mask = (1 << NumBits) - 1;
1114 if (Load->getExtensionType() == ISD::SEXTLOAD) {
1115 int64_t SignedValue = Constant->getSExtValue();
1116 if (uint64_t(SignedValue) + (1ULL << (NumBits - 1)) > Mask)
1118 // Unsigned comparison between two sign-extended values is equivalent
1119 // to unsigned comparison between two zero-extended values.
1122 else if (CCMask == SystemZ::CCMASK_CMP_EQ ||
1123 CCMask == SystemZ::CCMASK_CMP_NE)
1124 // Any choice of IsUnsigned is OK for equality comparisons.
1125 // We could use either CHHSI or CLHHSI for 16-bit comparisons,
1126 // but since we use CLHHSI for zero extensions, it seems better
1127 // to be consistent and do the same here.
1128 Value &= Mask, IsUnsigned = true;
1129 else if (NumBits == 8) {
1130 // Try to treat the comparison as unsigned, so that we can use CLI.
1131 // Adjust CCMask and Value as necessary.
1132 if (Value == 0 && CCMask == SystemZ::CCMASK_CMP_LT)
1133 // Test whether the high bit of the byte is set.
1134 Value = 127, CCMask = SystemZ::CCMASK_CMP_GT, IsUnsigned = true;
1135 else if (Value == 0 && CCMask == SystemZ::CCMASK_CMP_GE)
1136 // Test whether the high bit of the byte is clear.
1137 Value = 128, CCMask = SystemZ::CCMASK_CMP_LT, IsUnsigned = true;
1139 // No instruction exists for this combination.
1142 } else if (Load->getExtensionType() == ISD::ZEXTLOAD) {
1145 // Signed comparison between two zero-extended values is equivalent
1146 // to unsigned comparison.
1151 // Make sure that the first operand is an i32 of the right extension type.
1152 ISD::LoadExtType ExtType = IsUnsigned ? ISD::ZEXTLOAD : ISD::SEXTLOAD;
1153 if (CmpOp0.getValueType() != MVT::i32 ||
1154 Load->getExtensionType() != ExtType)
1155 CmpOp0 = DAG.getExtLoad(ExtType, SDLoc(Load), MVT::i32,
1156 Load->getChain(), Load->getBasePtr(),
1157 Load->getPointerInfo(), Load->getMemoryVT(),
1158 Load->isVolatile(), Load->isNonTemporal(),
1159 Load->getAlignment());
1161 // Make sure that the second operand is an i32 with the right value.
1162 if (CmpOp1.getValueType() != MVT::i32 ||
1163 Value != Constant->getZExtValue())
1164 CmpOp1 = DAG.getConstant(Value, MVT::i32);
1167 // Return true if Op is either an unextended load, or a load suitable
1168 // for integer register-memory comparisons of type ICmpType.
1169 static bool isNaturalMemoryOperand(SDValue Op, unsigned ICmpType) {
1170 LoadSDNode *Load = dyn_cast<LoadSDNode>(Op.getNode());
1172 // There are no instructions to compare a register with a memory byte.
1173 if (Load->getMemoryVT() == MVT::i8)
1175 // Otherwise decide on extension type.
1176 switch (Load->getExtensionType()) {
1177 case ISD::NON_EXTLOAD:
1180 return ICmpType != SystemZICMP::UnsignedOnly;
1182 return ICmpType != SystemZICMP::SignedOnly;
1190 // Return true if it is better to swap comparison operands Op0 and Op1.
1191 // ICmpType is the type of an integer comparison.
1192 static bool shouldSwapCmpOperands(SDValue Op0, SDValue Op1,
1193 unsigned ICmpType) {
1194 // Leave f128 comparisons alone, since they have no memory forms.
1195 if (Op0.getValueType() == MVT::f128)
1198 // Always keep a floating-point constant second, since comparisons with
1199 // zero can use LOAD TEST and comparisons with other constants make a
1200 // natural memory operand.
1201 if (isa<ConstantFPSDNode>(Op1))
1204 // Never swap comparisons with zero since there are many ways to optimize
1206 ConstantSDNode *COp1 = dyn_cast<ConstantSDNode>(Op1);
1207 if (COp1 && COp1->getZExtValue() == 0)
1210 // Look for cases where Cmp0 is a single-use load and Cmp1 isn't.
1211 // In that case we generally prefer the memory to be second.
1212 if ((isNaturalMemoryOperand(Op0, ICmpType) && Op0.hasOneUse()) &&
1213 !(isNaturalMemoryOperand(Op1, ICmpType) && Op1.hasOneUse())) {
1214 // The only exceptions are when the second operand is a constant and
1215 // we can use things like CHHSI.
1218 // The unsigned memory-immediate instructions can handle 16-bit
1219 // unsigned integers.
1220 if (ICmpType != SystemZICMP::SignedOnly &&
1221 isUInt<16>(COp1->getZExtValue()))
1223 // The signed memory-immediate instructions can handle 16-bit
1225 if (ICmpType != SystemZICMP::UnsignedOnly &&
1226 isInt<16>(COp1->getSExtValue()))
1233 // Return true if shift operation N has an in-range constant shift value.
1234 // Store it in ShiftVal if so.
1235 static bool isSimpleShift(SDValue N, unsigned &ShiftVal) {
1236 ConstantSDNode *Shift = dyn_cast<ConstantSDNode>(N.getOperand(1));
1240 uint64_t Amount = Shift->getZExtValue();
1241 if (Amount >= N.getValueType().getSizeInBits())
1248 // Check whether an AND with Mask is suitable for a TEST UNDER MASK
1249 // instruction and whether the CC value is descriptive enough to handle
1250 // a comparison of type Opcode between the AND result and CmpVal.
1251 // CCMask says which comparison result is being tested and BitSize is
1252 // the number of bits in the operands. If TEST UNDER MASK can be used,
1253 // return the corresponding CC mask, otherwise return 0.
1254 static unsigned getTestUnderMaskCond(unsigned BitSize, unsigned CCMask,
1255 uint64_t Mask, uint64_t CmpVal,
1256 unsigned ICmpType) {
1257 assert(Mask != 0 && "ANDs with zero should have been removed by now");
1259 // Check whether the mask is suitable for TMHH, TMHL, TMLH or TMLL.
1260 if (!SystemZ::isImmLL(Mask) && !SystemZ::isImmLH(Mask) &&
1261 !SystemZ::isImmHL(Mask) && !SystemZ::isImmHH(Mask))
1264 // Work out the masks for the lowest and highest bits.
1265 unsigned HighShift = 63 - countLeadingZeros(Mask);
1266 uint64_t High = uint64_t(1) << HighShift;
1267 uint64_t Low = uint64_t(1) << countTrailingZeros(Mask);
1269 // Signed ordered comparisons are effectively unsigned if the sign
1271 bool EffectivelyUnsigned = (ICmpType != SystemZICMP::SignedOnly);
1273 // Check for equality comparisons with 0, or the equivalent.
1275 if (CCMask == SystemZ::CCMASK_CMP_EQ)
1276 return SystemZ::CCMASK_TM_ALL_0;
1277 if (CCMask == SystemZ::CCMASK_CMP_NE)
1278 return SystemZ::CCMASK_TM_SOME_1;
1280 if (EffectivelyUnsigned && CmpVal <= Low) {
1281 if (CCMask == SystemZ::CCMASK_CMP_LT)
1282 return SystemZ::CCMASK_TM_ALL_0;
1283 if (CCMask == SystemZ::CCMASK_CMP_GE)
1284 return SystemZ::CCMASK_TM_SOME_1;
1286 if (EffectivelyUnsigned && CmpVal < Low) {
1287 if (CCMask == SystemZ::CCMASK_CMP_LE)
1288 return SystemZ::CCMASK_TM_ALL_0;
1289 if (CCMask == SystemZ::CCMASK_CMP_GT)
1290 return SystemZ::CCMASK_TM_SOME_1;
1293 // Check for equality comparisons with the mask, or the equivalent.
1294 if (CmpVal == Mask) {
1295 if (CCMask == SystemZ::CCMASK_CMP_EQ)
1296 return SystemZ::CCMASK_TM_ALL_1;
1297 if (CCMask == SystemZ::CCMASK_CMP_NE)
1298 return SystemZ::CCMASK_TM_SOME_0;
1300 if (EffectivelyUnsigned && CmpVal >= Mask - Low && CmpVal < Mask) {
1301 if (CCMask == SystemZ::CCMASK_CMP_GT)
1302 return SystemZ::CCMASK_TM_ALL_1;
1303 if (CCMask == SystemZ::CCMASK_CMP_LE)
1304 return SystemZ::CCMASK_TM_SOME_0;
1306 if (EffectivelyUnsigned && CmpVal > Mask - Low && CmpVal <= Mask) {
1307 if (CCMask == SystemZ::CCMASK_CMP_GE)
1308 return SystemZ::CCMASK_TM_ALL_1;
1309 if (CCMask == SystemZ::CCMASK_CMP_LT)
1310 return SystemZ::CCMASK_TM_SOME_0;
1313 // Check for ordered comparisons with the top bit.
1314 if (EffectivelyUnsigned && CmpVal >= Mask - High && CmpVal < High) {
1315 if (CCMask == SystemZ::CCMASK_CMP_LE)
1316 return SystemZ::CCMASK_TM_MSB_0;
1317 if (CCMask == SystemZ::CCMASK_CMP_GT)
1318 return SystemZ::CCMASK_TM_MSB_1;
1320 if (EffectivelyUnsigned && CmpVal > Mask - High && CmpVal <= High) {
1321 if (CCMask == SystemZ::CCMASK_CMP_LT)
1322 return SystemZ::CCMASK_TM_MSB_0;
1323 if (CCMask == SystemZ::CCMASK_CMP_GE)
1324 return SystemZ::CCMASK_TM_MSB_1;
1327 // If there are just two bits, we can do equality checks for Low and High
1329 if (Mask == Low + High) {
1330 if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == Low)
1331 return SystemZ::CCMASK_TM_MIXED_MSB_0;
1332 if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == Low)
1333 return SystemZ::CCMASK_TM_MIXED_MSB_0 ^ SystemZ::CCMASK_ANY;
1334 if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == High)
1335 return SystemZ::CCMASK_TM_MIXED_MSB_1;
1336 if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == High)
1337 return SystemZ::CCMASK_TM_MIXED_MSB_1 ^ SystemZ::CCMASK_ANY;
1340 // Looks like we've exhausted our options.
1344 // See whether the comparison (Opcode CmpOp0, CmpOp1, ICmpType) can be
1345 // implemented as a TEST UNDER MASK instruction when the condition being
1346 // tested is as described by CCValid and CCMask. Update the arguments
1347 // with the TM version if so.
1348 static void adjustForTestUnderMask(SelectionDAG &DAG, unsigned &Opcode,
1349 SDValue &CmpOp0, SDValue &CmpOp1,
1350 unsigned &CCValid, unsigned &CCMask,
1351 unsigned &ICmpType) {
1352 // Check that we have a comparison with a constant.
1353 ConstantSDNode *ConstCmpOp1 = dyn_cast<ConstantSDNode>(CmpOp1);
1356 uint64_t CmpVal = ConstCmpOp1->getZExtValue();
1358 // Check whether the nonconstant input is an AND with a constant mask.
1359 if (CmpOp0.getOpcode() != ISD::AND)
1361 SDValue AndOp0 = CmpOp0.getOperand(0);
1362 SDValue AndOp1 = CmpOp0.getOperand(1);
1363 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(AndOp1.getNode());
1366 uint64_t MaskVal = Mask->getZExtValue();
1368 // Check whether the combination of mask, comparison value and comparison
1369 // type are suitable.
1370 unsigned BitSize = CmpOp0.getValueType().getSizeInBits();
1371 unsigned NewCCMask, ShiftVal;
1372 if (ICmpType != SystemZICMP::SignedOnly &&
1373 AndOp0.getOpcode() == ISD::SHL &&
1374 isSimpleShift(AndOp0, ShiftVal) &&
1375 (NewCCMask = getTestUnderMaskCond(BitSize, CCMask, MaskVal >> ShiftVal,
1377 SystemZICMP::Any))) {
1378 AndOp0 = AndOp0.getOperand(0);
1379 AndOp1 = DAG.getConstant(MaskVal >> ShiftVal, AndOp0.getValueType());
1380 } else if (ICmpType != SystemZICMP::SignedOnly &&
1381 AndOp0.getOpcode() == ISD::SRL &&
1382 isSimpleShift(AndOp0, ShiftVal) &&
1383 (NewCCMask = getTestUnderMaskCond(BitSize, CCMask,
1384 MaskVal << ShiftVal,
1386 SystemZICMP::UnsignedOnly))) {
1387 AndOp0 = AndOp0.getOperand(0);
1388 AndOp1 = DAG.getConstant(MaskVal << ShiftVal, AndOp0.getValueType());
1390 NewCCMask = getTestUnderMaskCond(BitSize, CCMask, MaskVal, CmpVal,
1396 // Go ahead and make the change.
1397 Opcode = SystemZISD::TM;
1400 ICmpType = (bool(NewCCMask & SystemZ::CCMASK_TM_MIXED_MSB_0) !=
1401 bool(NewCCMask & SystemZ::CCMASK_TM_MIXED_MSB_1));
1402 CCValid = SystemZ::CCMASK_TM;
1406 // Return a target node that compares CmpOp0 with CmpOp1 and stores a
1407 // 2-bit result in CC. Set CCValid to the CCMASK_* of all possible
1408 // 2-bit results and CCMask to the subset of those results that are
1409 // associated with Cond.
1410 static SDValue emitCmp(const SystemZTargetMachine &TM, SelectionDAG &DAG,
1411 SDLoc DL, SDValue CmpOp0, SDValue CmpOp1,
1412 ISD::CondCode Cond, unsigned &CCValid,
1414 bool IsUnsigned = false;
1415 CCMask = CCMaskForCondCode(Cond);
1416 unsigned Opcode, ICmpType = 0;
1417 if (CmpOp0.getValueType().isFloatingPoint()) {
1418 CCValid = SystemZ::CCMASK_FCMP;
1419 Opcode = SystemZISD::FCMP;
1421 IsUnsigned = CCMask & SystemZ::CCMASK_CMP_UO;
1422 CCValid = SystemZ::CCMASK_ICMP;
1424 adjustZeroCmp(DAG, IsUnsigned, CmpOp0, CmpOp1, CCMask);
1425 adjustSubwordCmp(DAG, IsUnsigned, CmpOp0, CmpOp1, CCMask);
1426 Opcode = SystemZISD::ICMP;
1427 // Choose the type of comparison. Equality and inequality tests can
1428 // use either signed or unsigned comparisons. The choice also doesn't
1429 // matter if both sign bits are known to be clear. In those cases we
1430 // want to give the main isel code the freedom to choose whichever
1432 if (CCMask == SystemZ::CCMASK_CMP_EQ ||
1433 CCMask == SystemZ::CCMASK_CMP_NE ||
1434 (DAG.SignBitIsZero(CmpOp0) && DAG.SignBitIsZero(CmpOp1)))
1435 ICmpType = SystemZICMP::Any;
1436 else if (IsUnsigned)
1437 ICmpType = SystemZICMP::UnsignedOnly;
1439 ICmpType = SystemZICMP::SignedOnly;
1442 if (shouldSwapCmpOperands(CmpOp0, CmpOp1, ICmpType)) {
1443 std::swap(CmpOp0, CmpOp1);
1444 CCMask = ((CCMask & SystemZ::CCMASK_CMP_EQ) |
1445 (CCMask & SystemZ::CCMASK_CMP_GT ? SystemZ::CCMASK_CMP_LT : 0) |
1446 (CCMask & SystemZ::CCMASK_CMP_LT ? SystemZ::CCMASK_CMP_GT : 0) |
1447 (CCMask & SystemZ::CCMASK_CMP_UO));
1450 adjustForTestUnderMask(DAG, Opcode, CmpOp0, CmpOp1, CCValid, CCMask,
1452 if (Opcode == SystemZISD::ICMP || Opcode == SystemZISD::TM)
1453 return DAG.getNode(Opcode, DL, MVT::Glue, CmpOp0, CmpOp1,
1454 DAG.getConstant(ICmpType, MVT::i32));
1455 return DAG.getNode(Opcode, DL, MVT::Glue, CmpOp0, CmpOp1);
1458 // Implement a 32-bit *MUL_LOHI operation by extending both operands to
1459 // 64 bits. Extend is the extension type to use. Store the high part
1460 // in Hi and the low part in Lo.
1461 static void lowerMUL_LOHI32(SelectionDAG &DAG, SDLoc DL,
1462 unsigned Extend, SDValue Op0, SDValue Op1,
1463 SDValue &Hi, SDValue &Lo) {
1464 Op0 = DAG.getNode(Extend, DL, MVT::i64, Op0);
1465 Op1 = DAG.getNode(Extend, DL, MVT::i64, Op1);
1466 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, Op0, Op1);
1467 Hi = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul, DAG.getConstant(32, MVT::i64));
1468 Hi = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Hi);
1469 Lo = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mul);
1472 // Lower a binary operation that produces two VT results, one in each
1473 // half of a GR128 pair. Op0 and Op1 are the VT operands to the operation,
1474 // Extend extends Op0 to a GR128, and Opcode performs the GR128 operation
1475 // on the extended Op0 and (unextended) Op1. Store the even register result
1476 // in Even and the odd register result in Odd.
1477 static void lowerGR128Binary(SelectionDAG &DAG, SDLoc DL, EVT VT,
1478 unsigned Extend, unsigned Opcode,
1479 SDValue Op0, SDValue Op1,
1480 SDValue &Even, SDValue &Odd) {
1481 SDNode *In128 = DAG.getMachineNode(Extend, DL, MVT::Untyped, Op0);
1482 SDValue Result = DAG.getNode(Opcode, DL, MVT::Untyped,
1483 SDValue(In128, 0), Op1);
1484 bool Is32Bit = is32Bit(VT);
1485 Even = DAG.getTargetExtractSubreg(SystemZ::even128(Is32Bit), DL, VT, Result);
1486 Odd = DAG.getTargetExtractSubreg(SystemZ::odd128(Is32Bit), DL, VT, Result);
1489 SDValue SystemZTargetLowering::lowerSETCC(SDValue Op,
1490 SelectionDAG &DAG) const {
1491 SDValue CmpOp0 = Op.getOperand(0);
1492 SDValue CmpOp1 = Op.getOperand(1);
1493 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1496 unsigned CCValid, CCMask;
1497 SDValue Glue = emitCmp(TM, DAG, DL, CmpOp0, CmpOp1, CC, CCValid, CCMask);
1499 IPMConversion Conversion = getIPMConversion(CCValid, CCMask);
1500 SDValue Result = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, Glue);
1502 if (Conversion.XORValue)
1503 Result = DAG.getNode(ISD::XOR, DL, MVT::i32, Result,
1504 DAG.getConstant(Conversion.XORValue, MVT::i32));
1506 if (Conversion.AddValue)
1507 Result = DAG.getNode(ISD::ADD, DL, MVT::i32, Result,
1508 DAG.getConstant(Conversion.AddValue, MVT::i32));
1510 // The SHR/AND sequence should get optimized to an RISBG.
1511 Result = DAG.getNode(ISD::SRL, DL, MVT::i32, Result,
1512 DAG.getConstant(Conversion.Bit, MVT::i32));
1513 if (Conversion.Bit != 31)
1514 Result = DAG.getNode(ISD::AND, DL, MVT::i32, Result,
1515 DAG.getConstant(1, MVT::i32));
1519 SDValue SystemZTargetLowering::lowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
1520 SDValue Chain = Op.getOperand(0);
1521 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1522 SDValue CmpOp0 = Op.getOperand(2);
1523 SDValue CmpOp1 = Op.getOperand(3);
1524 SDValue Dest = Op.getOperand(4);
1527 unsigned CCValid, CCMask;
1528 SDValue Flags = emitCmp(TM, DAG, DL, CmpOp0, CmpOp1, CC, CCValid, CCMask);
1529 return DAG.getNode(SystemZISD::BR_CCMASK, DL, Op.getValueType(),
1530 Chain, DAG.getConstant(CCValid, MVT::i32),
1531 DAG.getConstant(CCMask, MVT::i32), Dest, Flags);
1534 SDValue SystemZTargetLowering::lowerSELECT_CC(SDValue Op,
1535 SelectionDAG &DAG) const {
1536 SDValue CmpOp0 = Op.getOperand(0);
1537 SDValue CmpOp1 = Op.getOperand(1);
1538 SDValue TrueOp = Op.getOperand(2);
1539 SDValue FalseOp = Op.getOperand(3);
1540 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1543 unsigned CCValid, CCMask;
1544 SDValue Flags = emitCmp(TM, DAG, DL, CmpOp0, CmpOp1, CC, CCValid, CCMask);
1546 SmallVector<SDValue, 5> Ops;
1547 Ops.push_back(TrueOp);
1548 Ops.push_back(FalseOp);
1549 Ops.push_back(DAG.getConstant(CCValid, MVT::i32));
1550 Ops.push_back(DAG.getConstant(CCMask, MVT::i32));
1551 Ops.push_back(Flags);
1553 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1554 return DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VTs, &Ops[0], Ops.size());
1557 SDValue SystemZTargetLowering::lowerGlobalAddress(GlobalAddressSDNode *Node,
1558 SelectionDAG &DAG) const {
1560 const GlobalValue *GV = Node->getGlobal();
1561 int64_t Offset = Node->getOffset();
1562 EVT PtrVT = getPointerTy();
1563 Reloc::Model RM = TM.getRelocationModel();
1564 CodeModel::Model CM = TM.getCodeModel();
1567 if (Subtarget.isPC32DBLSymbol(GV, RM, CM)) {
1568 // Assign anchors at 1<<12 byte boundaries.
1569 uint64_t Anchor = Offset & ~uint64_t(0xfff);
1570 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor);
1571 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1573 // The offset can be folded into the address if it is aligned to a halfword.
1575 if (Offset != 0 && (Offset & 1) == 0) {
1576 SDValue Full = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor + Offset);
1577 Result = DAG.getNode(SystemZISD::PCREL_OFFSET, DL, PtrVT, Full, Result);
1581 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, SystemZII::MO_GOT);
1582 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1583 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
1584 MachinePointerInfo::getGOT(), false, false, false, 0);
1587 // If there was a non-zero offset that we didn't fold, create an explicit
1590 Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result,
1591 DAG.getConstant(Offset, PtrVT));
1596 SDValue SystemZTargetLowering::lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
1597 SelectionDAG &DAG) const {
1599 const GlobalValue *GV = Node->getGlobal();
1600 EVT PtrVT = getPointerTy();
1601 TLSModel::Model model = TM.getTLSModel(GV);
1603 if (model != TLSModel::LocalExec)
1604 llvm_unreachable("only local-exec TLS mode supported");
1606 // The high part of the thread pointer is in access register 0.
1607 SDValue TPHi = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
1608 DAG.getConstant(0, MVT::i32));
1609 TPHi = DAG.getNode(ISD::ANY_EXTEND, DL, PtrVT, TPHi);
1611 // The low part of the thread pointer is in access register 1.
1612 SDValue TPLo = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
1613 DAG.getConstant(1, MVT::i32));
1614 TPLo = DAG.getNode(ISD::ZERO_EXTEND, DL, PtrVT, TPLo);
1616 // Merge them into a single 64-bit address.
1617 SDValue TPHiShifted = DAG.getNode(ISD::SHL, DL, PtrVT, TPHi,
1618 DAG.getConstant(32, PtrVT));
1619 SDValue TP = DAG.getNode(ISD::OR, DL, PtrVT, TPHiShifted, TPLo);
1621 // Get the offset of GA from the thread pointer.
1622 SystemZConstantPoolValue *CPV =
1623 SystemZConstantPoolValue::Create(GV, SystemZCP::NTPOFF);
1625 // Force the offset into the constant pool and load it from there.
1626 SDValue CPAddr = DAG.getConstantPool(CPV, PtrVT, 8);
1627 SDValue Offset = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(),
1628 CPAddr, MachinePointerInfo::getConstantPool(),
1629 false, false, false, 0);
1631 // Add the base and offset together.
1632 return DAG.getNode(ISD::ADD, DL, PtrVT, TP, Offset);
1635 SDValue SystemZTargetLowering::lowerBlockAddress(BlockAddressSDNode *Node,
1636 SelectionDAG &DAG) const {
1638 const BlockAddress *BA = Node->getBlockAddress();
1639 int64_t Offset = Node->getOffset();
1640 EVT PtrVT = getPointerTy();
1642 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset);
1643 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1647 SDValue SystemZTargetLowering::lowerJumpTable(JumpTableSDNode *JT,
1648 SelectionDAG &DAG) const {
1650 EVT PtrVT = getPointerTy();
1651 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1653 // Use LARL to load the address of the table.
1654 return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1657 SDValue SystemZTargetLowering::lowerConstantPool(ConstantPoolSDNode *CP,
1658 SelectionDAG &DAG) const {
1660 EVT PtrVT = getPointerTy();
1663 if (CP->isMachineConstantPoolEntry())
1664 Result = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1665 CP->getAlignment());
1667 Result = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1668 CP->getAlignment(), CP->getOffset());
1670 // Use LARL to load the address of the constant pool entry.
1671 return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1674 SDValue SystemZTargetLowering::lowerBITCAST(SDValue Op,
1675 SelectionDAG &DAG) const {
1677 SDValue In = Op.getOperand(0);
1678 EVT InVT = In.getValueType();
1679 EVT ResVT = Op.getValueType();
1681 if (InVT == MVT::i32 && ResVT == MVT::f32) {
1683 if (Subtarget.hasHighWord()) {
1684 SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL,
1686 In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h32, DL,
1687 MVT::i64, SDValue(U64, 0), In);
1689 In64 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, In);
1690 In64 = DAG.getNode(ISD::SHL, DL, MVT::i64, In64,
1691 DAG.getConstant(32, MVT::i64));
1693 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::f64, In64);
1694 return DAG.getTargetExtractSubreg(SystemZ::subreg_h32,
1695 DL, MVT::f32, Out64);
1697 if (InVT == MVT::f32 && ResVT == MVT::i32) {
1698 SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::f64);
1699 SDValue In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h32, DL,
1700 MVT::f64, SDValue(U64, 0), In);
1701 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::i64, In64);
1702 if (Subtarget.hasHighWord())
1703 return DAG.getTargetExtractSubreg(SystemZ::subreg_h32, DL,
1705 SDValue Shift = DAG.getNode(ISD::SRL, DL, MVT::i64, Out64,
1706 DAG.getConstant(32, MVT::i64));
1707 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Shift);
1709 llvm_unreachable("Unexpected bitcast combination");
1712 SDValue SystemZTargetLowering::lowerVASTART(SDValue Op,
1713 SelectionDAG &DAG) const {
1714 MachineFunction &MF = DAG.getMachineFunction();
1715 SystemZMachineFunctionInfo *FuncInfo =
1716 MF.getInfo<SystemZMachineFunctionInfo>();
1717 EVT PtrVT = getPointerTy();
1719 SDValue Chain = Op.getOperand(0);
1720 SDValue Addr = Op.getOperand(1);
1721 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1724 // The initial values of each field.
1725 const unsigned NumFields = 4;
1726 SDValue Fields[NumFields] = {
1727 DAG.getConstant(FuncInfo->getVarArgsFirstGPR(), PtrVT),
1728 DAG.getConstant(FuncInfo->getVarArgsFirstFPR(), PtrVT),
1729 DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT),
1730 DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT)
1733 // Store each field into its respective slot.
1734 SDValue MemOps[NumFields];
1735 unsigned Offset = 0;
1736 for (unsigned I = 0; I < NumFields; ++I) {
1737 SDValue FieldAddr = Addr;
1739 FieldAddr = DAG.getNode(ISD::ADD, DL, PtrVT, FieldAddr,
1740 DAG.getIntPtrConstant(Offset));
1741 MemOps[I] = DAG.getStore(Chain, DL, Fields[I], FieldAddr,
1742 MachinePointerInfo(SV, Offset),
1746 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps, NumFields);
1749 SDValue SystemZTargetLowering::lowerVACOPY(SDValue Op,
1750 SelectionDAG &DAG) const {
1751 SDValue Chain = Op.getOperand(0);
1752 SDValue DstPtr = Op.getOperand(1);
1753 SDValue SrcPtr = Op.getOperand(2);
1754 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
1755 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
1758 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, DAG.getIntPtrConstant(32),
1759 /*Align*/8, /*isVolatile*/false, /*AlwaysInline*/false,
1760 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
1763 SDValue SystemZTargetLowering::
1764 lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
1765 SDValue Chain = Op.getOperand(0);
1766 SDValue Size = Op.getOperand(1);
1769 unsigned SPReg = getStackPointerRegisterToSaveRestore();
1771 // Get a reference to the stack pointer.
1772 SDValue OldSP = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i64);
1774 // Get the new stack pointer value.
1775 SDValue NewSP = DAG.getNode(ISD::SUB, DL, MVT::i64, OldSP, Size);
1777 // Copy the new stack pointer back.
1778 Chain = DAG.getCopyToReg(Chain, DL, SPReg, NewSP);
1780 // The allocated data lives above the 160 bytes allocated for the standard
1781 // frame, plus any outgoing stack arguments. We don't know how much that
1782 // amounts to yet, so emit a special ADJDYNALLOC placeholder.
1783 SDValue ArgAdjust = DAG.getNode(SystemZISD::ADJDYNALLOC, DL, MVT::i64);
1784 SDValue Result = DAG.getNode(ISD::ADD, DL, MVT::i64, NewSP, ArgAdjust);
1786 SDValue Ops[2] = { Result, Chain };
1787 return DAG.getMergeValues(Ops, 2, DL);
1790 SDValue SystemZTargetLowering::lowerSMUL_LOHI(SDValue Op,
1791 SelectionDAG &DAG) const {
1792 EVT VT = Op.getValueType();
1796 // Just do a normal 64-bit multiplication and extract the results.
1797 // We define this so that it can be used for constant division.
1798 lowerMUL_LOHI32(DAG, DL, ISD::SIGN_EXTEND, Op.getOperand(0),
1799 Op.getOperand(1), Ops[1], Ops[0]);
1801 // Do a full 128-bit multiplication based on UMUL_LOHI64:
1803 // (ll * rl) + ((lh * rl) << 64) + ((ll * rh) << 64)
1805 // but using the fact that the upper halves are either all zeros
1808 // (ll * rl) - ((lh & rl) << 64) - ((ll & rh) << 64)
1810 // and grouping the right terms together since they are quicker than the
1813 // (ll * rl) - (((lh & rl) + (ll & rh)) << 64)
1814 SDValue C63 = DAG.getConstant(63, MVT::i64);
1815 SDValue LL = Op.getOperand(0);
1816 SDValue RL = Op.getOperand(1);
1817 SDValue LH = DAG.getNode(ISD::SRA, DL, VT, LL, C63);
1818 SDValue RH = DAG.getNode(ISD::SRA, DL, VT, RL, C63);
1819 // UMUL_LOHI64 returns the low result in the odd register and the high
1820 // result in the even register. SMUL_LOHI is defined to return the
1821 // low half first, so the results are in reverse order.
1822 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
1823 LL, RL, Ops[1], Ops[0]);
1824 SDValue NegLLTimesRH = DAG.getNode(ISD::AND, DL, VT, LL, RH);
1825 SDValue NegLHTimesRL = DAG.getNode(ISD::AND, DL, VT, LH, RL);
1826 SDValue NegSum = DAG.getNode(ISD::ADD, DL, VT, NegLLTimesRH, NegLHTimesRL);
1827 Ops[1] = DAG.getNode(ISD::SUB, DL, VT, Ops[1], NegSum);
1829 return DAG.getMergeValues(Ops, 2, DL);
1832 SDValue SystemZTargetLowering::lowerUMUL_LOHI(SDValue Op,
1833 SelectionDAG &DAG) const {
1834 EVT VT = Op.getValueType();
1838 // Just do a normal 64-bit multiplication and extract the results.
1839 // We define this so that it can be used for constant division.
1840 lowerMUL_LOHI32(DAG, DL, ISD::ZERO_EXTEND, Op.getOperand(0),
1841 Op.getOperand(1), Ops[1], Ops[0]);
1843 // UMUL_LOHI64 returns the low result in the odd register and the high
1844 // result in the even register. UMUL_LOHI is defined to return the
1845 // low half first, so the results are in reverse order.
1846 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
1847 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
1848 return DAG.getMergeValues(Ops, 2, DL);
1851 SDValue SystemZTargetLowering::lowerSDIVREM(SDValue Op,
1852 SelectionDAG &DAG) const {
1853 SDValue Op0 = Op.getOperand(0);
1854 SDValue Op1 = Op.getOperand(1);
1855 EVT VT = Op.getValueType();
1859 // We use DSGF for 32-bit division.
1861 Op0 = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op0);
1862 Opcode = SystemZISD::SDIVREM32;
1863 } else if (DAG.ComputeNumSignBits(Op1) > 32) {
1864 Op1 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op1);
1865 Opcode = SystemZISD::SDIVREM32;
1867 Opcode = SystemZISD::SDIVREM64;
1869 // DSG(F) takes a 64-bit dividend, so the even register in the GR128
1870 // input is "don't care". The instruction returns the remainder in
1871 // the even register and the quotient in the odd register.
1873 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, Opcode,
1874 Op0, Op1, Ops[1], Ops[0]);
1875 return DAG.getMergeValues(Ops, 2, DL);
1878 SDValue SystemZTargetLowering::lowerUDIVREM(SDValue Op,
1879 SelectionDAG &DAG) const {
1880 EVT VT = Op.getValueType();
1883 // DL(G) uses a double-width dividend, so we need to clear the even
1884 // register in the GR128 input. The instruction returns the remainder
1885 // in the even register and the quotient in the odd register.
1888 lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_32, SystemZISD::UDIVREM32,
1889 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
1891 lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_64, SystemZISD::UDIVREM64,
1892 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
1893 return DAG.getMergeValues(Ops, 2, DL);
1896 SDValue SystemZTargetLowering::lowerOR(SDValue Op, SelectionDAG &DAG) const {
1897 assert(Op.getValueType() == MVT::i64 && "Should be 64-bit operation");
1899 // Get the known-zero masks for each operand.
1900 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1) };
1901 APInt KnownZero[2], KnownOne[2];
1902 DAG.ComputeMaskedBits(Ops[0], KnownZero[0], KnownOne[0]);
1903 DAG.ComputeMaskedBits(Ops[1], KnownZero[1], KnownOne[1]);
1905 // See if the upper 32 bits of one operand and the lower 32 bits of the
1906 // other are known zero. They are the low and high operands respectively.
1907 uint64_t Masks[] = { KnownZero[0].getZExtValue(),
1908 KnownZero[1].getZExtValue() };
1910 if ((Masks[0] >> 32) == 0xffffffff && uint32_t(Masks[1]) == 0xffffffff)
1912 else if ((Masks[1] >> 32) == 0xffffffff && uint32_t(Masks[0]) == 0xffffffff)
1917 SDValue LowOp = Ops[Low];
1918 SDValue HighOp = Ops[High];
1920 // If the high part is a constant, we're better off using IILH.
1921 if (HighOp.getOpcode() == ISD::Constant)
1924 // If the low part is a constant that is outside the range of LHI,
1925 // then we're better off using IILF.
1926 if (LowOp.getOpcode() == ISD::Constant) {
1927 int64_t Value = int32_t(cast<ConstantSDNode>(LowOp)->getZExtValue());
1928 if (!isInt<16>(Value))
1932 // Check whether the high part is an AND that doesn't change the
1933 // high 32 bits and just masks out low bits. We can skip it if so.
1934 if (HighOp.getOpcode() == ISD::AND &&
1935 HighOp.getOperand(1).getOpcode() == ISD::Constant) {
1936 ConstantSDNode *MaskNode = cast<ConstantSDNode>(HighOp.getOperand(1));
1937 uint64_t Mask = MaskNode->getZExtValue() | Masks[High];
1938 if ((Mask >> 32) == 0xffffffff)
1939 HighOp = HighOp.getOperand(0);
1942 // Take advantage of the fact that all GR32 operations only change the
1943 // low 32 bits by truncating Low to an i32 and inserting it directly
1944 // using a subreg. The interesting cases are those where the truncation
1947 SDValue Low32 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, LowOp);
1948 return DAG.getTargetInsertSubreg(SystemZ::subreg_l32, DL,
1949 MVT::i64, HighOp, Low32);
1952 // Op is an 8-, 16-bit or 32-bit ATOMIC_LOAD_* operation. Lower the first
1953 // two into the fullword ATOMIC_LOADW_* operation given by Opcode.
1954 SDValue SystemZTargetLowering::lowerATOMIC_LOAD(SDValue Op,
1956 unsigned Opcode) const {
1957 AtomicSDNode *Node = cast<AtomicSDNode>(Op.getNode());
1959 // 32-bit operations need no code outside the main loop.
1960 EVT NarrowVT = Node->getMemoryVT();
1961 EVT WideVT = MVT::i32;
1962 if (NarrowVT == WideVT)
1965 int64_t BitSize = NarrowVT.getSizeInBits();
1966 SDValue ChainIn = Node->getChain();
1967 SDValue Addr = Node->getBasePtr();
1968 SDValue Src2 = Node->getVal();
1969 MachineMemOperand *MMO = Node->getMemOperand();
1971 EVT PtrVT = Addr.getValueType();
1973 // Convert atomic subtracts of constants into additions.
1974 if (Opcode == SystemZISD::ATOMIC_LOADW_SUB)
1975 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Src2)) {
1976 Opcode = SystemZISD::ATOMIC_LOADW_ADD;
1977 Src2 = DAG.getConstant(-Const->getSExtValue(), Src2.getValueType());
1980 // Get the address of the containing word.
1981 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
1982 DAG.getConstant(-4, PtrVT));
1984 // Get the number of bits that the word must be rotated left in order
1985 // to bring the field to the top bits of a GR32.
1986 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
1987 DAG.getConstant(3, PtrVT));
1988 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
1990 // Get the complementing shift amount, for rotating a field in the top
1991 // bits back to its proper position.
1992 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
1993 DAG.getConstant(0, WideVT), BitShift);
1995 // Extend the source operand to 32 bits and prepare it for the inner loop.
1996 // ATOMIC_SWAPW uses RISBG to rotate the field left, but all other
1997 // operations require the source to be shifted in advance. (This shift
1998 // can be folded if the source is constant.) For AND and NAND, the lower
1999 // bits must be set, while for other opcodes they should be left clear.
2000 if (Opcode != SystemZISD::ATOMIC_SWAPW)
2001 Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2,
2002 DAG.getConstant(32 - BitSize, WideVT));
2003 if (Opcode == SystemZISD::ATOMIC_LOADW_AND ||
2004 Opcode == SystemZISD::ATOMIC_LOADW_NAND)
2005 Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2,
2006 DAG.getConstant(uint32_t(-1) >> BitSize, WideVT));
2008 // Construct the ATOMIC_LOADW_* node.
2009 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
2010 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift,
2011 DAG.getConstant(BitSize, WideVT) };
2012 SDValue AtomicOp = DAG.getMemIntrinsicNode(Opcode, DL, VTList, Ops,
2013 array_lengthof(Ops),
2016 // Rotate the result of the final CS so that the field is in the lower
2017 // bits of a GR32, then truncate it.
2018 SDValue ResultShift = DAG.getNode(ISD::ADD, DL, WideVT, BitShift,
2019 DAG.getConstant(BitSize, WideVT));
2020 SDValue Result = DAG.getNode(ISD::ROTL, DL, WideVT, AtomicOp, ResultShift);
2022 SDValue RetOps[2] = { Result, AtomicOp.getValue(1) };
2023 return DAG.getMergeValues(RetOps, 2, DL);
2026 // Node is an 8- or 16-bit ATOMIC_CMP_SWAP operation. Lower the first two
2027 // into a fullword ATOMIC_CMP_SWAPW operation.
2028 SDValue SystemZTargetLowering::lowerATOMIC_CMP_SWAP(SDValue Op,
2029 SelectionDAG &DAG) const {
2030 AtomicSDNode *Node = cast<AtomicSDNode>(Op.getNode());
2032 // We have native support for 32-bit compare and swap.
2033 EVT NarrowVT = Node->getMemoryVT();
2034 EVT WideVT = MVT::i32;
2035 if (NarrowVT == WideVT)
2038 int64_t BitSize = NarrowVT.getSizeInBits();
2039 SDValue ChainIn = Node->getOperand(0);
2040 SDValue Addr = Node->getOperand(1);
2041 SDValue CmpVal = Node->getOperand(2);
2042 SDValue SwapVal = Node->getOperand(3);
2043 MachineMemOperand *MMO = Node->getMemOperand();
2045 EVT PtrVT = Addr.getValueType();
2047 // Get the address of the containing word.
2048 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
2049 DAG.getConstant(-4, PtrVT));
2051 // Get the number of bits that the word must be rotated left in order
2052 // to bring the field to the top bits of a GR32.
2053 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
2054 DAG.getConstant(3, PtrVT));
2055 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
2057 // Get the complementing shift amount, for rotating a field in the top
2058 // bits back to its proper position.
2059 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
2060 DAG.getConstant(0, WideVT), BitShift);
2062 // Construct the ATOMIC_CMP_SWAPW node.
2063 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
2064 SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift,
2065 NegBitShift, DAG.getConstant(BitSize, WideVT) };
2066 SDValue AtomicOp = DAG.getMemIntrinsicNode(SystemZISD::ATOMIC_CMP_SWAPW, DL,
2067 VTList, Ops, array_lengthof(Ops),
2072 SDValue SystemZTargetLowering::lowerSTACKSAVE(SDValue Op,
2073 SelectionDAG &DAG) const {
2074 MachineFunction &MF = DAG.getMachineFunction();
2075 MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
2076 return DAG.getCopyFromReg(Op.getOperand(0), SDLoc(Op),
2077 SystemZ::R15D, Op.getValueType());
2080 SDValue SystemZTargetLowering::lowerSTACKRESTORE(SDValue Op,
2081 SelectionDAG &DAG) const {
2082 MachineFunction &MF = DAG.getMachineFunction();
2083 MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
2084 return DAG.getCopyToReg(Op.getOperand(0), SDLoc(Op),
2085 SystemZ::R15D, Op.getOperand(1));
2088 SDValue SystemZTargetLowering::lowerPREFETCH(SDValue Op,
2089 SelectionDAG &DAG) const {
2090 bool IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
2092 // Just preserve the chain.
2093 return Op.getOperand(0);
2095 bool IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
2096 unsigned Code = IsWrite ? SystemZ::PFD_WRITE : SystemZ::PFD_READ;
2097 MemIntrinsicSDNode *Node = cast<MemIntrinsicSDNode>(Op.getNode());
2100 DAG.getConstant(Code, MVT::i32),
2103 return DAG.getMemIntrinsicNode(SystemZISD::PREFETCH, SDLoc(Op),
2104 Node->getVTList(), Ops, array_lengthof(Ops),
2105 Node->getMemoryVT(), Node->getMemOperand());
2108 SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
2109 SelectionDAG &DAG) const {
2110 switch (Op.getOpcode()) {
2112 return lowerBR_CC(Op, DAG);
2113 case ISD::SELECT_CC:
2114 return lowerSELECT_CC(Op, DAG);
2116 return lowerSETCC(Op, DAG);
2117 case ISD::GlobalAddress:
2118 return lowerGlobalAddress(cast<GlobalAddressSDNode>(Op), DAG);
2119 case ISD::GlobalTLSAddress:
2120 return lowerGlobalTLSAddress(cast<GlobalAddressSDNode>(Op), DAG);
2121 case ISD::BlockAddress:
2122 return lowerBlockAddress(cast<BlockAddressSDNode>(Op), DAG);
2123 case ISD::JumpTable:
2124 return lowerJumpTable(cast<JumpTableSDNode>(Op), DAG);
2125 case ISD::ConstantPool:
2126 return lowerConstantPool(cast<ConstantPoolSDNode>(Op), DAG);
2128 return lowerBITCAST(Op, DAG);
2130 return lowerVASTART(Op, DAG);
2132 return lowerVACOPY(Op, DAG);
2133 case ISD::DYNAMIC_STACKALLOC:
2134 return lowerDYNAMIC_STACKALLOC(Op, DAG);
2135 case ISD::SMUL_LOHI:
2136 return lowerSMUL_LOHI(Op, DAG);
2137 case ISD::UMUL_LOHI:
2138 return lowerUMUL_LOHI(Op, DAG);
2140 return lowerSDIVREM(Op, DAG);
2142 return lowerUDIVREM(Op, DAG);
2144 return lowerOR(Op, DAG);
2145 case ISD::ATOMIC_SWAP:
2146 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_SWAPW);
2147 case ISD::ATOMIC_LOAD_ADD:
2148 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_ADD);
2149 case ISD::ATOMIC_LOAD_SUB:
2150 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_SUB);
2151 case ISD::ATOMIC_LOAD_AND:
2152 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_AND);
2153 case ISD::ATOMIC_LOAD_OR:
2154 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_OR);
2155 case ISD::ATOMIC_LOAD_XOR:
2156 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_XOR);
2157 case ISD::ATOMIC_LOAD_NAND:
2158 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_NAND);
2159 case ISD::ATOMIC_LOAD_MIN:
2160 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_MIN);
2161 case ISD::ATOMIC_LOAD_MAX:
2162 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_MAX);
2163 case ISD::ATOMIC_LOAD_UMIN:
2164 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_UMIN);
2165 case ISD::ATOMIC_LOAD_UMAX:
2166 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_UMAX);
2167 case ISD::ATOMIC_CMP_SWAP:
2168 return lowerATOMIC_CMP_SWAP(Op, DAG);
2169 case ISD::STACKSAVE:
2170 return lowerSTACKSAVE(Op, DAG);
2171 case ISD::STACKRESTORE:
2172 return lowerSTACKRESTORE(Op, DAG);
2174 return lowerPREFETCH(Op, DAG);
2176 llvm_unreachable("Unexpected node to lower");
2180 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
2181 #define OPCODE(NAME) case SystemZISD::NAME: return "SystemZISD::" #NAME
2186 OPCODE(PCREL_WRAPPER);
2187 OPCODE(PCREL_OFFSET);
2192 OPCODE(SELECT_CCMASK);
2193 OPCODE(ADJDYNALLOC);
2194 OPCODE(EXTRACT_ACCESS);
2195 OPCODE(UMUL_LOHI64);
2211 OPCODE(SEARCH_STRING);
2213 OPCODE(ATOMIC_SWAPW);
2214 OPCODE(ATOMIC_LOADW_ADD);
2215 OPCODE(ATOMIC_LOADW_SUB);
2216 OPCODE(ATOMIC_LOADW_AND);
2217 OPCODE(ATOMIC_LOADW_OR);
2218 OPCODE(ATOMIC_LOADW_XOR);
2219 OPCODE(ATOMIC_LOADW_NAND);
2220 OPCODE(ATOMIC_LOADW_MIN);
2221 OPCODE(ATOMIC_LOADW_MAX);
2222 OPCODE(ATOMIC_LOADW_UMIN);
2223 OPCODE(ATOMIC_LOADW_UMAX);
2224 OPCODE(ATOMIC_CMP_SWAPW);
2231 //===----------------------------------------------------------------------===//
2233 //===----------------------------------------------------------------------===//
2235 // Create a new basic block after MBB.
2236 static MachineBasicBlock *emitBlockAfter(MachineBasicBlock *MBB) {
2237 MachineFunction &MF = *MBB->getParent();
2238 MachineBasicBlock *NewMBB = MF.CreateMachineBasicBlock(MBB->getBasicBlock());
2239 MF.insert(llvm::next(MachineFunction::iterator(MBB)), NewMBB);
2243 // Split MBB after MI and return the new block (the one that contains
2244 // instructions after MI).
2245 static MachineBasicBlock *splitBlockAfter(MachineInstr *MI,
2246 MachineBasicBlock *MBB) {
2247 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
2248 NewMBB->splice(NewMBB->begin(), MBB,
2249 llvm::next(MachineBasicBlock::iterator(MI)),
2251 NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
2255 // Split MBB before MI and return the new block (the one that contains MI).
2256 static MachineBasicBlock *splitBlockBefore(MachineInstr *MI,
2257 MachineBasicBlock *MBB) {
2258 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
2259 NewMBB->splice(NewMBB->begin(), MBB, MI, MBB->end());
2260 NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
2264 // Force base value Base into a register before MI. Return the register.
2265 static unsigned forceReg(MachineInstr *MI, MachineOperand &Base,
2266 const SystemZInstrInfo *TII) {
2268 return Base.getReg();
2270 MachineBasicBlock *MBB = MI->getParent();
2271 MachineFunction &MF = *MBB->getParent();
2272 MachineRegisterInfo &MRI = MF.getRegInfo();
2274 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
2275 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LA), Reg)
2276 .addOperand(Base).addImm(0).addReg(0);
2280 // Implement EmitInstrWithCustomInserter for pseudo Select* instruction MI.
2282 SystemZTargetLowering::emitSelect(MachineInstr *MI,
2283 MachineBasicBlock *MBB) const {
2284 const SystemZInstrInfo *TII = TM.getInstrInfo();
2286 unsigned DestReg = MI->getOperand(0).getReg();
2287 unsigned TrueReg = MI->getOperand(1).getReg();
2288 unsigned FalseReg = MI->getOperand(2).getReg();
2289 unsigned CCValid = MI->getOperand(3).getImm();
2290 unsigned CCMask = MI->getOperand(4).getImm();
2291 DebugLoc DL = MI->getDebugLoc();
2293 MachineBasicBlock *StartMBB = MBB;
2294 MachineBasicBlock *JoinMBB = splitBlockBefore(MI, MBB);
2295 MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
2298 // BRC CCMask, JoinMBB
2299 // # fallthrough to FalseMBB
2301 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2302 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
2303 MBB->addSuccessor(JoinMBB);
2304 MBB->addSuccessor(FalseMBB);
2307 // # fallthrough to JoinMBB
2309 MBB->addSuccessor(JoinMBB);
2312 // %Result = phi [ %FalseReg, FalseMBB ], [ %TrueReg, StartMBB ]
2315 BuildMI(*MBB, MI, DL, TII->get(SystemZ::PHI), DestReg)
2316 .addReg(TrueReg).addMBB(StartMBB)
2317 .addReg(FalseReg).addMBB(FalseMBB);
2319 MI->eraseFromParent();
2323 // Implement EmitInstrWithCustomInserter for pseudo CondStore* instruction MI.
2324 // StoreOpcode is the store to use and Invert says whether the store should
2325 // happen when the condition is false rather than true. If a STORE ON
2326 // CONDITION is available, STOCOpcode is its opcode, otherwise it is 0.
2328 SystemZTargetLowering::emitCondStore(MachineInstr *MI,
2329 MachineBasicBlock *MBB,
2330 unsigned StoreOpcode, unsigned STOCOpcode,
2331 bool Invert) const {
2332 const SystemZInstrInfo *TII = TM.getInstrInfo();
2334 unsigned SrcReg = MI->getOperand(0).getReg();
2335 MachineOperand Base = MI->getOperand(1);
2336 int64_t Disp = MI->getOperand(2).getImm();
2337 unsigned IndexReg = MI->getOperand(3).getReg();
2338 unsigned CCValid = MI->getOperand(4).getImm();
2339 unsigned CCMask = MI->getOperand(5).getImm();
2340 DebugLoc DL = MI->getDebugLoc();
2342 StoreOpcode = TII->getOpcodeForOffset(StoreOpcode, Disp);
2344 // Use STOCOpcode if possible. We could use different store patterns in
2345 // order to avoid matching the index register, but the performance trade-offs
2346 // might be more complicated in that case.
2347 if (STOCOpcode && !IndexReg && TM.getSubtargetImpl()->hasLoadStoreOnCond()) {
2350 BuildMI(*MBB, MI, DL, TII->get(STOCOpcode))
2351 .addReg(SrcReg).addOperand(Base).addImm(Disp)
2352 .addImm(CCValid).addImm(CCMask);
2353 MI->eraseFromParent();
2357 // Get the condition needed to branch around the store.
2361 MachineBasicBlock *StartMBB = MBB;
2362 MachineBasicBlock *JoinMBB = splitBlockBefore(MI, MBB);
2363 MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
2366 // BRC CCMask, JoinMBB
2367 // # fallthrough to FalseMBB
2369 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2370 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
2371 MBB->addSuccessor(JoinMBB);
2372 MBB->addSuccessor(FalseMBB);
2375 // store %SrcReg, %Disp(%Index,%Base)
2376 // # fallthrough to JoinMBB
2378 BuildMI(MBB, DL, TII->get(StoreOpcode))
2379 .addReg(SrcReg).addOperand(Base).addImm(Disp).addReg(IndexReg);
2380 MBB->addSuccessor(JoinMBB);
2382 MI->eraseFromParent();
2386 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_LOAD{,W}_*
2387 // or ATOMIC_SWAP{,W} instruction MI. BinOpcode is the instruction that
2388 // performs the binary operation elided by "*", or 0 for ATOMIC_SWAP{,W}.
2389 // BitSize is the width of the field in bits, or 0 if this is a partword
2390 // ATOMIC_LOADW_* or ATOMIC_SWAPW instruction, in which case the bitsize
2391 // is one of the operands. Invert says whether the field should be
2392 // inverted after performing BinOpcode (e.g. for NAND).
2394 SystemZTargetLowering::emitAtomicLoadBinary(MachineInstr *MI,
2395 MachineBasicBlock *MBB,
2398 bool Invert) const {
2399 const SystemZInstrInfo *TII = TM.getInstrInfo();
2400 MachineFunction &MF = *MBB->getParent();
2401 MachineRegisterInfo &MRI = MF.getRegInfo();
2402 bool IsSubWord = (BitSize < 32);
2404 // Extract the operands. Base can be a register or a frame index.
2405 // Src2 can be a register or immediate.
2406 unsigned Dest = MI->getOperand(0).getReg();
2407 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
2408 int64_t Disp = MI->getOperand(2).getImm();
2409 MachineOperand Src2 = earlyUseOperand(MI->getOperand(3));
2410 unsigned BitShift = (IsSubWord ? MI->getOperand(4).getReg() : 0);
2411 unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0);
2412 DebugLoc DL = MI->getDebugLoc();
2414 BitSize = MI->getOperand(6).getImm();
2416 // Subword operations use 32-bit registers.
2417 const TargetRegisterClass *RC = (BitSize <= 32 ?
2418 &SystemZ::GR32BitRegClass :
2419 &SystemZ::GR64BitRegClass);
2420 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
2421 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
2423 // Get the right opcodes for the displacement.
2424 LOpcode = TII->getOpcodeForOffset(LOpcode, Disp);
2425 CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
2426 assert(LOpcode && CSOpcode && "Displacement out of range");
2428 // Create virtual registers for temporary results.
2429 unsigned OrigVal = MRI.createVirtualRegister(RC);
2430 unsigned OldVal = MRI.createVirtualRegister(RC);
2431 unsigned NewVal = (BinOpcode || IsSubWord ?
2432 MRI.createVirtualRegister(RC) : Src2.getReg());
2433 unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
2434 unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
2436 // Insert a basic block for the main loop.
2437 MachineBasicBlock *StartMBB = MBB;
2438 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
2439 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
2443 // %OrigVal = L Disp(%Base)
2444 // # fall through to LoopMMB
2446 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
2447 .addOperand(Base).addImm(Disp).addReg(0);
2448 MBB->addSuccessor(LoopMBB);
2451 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, LoopMBB ]
2452 // %RotatedOldVal = RLL %OldVal, 0(%BitShift)
2453 // %RotatedNewVal = OP %RotatedOldVal, %Src2
2454 // %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
2455 // %Dest = CS %OldVal, %NewVal, Disp(%Base)
2457 // # fall through to DoneMMB
2459 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
2460 .addReg(OrigVal).addMBB(StartMBB)
2461 .addReg(Dest).addMBB(LoopMBB);
2463 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
2464 .addReg(OldVal).addReg(BitShift).addImm(0);
2466 // Perform the operation normally and then invert every bit of the field.
2467 unsigned Tmp = MRI.createVirtualRegister(RC);
2468 BuildMI(MBB, DL, TII->get(BinOpcode), Tmp)
2469 .addReg(RotatedOldVal).addOperand(Src2);
2471 // XILF with the upper BitSize bits set.
2472 BuildMI(MBB, DL, TII->get(SystemZ::XILF), RotatedNewVal)
2473 .addReg(Tmp).addImm(uint32_t(~0 << (32 - BitSize)));
2474 else if (BitSize == 32)
2475 // XILF with every bit set.
2476 BuildMI(MBB, DL, TII->get(SystemZ::XILF), RotatedNewVal)
2477 .addReg(Tmp).addImm(~uint32_t(0));
2479 // Use LCGR and add -1 to the result, which is more compact than
2480 // an XILF, XILH pair.
2481 unsigned Tmp2 = MRI.createVirtualRegister(RC);
2482 BuildMI(MBB, DL, TII->get(SystemZ::LCGR), Tmp2).addReg(Tmp);
2483 BuildMI(MBB, DL, TII->get(SystemZ::AGHI), RotatedNewVal)
2484 .addReg(Tmp2).addImm(-1);
2486 } else if (BinOpcode)
2487 // A simply binary operation.
2488 BuildMI(MBB, DL, TII->get(BinOpcode), RotatedNewVal)
2489 .addReg(RotatedOldVal).addOperand(Src2);
2491 // Use RISBG to rotate Src2 into position and use it to replace the
2492 // field in RotatedOldVal.
2493 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedNewVal)
2494 .addReg(RotatedOldVal).addReg(Src2.getReg())
2495 .addImm(32).addImm(31 + BitSize).addImm(32 - BitSize);
2497 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
2498 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
2499 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
2500 .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
2501 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2502 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
2503 MBB->addSuccessor(LoopMBB);
2504 MBB->addSuccessor(DoneMBB);
2506 MI->eraseFromParent();
2510 // Implement EmitInstrWithCustomInserter for pseudo
2511 // ATOMIC_LOAD{,W}_{,U}{MIN,MAX} instruction MI. CompareOpcode is the
2512 // instruction that should be used to compare the current field with the
2513 // minimum or maximum value. KeepOldMask is the BRC condition-code mask
2514 // for when the current field should be kept. BitSize is the width of
2515 // the field in bits, or 0 if this is a partword ATOMIC_LOADW_* instruction.
2517 SystemZTargetLowering::emitAtomicLoadMinMax(MachineInstr *MI,
2518 MachineBasicBlock *MBB,
2519 unsigned CompareOpcode,
2520 unsigned KeepOldMask,
2521 unsigned BitSize) const {
2522 const SystemZInstrInfo *TII = TM.getInstrInfo();
2523 MachineFunction &MF = *MBB->getParent();
2524 MachineRegisterInfo &MRI = MF.getRegInfo();
2525 bool IsSubWord = (BitSize < 32);
2527 // Extract the operands. Base can be a register or a frame index.
2528 unsigned Dest = MI->getOperand(0).getReg();
2529 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
2530 int64_t Disp = MI->getOperand(2).getImm();
2531 unsigned Src2 = MI->getOperand(3).getReg();
2532 unsigned BitShift = (IsSubWord ? MI->getOperand(4).getReg() : 0);
2533 unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0);
2534 DebugLoc DL = MI->getDebugLoc();
2536 BitSize = MI->getOperand(6).getImm();
2538 // Subword operations use 32-bit registers.
2539 const TargetRegisterClass *RC = (BitSize <= 32 ?
2540 &SystemZ::GR32BitRegClass :
2541 &SystemZ::GR64BitRegClass);
2542 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
2543 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
2545 // Get the right opcodes for the displacement.
2546 LOpcode = TII->getOpcodeForOffset(LOpcode, Disp);
2547 CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
2548 assert(LOpcode && CSOpcode && "Displacement out of range");
2550 // Create virtual registers for temporary results.
2551 unsigned OrigVal = MRI.createVirtualRegister(RC);
2552 unsigned OldVal = MRI.createVirtualRegister(RC);
2553 unsigned NewVal = MRI.createVirtualRegister(RC);
2554 unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
2555 unsigned RotatedAltVal = (IsSubWord ? MRI.createVirtualRegister(RC) : Src2);
2556 unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
2558 // Insert 3 basic blocks for the loop.
2559 MachineBasicBlock *StartMBB = MBB;
2560 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
2561 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
2562 MachineBasicBlock *UseAltMBB = emitBlockAfter(LoopMBB);
2563 MachineBasicBlock *UpdateMBB = emitBlockAfter(UseAltMBB);
2567 // %OrigVal = L Disp(%Base)
2568 // # fall through to LoopMMB
2570 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
2571 .addOperand(Base).addImm(Disp).addReg(0);
2572 MBB->addSuccessor(LoopMBB);
2575 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, UpdateMBB ]
2576 // %RotatedOldVal = RLL %OldVal, 0(%BitShift)
2577 // CompareOpcode %RotatedOldVal, %Src2
2578 // BRC KeepOldMask, UpdateMBB
2580 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
2581 .addReg(OrigVal).addMBB(StartMBB)
2582 .addReg(Dest).addMBB(UpdateMBB);
2584 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
2585 .addReg(OldVal).addReg(BitShift).addImm(0);
2586 BuildMI(MBB, DL, TII->get(CompareOpcode))
2587 .addReg(RotatedOldVal).addReg(Src2);
2588 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2589 .addImm(SystemZ::CCMASK_ICMP).addImm(KeepOldMask).addMBB(UpdateMBB);
2590 MBB->addSuccessor(UpdateMBB);
2591 MBB->addSuccessor(UseAltMBB);
2594 // %RotatedAltVal = RISBG %RotatedOldVal, %Src2, 32, 31 + BitSize, 0
2595 // # fall through to UpdateMMB
2598 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedAltVal)
2599 .addReg(RotatedOldVal).addReg(Src2)
2600 .addImm(32).addImm(31 + BitSize).addImm(0);
2601 MBB->addSuccessor(UpdateMBB);
2604 // %RotatedNewVal = PHI [ %RotatedOldVal, LoopMBB ],
2605 // [ %RotatedAltVal, UseAltMBB ]
2606 // %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
2607 // %Dest = CS %OldVal, %NewVal, Disp(%Base)
2609 // # fall through to DoneMMB
2611 BuildMI(MBB, DL, TII->get(SystemZ::PHI), RotatedNewVal)
2612 .addReg(RotatedOldVal).addMBB(LoopMBB)
2613 .addReg(RotatedAltVal).addMBB(UseAltMBB);
2615 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
2616 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
2617 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
2618 .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
2619 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2620 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
2621 MBB->addSuccessor(LoopMBB);
2622 MBB->addSuccessor(DoneMBB);
2624 MI->eraseFromParent();
2628 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_CMP_SWAPW
2631 SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr *MI,
2632 MachineBasicBlock *MBB) const {
2633 const SystemZInstrInfo *TII = TM.getInstrInfo();
2634 MachineFunction &MF = *MBB->getParent();
2635 MachineRegisterInfo &MRI = MF.getRegInfo();
2637 // Extract the operands. Base can be a register or a frame index.
2638 unsigned Dest = MI->getOperand(0).getReg();
2639 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
2640 int64_t Disp = MI->getOperand(2).getImm();
2641 unsigned OrigCmpVal = MI->getOperand(3).getReg();
2642 unsigned OrigSwapVal = MI->getOperand(4).getReg();
2643 unsigned BitShift = MI->getOperand(5).getReg();
2644 unsigned NegBitShift = MI->getOperand(6).getReg();
2645 int64_t BitSize = MI->getOperand(7).getImm();
2646 DebugLoc DL = MI->getDebugLoc();
2648 const TargetRegisterClass *RC = &SystemZ::GR32BitRegClass;
2650 // Get the right opcodes for the displacement.
2651 unsigned LOpcode = TII->getOpcodeForOffset(SystemZ::L, Disp);
2652 unsigned CSOpcode = TII->getOpcodeForOffset(SystemZ::CS, Disp);
2653 assert(LOpcode && CSOpcode && "Displacement out of range");
2655 // Create virtual registers for temporary results.
2656 unsigned OrigOldVal = MRI.createVirtualRegister(RC);
2657 unsigned OldVal = MRI.createVirtualRegister(RC);
2658 unsigned CmpVal = MRI.createVirtualRegister(RC);
2659 unsigned SwapVal = MRI.createVirtualRegister(RC);
2660 unsigned StoreVal = MRI.createVirtualRegister(RC);
2661 unsigned RetryOldVal = MRI.createVirtualRegister(RC);
2662 unsigned RetryCmpVal = MRI.createVirtualRegister(RC);
2663 unsigned RetrySwapVal = MRI.createVirtualRegister(RC);
2665 // Insert 2 basic blocks for the loop.
2666 MachineBasicBlock *StartMBB = MBB;
2667 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
2668 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
2669 MachineBasicBlock *SetMBB = emitBlockAfter(LoopMBB);
2673 // %OrigOldVal = L Disp(%Base)
2674 // # fall through to LoopMMB
2676 BuildMI(MBB, DL, TII->get(LOpcode), OrigOldVal)
2677 .addOperand(Base).addImm(Disp).addReg(0);
2678 MBB->addSuccessor(LoopMBB);
2681 // %OldVal = phi [ %OrigOldVal, EntryBB ], [ %RetryOldVal, SetMBB ]
2682 // %CmpVal = phi [ %OrigCmpVal, EntryBB ], [ %RetryCmpVal, SetMBB ]
2683 // %SwapVal = phi [ %OrigSwapVal, EntryBB ], [ %RetrySwapVal, SetMBB ]
2684 // %Dest = RLL %OldVal, BitSize(%BitShift)
2685 // ^^ The low BitSize bits contain the field
2687 // %RetryCmpVal = RISBG32 %CmpVal, %Dest, 32, 63-BitSize, 0
2688 // ^^ Replace the upper 32-BitSize bits of the
2689 // comparison value with those that we loaded,
2690 // so that we can use a full word comparison.
2691 // CR %Dest, %RetryCmpVal
2693 // # Fall through to SetMBB
2695 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
2696 .addReg(OrigOldVal).addMBB(StartMBB)
2697 .addReg(RetryOldVal).addMBB(SetMBB);
2698 BuildMI(MBB, DL, TII->get(SystemZ::PHI), CmpVal)
2699 .addReg(OrigCmpVal).addMBB(StartMBB)
2700 .addReg(RetryCmpVal).addMBB(SetMBB);
2701 BuildMI(MBB, DL, TII->get(SystemZ::PHI), SwapVal)
2702 .addReg(OrigSwapVal).addMBB(StartMBB)
2703 .addReg(RetrySwapVal).addMBB(SetMBB);
2704 BuildMI(MBB, DL, TII->get(SystemZ::RLL), Dest)
2705 .addReg(OldVal).addReg(BitShift).addImm(BitSize);
2706 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetryCmpVal)
2707 .addReg(CmpVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
2708 BuildMI(MBB, DL, TII->get(SystemZ::CR))
2709 .addReg(Dest).addReg(RetryCmpVal);
2710 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2711 .addImm(SystemZ::CCMASK_ICMP)
2712 .addImm(SystemZ::CCMASK_CMP_NE).addMBB(DoneMBB);
2713 MBB->addSuccessor(DoneMBB);
2714 MBB->addSuccessor(SetMBB);
2717 // %RetrySwapVal = RISBG32 %SwapVal, %Dest, 32, 63-BitSize, 0
2718 // ^^ Replace the upper 32-BitSize bits of the new
2719 // value with those that we loaded.
2720 // %StoreVal = RLL %RetrySwapVal, -BitSize(%NegBitShift)
2721 // ^^ Rotate the new field to its proper position.
2722 // %RetryOldVal = CS %Dest, %StoreVal, Disp(%Base)
2724 // # fall through to ExitMMB
2726 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetrySwapVal)
2727 .addReg(SwapVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
2728 BuildMI(MBB, DL, TII->get(SystemZ::RLL), StoreVal)
2729 .addReg(RetrySwapVal).addReg(NegBitShift).addImm(-BitSize);
2730 BuildMI(MBB, DL, TII->get(CSOpcode), RetryOldVal)
2731 .addReg(OldVal).addReg(StoreVal).addOperand(Base).addImm(Disp);
2732 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2733 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
2734 MBB->addSuccessor(LoopMBB);
2735 MBB->addSuccessor(DoneMBB);
2737 MI->eraseFromParent();
2741 // Emit an extension from a GR32 or GR64 to a GR128. ClearEven is true
2742 // if the high register of the GR128 value must be cleared or false if
2743 // it's "don't care". SubReg is subreg_l32 when extending a GR32
2744 // and subreg_l64 when extending a GR64.
2746 SystemZTargetLowering::emitExt128(MachineInstr *MI,
2747 MachineBasicBlock *MBB,
2748 bool ClearEven, unsigned SubReg) const {
2749 const SystemZInstrInfo *TII = TM.getInstrInfo();
2750 MachineFunction &MF = *MBB->getParent();
2751 MachineRegisterInfo &MRI = MF.getRegInfo();
2752 DebugLoc DL = MI->getDebugLoc();
2754 unsigned Dest = MI->getOperand(0).getReg();
2755 unsigned Src = MI->getOperand(1).getReg();
2756 unsigned In128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
2758 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::IMPLICIT_DEF), In128);
2760 unsigned NewIn128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
2761 unsigned Zero64 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
2763 BuildMI(*MBB, MI, DL, TII->get(SystemZ::LLILL), Zero64)
2765 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), NewIn128)
2766 .addReg(In128).addReg(Zero64).addImm(SystemZ::subreg_h64);
2769 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dest)
2770 .addReg(In128).addReg(Src).addImm(SubReg);
2772 MI->eraseFromParent();
2777 SystemZTargetLowering::emitMemMemWrapper(MachineInstr *MI,
2778 MachineBasicBlock *MBB,
2779 unsigned Opcode) const {
2780 const SystemZInstrInfo *TII = TM.getInstrInfo();
2781 MachineFunction &MF = *MBB->getParent();
2782 MachineRegisterInfo &MRI = MF.getRegInfo();
2783 DebugLoc DL = MI->getDebugLoc();
2785 MachineOperand DestBase = earlyUseOperand(MI->getOperand(0));
2786 uint64_t DestDisp = MI->getOperand(1).getImm();
2787 MachineOperand SrcBase = earlyUseOperand(MI->getOperand(2));
2788 uint64_t SrcDisp = MI->getOperand(3).getImm();
2789 uint64_t Length = MI->getOperand(4).getImm();
2791 // When generating more than one CLC, all but the last will need to
2792 // branch to the end when a difference is found.
2793 MachineBasicBlock *EndMBB = (Length > 256 && Opcode == SystemZ::CLC ?
2794 splitBlockAfter(MI, MBB) : 0);
2796 // Check for the loop form, in which operand 5 is the trip count.
2797 if (MI->getNumExplicitOperands() > 5) {
2798 bool HaveSingleBase = DestBase.isIdenticalTo(SrcBase);
2800 uint64_t StartCountReg = MI->getOperand(5).getReg();
2801 uint64_t StartSrcReg = forceReg(MI, SrcBase, TII);
2802 uint64_t StartDestReg = (HaveSingleBase ? StartSrcReg :
2803 forceReg(MI, DestBase, TII));
2805 const TargetRegisterClass *RC = &SystemZ::ADDR64BitRegClass;
2806 uint64_t ThisSrcReg = MRI.createVirtualRegister(RC);
2807 uint64_t ThisDestReg = (HaveSingleBase ? ThisSrcReg :
2808 MRI.createVirtualRegister(RC));
2809 uint64_t NextSrcReg = MRI.createVirtualRegister(RC);
2810 uint64_t NextDestReg = (HaveSingleBase ? NextSrcReg :
2811 MRI.createVirtualRegister(RC));
2813 RC = &SystemZ::GR64BitRegClass;
2814 uint64_t ThisCountReg = MRI.createVirtualRegister(RC);
2815 uint64_t NextCountReg = MRI.createVirtualRegister(RC);
2817 MachineBasicBlock *StartMBB = MBB;
2818 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
2819 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
2820 MachineBasicBlock *NextMBB = (EndMBB ? emitBlockAfter(LoopMBB) : LoopMBB);
2823 // # fall through to LoopMMB
2824 MBB->addSuccessor(LoopMBB);
2827 // %ThisDestReg = phi [ %StartDestReg, StartMBB ],
2828 // [ %NextDestReg, NextMBB ]
2829 // %ThisSrcReg = phi [ %StartSrcReg, StartMBB ],
2830 // [ %NextSrcReg, NextMBB ]
2831 // %ThisCountReg = phi [ %StartCountReg, StartMBB ],
2832 // [ %NextCountReg, NextMBB ]
2833 // ( PFD 2, 768+DestDisp(%ThisDestReg) )
2834 // Opcode DestDisp(256,%ThisDestReg), SrcDisp(%ThisSrcReg)
2837 // The prefetch is used only for MVC. The JLH is used only for CLC.
2840 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisDestReg)
2841 .addReg(StartDestReg).addMBB(StartMBB)
2842 .addReg(NextDestReg).addMBB(NextMBB);
2843 if (!HaveSingleBase)
2844 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisSrcReg)
2845 .addReg(StartSrcReg).addMBB(StartMBB)
2846 .addReg(NextSrcReg).addMBB(NextMBB);
2847 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisCountReg)
2848 .addReg(StartCountReg).addMBB(StartMBB)
2849 .addReg(NextCountReg).addMBB(NextMBB);
2850 if (Opcode == SystemZ::MVC)
2851 BuildMI(MBB, DL, TII->get(SystemZ::PFD))
2852 .addImm(SystemZ::PFD_WRITE)
2853 .addReg(ThisDestReg).addImm(DestDisp + 768).addReg(0);
2854 BuildMI(MBB, DL, TII->get(Opcode))
2855 .addReg(ThisDestReg).addImm(DestDisp).addImm(256)
2856 .addReg(ThisSrcReg).addImm(SrcDisp);
2858 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2859 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
2861 MBB->addSuccessor(EndMBB);
2862 MBB->addSuccessor(NextMBB);
2866 // %NextDestReg = LA 256(%ThisDestReg)
2867 // %NextSrcReg = LA 256(%ThisSrcReg)
2868 // %NextCountReg = AGHI %ThisCountReg, -1
2869 // CGHI %NextCountReg, 0
2871 // # fall through to DoneMMB
2873 // The AGHI, CGHI and JLH should be converted to BRCTG by later passes.
2876 BuildMI(MBB, DL, TII->get(SystemZ::LA), NextDestReg)
2877 .addReg(ThisDestReg).addImm(256).addReg(0);
2878 if (!HaveSingleBase)
2879 BuildMI(MBB, DL, TII->get(SystemZ::LA), NextSrcReg)
2880 .addReg(ThisSrcReg).addImm(256).addReg(0);
2881 BuildMI(MBB, DL, TII->get(SystemZ::AGHI), NextCountReg)
2882 .addReg(ThisCountReg).addImm(-1);
2883 BuildMI(MBB, DL, TII->get(SystemZ::CGHI))
2884 .addReg(NextCountReg).addImm(0);
2885 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2886 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
2888 MBB->addSuccessor(LoopMBB);
2889 MBB->addSuccessor(DoneMBB);
2891 DestBase = MachineOperand::CreateReg(NextDestReg, false);
2892 SrcBase = MachineOperand::CreateReg(NextSrcReg, false);
2896 // Handle any remaining bytes with straight-line code.
2897 while (Length > 0) {
2898 uint64_t ThisLength = std::min(Length, uint64_t(256));
2899 // The previous iteration might have created out-of-range displacements.
2900 // Apply them using LAY if so.
2901 if (!isUInt<12>(DestDisp)) {
2902 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
2903 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LAY), Reg)
2904 .addOperand(DestBase).addImm(DestDisp).addReg(0);
2905 DestBase = MachineOperand::CreateReg(Reg, false);
2908 if (!isUInt<12>(SrcDisp)) {
2909 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
2910 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LAY), Reg)
2911 .addOperand(SrcBase).addImm(SrcDisp).addReg(0);
2912 SrcBase = MachineOperand::CreateReg(Reg, false);
2915 BuildMI(*MBB, MI, DL, TII->get(Opcode))
2916 .addOperand(DestBase).addImm(DestDisp).addImm(ThisLength)
2917 .addOperand(SrcBase).addImm(SrcDisp);
2918 DestDisp += ThisLength;
2919 SrcDisp += ThisLength;
2920 Length -= ThisLength;
2921 // If there's another CLC to go, branch to the end if a difference
2923 if (EndMBB && Length > 0) {
2924 MachineBasicBlock *NextMBB = splitBlockBefore(MI, MBB);
2925 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2926 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
2928 MBB->addSuccessor(EndMBB);
2929 MBB->addSuccessor(NextMBB);
2934 MBB->addSuccessor(EndMBB);
2936 MBB->addLiveIn(SystemZ::CC);
2939 MI->eraseFromParent();
2943 // Decompose string pseudo-instruction MI into a loop that continually performs
2944 // Opcode until CC != 3.
2946 SystemZTargetLowering::emitStringWrapper(MachineInstr *MI,
2947 MachineBasicBlock *MBB,
2948 unsigned Opcode) const {
2949 const SystemZInstrInfo *TII = TM.getInstrInfo();
2950 MachineFunction &MF = *MBB->getParent();
2951 MachineRegisterInfo &MRI = MF.getRegInfo();
2952 DebugLoc DL = MI->getDebugLoc();
2954 uint64_t End1Reg = MI->getOperand(0).getReg();
2955 uint64_t Start1Reg = MI->getOperand(1).getReg();
2956 uint64_t Start2Reg = MI->getOperand(2).getReg();
2957 uint64_t CharReg = MI->getOperand(3).getReg();
2959 const TargetRegisterClass *RC = &SystemZ::GR64BitRegClass;
2960 uint64_t This1Reg = MRI.createVirtualRegister(RC);
2961 uint64_t This2Reg = MRI.createVirtualRegister(RC);
2962 uint64_t End2Reg = MRI.createVirtualRegister(RC);
2964 MachineBasicBlock *StartMBB = MBB;
2965 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
2966 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
2969 // # fall through to LoopMMB
2970 MBB->addSuccessor(LoopMBB);
2973 // %This1Reg = phi [ %Start1Reg, StartMBB ], [ %End1Reg, LoopMBB ]
2974 // %This2Reg = phi [ %Start2Reg, StartMBB ], [ %End2Reg, LoopMBB ]
2976 // %End1Reg, %End2Reg = CLST %This1Reg, %This2Reg -- uses R0L
2978 // # fall through to DoneMMB
2980 // The load of R0L can be hoisted by post-RA LICM.
2983 BuildMI(MBB, DL, TII->get(SystemZ::PHI), This1Reg)
2984 .addReg(Start1Reg).addMBB(StartMBB)
2985 .addReg(End1Reg).addMBB(LoopMBB);
2986 BuildMI(MBB, DL, TII->get(SystemZ::PHI), This2Reg)
2987 .addReg(Start2Reg).addMBB(StartMBB)
2988 .addReg(End2Reg).addMBB(LoopMBB);
2989 BuildMI(MBB, DL, TII->get(TargetOpcode::COPY), SystemZ::R0L).addReg(CharReg);
2990 BuildMI(MBB, DL, TII->get(Opcode))
2991 .addReg(End1Reg, RegState::Define).addReg(End2Reg, RegState::Define)
2992 .addReg(This1Reg).addReg(This2Reg);
2993 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2994 .addImm(SystemZ::CCMASK_ANY).addImm(SystemZ::CCMASK_3).addMBB(LoopMBB);
2995 MBB->addSuccessor(LoopMBB);
2996 MBB->addSuccessor(DoneMBB);
2998 DoneMBB->addLiveIn(SystemZ::CC);
3000 MI->eraseFromParent();
3004 MachineBasicBlock *SystemZTargetLowering::
3005 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const {
3006 switch (MI->getOpcode()) {
3007 case SystemZ::Select32Mux:
3008 case SystemZ::Select32:
3009 case SystemZ::SelectF32:
3010 case SystemZ::Select64:
3011 case SystemZ::SelectF64:
3012 case SystemZ::SelectF128:
3013 return emitSelect(MI, MBB);
3015 case SystemZ::CondStore8Mux:
3016 return emitCondStore(MI, MBB, SystemZ::STCMux, 0, false);
3017 case SystemZ::CondStore8MuxInv:
3018 return emitCondStore(MI, MBB, SystemZ::STCMux, 0, true);
3019 case SystemZ::CondStore16Mux:
3020 return emitCondStore(MI, MBB, SystemZ::STHMux, 0, false);
3021 case SystemZ::CondStore16MuxInv:
3022 return emitCondStore(MI, MBB, SystemZ::STHMux, 0, true);
3023 case SystemZ::CondStore8:
3024 return emitCondStore(MI, MBB, SystemZ::STC, 0, false);
3025 case SystemZ::CondStore8Inv:
3026 return emitCondStore(MI, MBB, SystemZ::STC, 0, true);
3027 case SystemZ::CondStore16:
3028 return emitCondStore(MI, MBB, SystemZ::STH, 0, false);
3029 case SystemZ::CondStore16Inv:
3030 return emitCondStore(MI, MBB, SystemZ::STH, 0, true);
3031 case SystemZ::CondStore32:
3032 return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, false);
3033 case SystemZ::CondStore32Inv:
3034 return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, true);
3035 case SystemZ::CondStore64:
3036 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, false);
3037 case SystemZ::CondStore64Inv:
3038 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, true);
3039 case SystemZ::CondStoreF32:
3040 return emitCondStore(MI, MBB, SystemZ::STE, 0, false);
3041 case SystemZ::CondStoreF32Inv:
3042 return emitCondStore(MI, MBB, SystemZ::STE, 0, true);
3043 case SystemZ::CondStoreF64:
3044 return emitCondStore(MI, MBB, SystemZ::STD, 0, false);
3045 case SystemZ::CondStoreF64Inv:
3046 return emitCondStore(MI, MBB, SystemZ::STD, 0, true);
3048 case SystemZ::AEXT128_64:
3049 return emitExt128(MI, MBB, false, SystemZ::subreg_l64);
3050 case SystemZ::ZEXT128_32:
3051 return emitExt128(MI, MBB, true, SystemZ::subreg_l32);
3052 case SystemZ::ZEXT128_64:
3053 return emitExt128(MI, MBB, true, SystemZ::subreg_l64);
3055 case SystemZ::ATOMIC_SWAPW:
3056 return emitAtomicLoadBinary(MI, MBB, 0, 0);
3057 case SystemZ::ATOMIC_SWAP_32:
3058 return emitAtomicLoadBinary(MI, MBB, 0, 32);
3059 case SystemZ::ATOMIC_SWAP_64:
3060 return emitAtomicLoadBinary(MI, MBB, 0, 64);
3062 case SystemZ::ATOMIC_LOADW_AR:
3063 return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 0);
3064 case SystemZ::ATOMIC_LOADW_AFI:
3065 return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 0);
3066 case SystemZ::ATOMIC_LOAD_AR:
3067 return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 32);
3068 case SystemZ::ATOMIC_LOAD_AHI:
3069 return emitAtomicLoadBinary(MI, MBB, SystemZ::AHI, 32);
3070 case SystemZ::ATOMIC_LOAD_AFI:
3071 return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 32);
3072 case SystemZ::ATOMIC_LOAD_AGR:
3073 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGR, 64);
3074 case SystemZ::ATOMIC_LOAD_AGHI:
3075 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGHI, 64);
3076 case SystemZ::ATOMIC_LOAD_AGFI:
3077 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGFI, 64);
3079 case SystemZ::ATOMIC_LOADW_SR:
3080 return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 0);
3081 case SystemZ::ATOMIC_LOAD_SR:
3082 return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 32);
3083 case SystemZ::ATOMIC_LOAD_SGR:
3084 return emitAtomicLoadBinary(MI, MBB, SystemZ::SGR, 64);
3086 case SystemZ::ATOMIC_LOADW_NR:
3087 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0);
3088 case SystemZ::ATOMIC_LOADW_NILH:
3089 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 0);
3090 case SystemZ::ATOMIC_LOAD_NR:
3091 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32);
3092 case SystemZ::ATOMIC_LOAD_NILL:
3093 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 32);
3094 case SystemZ::ATOMIC_LOAD_NILH:
3095 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 32);
3096 case SystemZ::ATOMIC_LOAD_NILF:
3097 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 32);
3098 case SystemZ::ATOMIC_LOAD_NGR:
3099 return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64);
3100 case SystemZ::ATOMIC_LOAD_NILL64:
3101 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL64, 64);
3102 case SystemZ::ATOMIC_LOAD_NILH64:
3103 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH64, 64);
3104 case SystemZ::ATOMIC_LOAD_NIHL64:
3105 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL64, 64);
3106 case SystemZ::ATOMIC_LOAD_NIHH64:
3107 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH64, 64);
3108 case SystemZ::ATOMIC_LOAD_NILF64:
3109 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF64, 64);
3110 case SystemZ::ATOMIC_LOAD_NIHF64:
3111 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF64, 64);
3113 case SystemZ::ATOMIC_LOADW_OR:
3114 return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 0);
3115 case SystemZ::ATOMIC_LOADW_OILH:
3116 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 0);
3117 case SystemZ::ATOMIC_LOAD_OR:
3118 return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 32);
3119 case SystemZ::ATOMIC_LOAD_OILL:
3120 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL, 32);
3121 case SystemZ::ATOMIC_LOAD_OILH:
3122 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 32);
3123 case SystemZ::ATOMIC_LOAD_OILF:
3124 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF, 32);
3125 case SystemZ::ATOMIC_LOAD_OGR:
3126 return emitAtomicLoadBinary(MI, MBB, SystemZ::OGR, 64);
3127 case SystemZ::ATOMIC_LOAD_OILL64:
3128 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL64, 64);
3129 case SystemZ::ATOMIC_LOAD_OILH64:
3130 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH64, 64);
3131 case SystemZ::ATOMIC_LOAD_OIHL64:
3132 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHL64, 64);
3133 case SystemZ::ATOMIC_LOAD_OIHH64:
3134 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHH64, 64);
3135 case SystemZ::ATOMIC_LOAD_OILF64:
3136 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF64, 64);
3137 case SystemZ::ATOMIC_LOAD_OIHF64:
3138 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHF64, 64);
3140 case SystemZ::ATOMIC_LOADW_XR:
3141 return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 0);
3142 case SystemZ::ATOMIC_LOADW_XILF:
3143 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 0);
3144 case SystemZ::ATOMIC_LOAD_XR:
3145 return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 32);
3146 case SystemZ::ATOMIC_LOAD_XILF:
3147 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 32);
3148 case SystemZ::ATOMIC_LOAD_XGR:
3149 return emitAtomicLoadBinary(MI, MBB, SystemZ::XGR, 64);
3150 case SystemZ::ATOMIC_LOAD_XILF64:
3151 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF64, 64);
3152 case SystemZ::ATOMIC_LOAD_XIHF64:
3153 return emitAtomicLoadBinary(MI, MBB, SystemZ::XIHF64, 64);
3155 case SystemZ::ATOMIC_LOADW_NRi:
3156 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0, true);
3157 case SystemZ::ATOMIC_LOADW_NILHi:
3158 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 0, true);
3159 case SystemZ::ATOMIC_LOAD_NRi:
3160 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32, true);
3161 case SystemZ::ATOMIC_LOAD_NILLi:
3162 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 32, true);
3163 case SystemZ::ATOMIC_LOAD_NILHi:
3164 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 32, true);
3165 case SystemZ::ATOMIC_LOAD_NILFi:
3166 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 32, true);
3167 case SystemZ::ATOMIC_LOAD_NGRi:
3168 return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64, true);
3169 case SystemZ::ATOMIC_LOAD_NILL64i:
3170 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL64, 64, true);
3171 case SystemZ::ATOMIC_LOAD_NILH64i:
3172 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH64, 64, true);
3173 case SystemZ::ATOMIC_LOAD_NIHL64i:
3174 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL64, 64, true);
3175 case SystemZ::ATOMIC_LOAD_NIHH64i:
3176 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH64, 64, true);
3177 case SystemZ::ATOMIC_LOAD_NILF64i:
3178 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF64, 64, true);
3179 case SystemZ::ATOMIC_LOAD_NIHF64i:
3180 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF64, 64, true);
3182 case SystemZ::ATOMIC_LOADW_MIN:
3183 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
3184 SystemZ::CCMASK_CMP_LE, 0);
3185 case SystemZ::ATOMIC_LOAD_MIN_32:
3186 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
3187 SystemZ::CCMASK_CMP_LE, 32);
3188 case SystemZ::ATOMIC_LOAD_MIN_64:
3189 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
3190 SystemZ::CCMASK_CMP_LE, 64);
3192 case SystemZ::ATOMIC_LOADW_MAX:
3193 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
3194 SystemZ::CCMASK_CMP_GE, 0);
3195 case SystemZ::ATOMIC_LOAD_MAX_32:
3196 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
3197 SystemZ::CCMASK_CMP_GE, 32);
3198 case SystemZ::ATOMIC_LOAD_MAX_64:
3199 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
3200 SystemZ::CCMASK_CMP_GE, 64);
3202 case SystemZ::ATOMIC_LOADW_UMIN:
3203 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
3204 SystemZ::CCMASK_CMP_LE, 0);
3205 case SystemZ::ATOMIC_LOAD_UMIN_32:
3206 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
3207 SystemZ::CCMASK_CMP_LE, 32);
3208 case SystemZ::ATOMIC_LOAD_UMIN_64:
3209 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
3210 SystemZ::CCMASK_CMP_LE, 64);
3212 case SystemZ::ATOMIC_LOADW_UMAX:
3213 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
3214 SystemZ::CCMASK_CMP_GE, 0);
3215 case SystemZ::ATOMIC_LOAD_UMAX_32:
3216 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
3217 SystemZ::CCMASK_CMP_GE, 32);
3218 case SystemZ::ATOMIC_LOAD_UMAX_64:
3219 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
3220 SystemZ::CCMASK_CMP_GE, 64);
3222 case SystemZ::ATOMIC_CMP_SWAPW:
3223 return emitAtomicCmpSwapW(MI, MBB);
3224 case SystemZ::MVCSequence:
3225 case SystemZ::MVCLoop:
3226 return emitMemMemWrapper(MI, MBB, SystemZ::MVC);
3227 case SystemZ::NCSequence:
3228 case SystemZ::NCLoop:
3229 return emitMemMemWrapper(MI, MBB, SystemZ::NC);
3230 case SystemZ::OCSequence:
3231 case SystemZ::OCLoop:
3232 return emitMemMemWrapper(MI, MBB, SystemZ::OC);
3233 case SystemZ::XCSequence:
3234 case SystemZ::XCLoop:
3235 return emitMemMemWrapper(MI, MBB, SystemZ::XC);
3236 case SystemZ::CLCSequence:
3237 case SystemZ::CLCLoop:
3238 return emitMemMemWrapper(MI, MBB, SystemZ::CLC);
3239 case SystemZ::CLSTLoop:
3240 return emitStringWrapper(MI, MBB, SystemZ::CLST);
3241 case SystemZ::MVSTLoop:
3242 return emitStringWrapper(MI, MBB, SystemZ::MVST);
3243 case SystemZ::SRSTLoop:
3244 return emitStringWrapper(MI, MBB, SystemZ::SRST);
3246 llvm_unreachable("Unexpected instr type to insert");