1 //===-- SystemZISelLowering.cpp - SystemZ DAG lowering implementation -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SystemZTargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "SystemZISelLowering.h"
15 #include "SystemZCallingConv.h"
16 #include "SystemZConstantPoolValue.h"
17 #include "SystemZMachineFunctionInfo.h"
18 #include "SystemZTargetMachine.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
23 #include "llvm/IR/Intrinsics.h"
28 #define DEBUG_TYPE "systemz-lower"
31 // Represents a sequence for extracting a 0/1 value from an IPM result:
32 // (((X ^ XORValue) + AddValue) >> Bit)
33 struct IPMConversion {
34 IPMConversion(unsigned xorValue, int64_t addValue, unsigned bit)
35 : XORValue(xorValue), AddValue(addValue), Bit(bit) {}
42 // Represents information about a comparison.
44 Comparison(SDValue Op0In, SDValue Op1In)
45 : Op0(Op0In), Op1(Op1In), Opcode(0), ICmpType(0), CCValid(0), CCMask(0) {}
47 // The operands to the comparison.
50 // The opcode that should be used to compare Op0 and Op1.
53 // A SystemZICMP value. Only used for integer comparisons.
56 // The mask of CC values that Opcode can produce.
59 // The mask of CC values for which the original condition is true.
62 } // end anonymous namespace
64 // Classify VT as either 32 or 64 bit.
65 static bool is32Bit(EVT VT) {
66 switch (VT.getSimpleVT().SimpleTy) {
72 llvm_unreachable("Unsupported type");
76 // Return a version of MachineOperand that can be safely used before the
78 static MachineOperand earlyUseOperand(MachineOperand Op) {
84 SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &tm,
85 const SystemZSubtarget &STI)
86 : TargetLowering(tm), Subtarget(STI) {
87 MVT PtrVT = getPointerTy();
89 // Set up the register classes.
90 if (Subtarget.hasHighWord())
91 addRegisterClass(MVT::i32, &SystemZ::GRX32BitRegClass);
93 addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass);
94 addRegisterClass(MVT::i64, &SystemZ::GR64BitRegClass);
95 addRegisterClass(MVT::f32, &SystemZ::FP32BitRegClass);
96 addRegisterClass(MVT::f64, &SystemZ::FP64BitRegClass);
97 addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass);
99 // Compute derived properties from the register classes
100 computeRegisterProperties(Subtarget.getRegisterInfo());
102 // Set up special registers.
103 setExceptionPointerRegister(SystemZ::R6D);
104 setExceptionSelectorRegister(SystemZ::R7D);
105 setStackPointerRegisterToSaveRestore(SystemZ::R15D);
107 // TODO: It may be better to default to latency-oriented scheduling, however
108 // LLVM's current latency-oriented scheduler can't handle physreg definitions
109 // such as SystemZ has with CC, so set this to the register-pressure
110 // scheduler, because it can.
111 setSchedulingPreference(Sched::RegPressure);
113 setBooleanContents(ZeroOrOneBooleanContent);
114 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
116 // Instructions are strings of 2-byte aligned 2-byte values.
117 setMinFunctionAlignment(2);
119 // Handle operations that are handled in a similar way for all types.
120 for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
121 I <= MVT::LAST_FP_VALUETYPE;
123 MVT VT = MVT::SimpleValueType(I);
124 if (isTypeLegal(VT)) {
125 // Lower SET_CC into an IPM-based sequence.
126 setOperationAction(ISD::SETCC, VT, Custom);
128 // Expand SELECT(C, A, B) into SELECT_CC(X, 0, A, B, NE).
129 setOperationAction(ISD::SELECT, VT, Expand);
131 // Lower SELECT_CC and BR_CC into separate comparisons and branches.
132 setOperationAction(ISD::SELECT_CC, VT, Custom);
133 setOperationAction(ISD::BR_CC, VT, Custom);
137 // Expand jump table branches as address arithmetic followed by an
139 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
141 // Expand BRCOND into a BR_CC (see above).
142 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
144 // Handle integer types.
145 for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
146 I <= MVT::LAST_INTEGER_VALUETYPE;
148 MVT VT = MVT::SimpleValueType(I);
149 if (isTypeLegal(VT)) {
150 // Expand individual DIV and REMs into DIVREMs.
151 setOperationAction(ISD::SDIV, VT, Expand);
152 setOperationAction(ISD::UDIV, VT, Expand);
153 setOperationAction(ISD::SREM, VT, Expand);
154 setOperationAction(ISD::UREM, VT, Expand);
155 setOperationAction(ISD::SDIVREM, VT, Custom);
156 setOperationAction(ISD::UDIVREM, VT, Custom);
158 // Lower ATOMIC_LOAD and ATOMIC_STORE into normal volatile loads and
159 // stores, putting a serialization instruction after the stores.
160 setOperationAction(ISD::ATOMIC_LOAD, VT, Custom);
161 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
163 // Lower ATOMIC_LOAD_SUB into ATOMIC_LOAD_ADD if LAA and LAAG are
164 // available, or if the operand is constant.
165 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
167 // Use POPCNT on z196 and above.
168 if (Subtarget.hasPopulationCount())
169 setOperationAction(ISD::CTPOP, VT, Custom);
171 setOperationAction(ISD::CTPOP, VT, Expand);
173 // No special instructions for these.
174 setOperationAction(ISD::CTTZ, VT, Expand);
175 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
176 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
177 setOperationAction(ISD::ROTR, VT, Expand);
179 // Use *MUL_LOHI where possible instead of MULH*.
180 setOperationAction(ISD::MULHS, VT, Expand);
181 setOperationAction(ISD::MULHU, VT, Expand);
182 setOperationAction(ISD::SMUL_LOHI, VT, Custom);
183 setOperationAction(ISD::UMUL_LOHI, VT, Custom);
185 // Only z196 and above have native support for conversions to unsigned.
186 if (!Subtarget.hasFPExtension())
187 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
191 // Type legalization will convert 8- and 16-bit atomic operations into
192 // forms that operate on i32s (but still keeping the original memory VT).
193 // Lower them into full i32 operations.
194 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Custom);
195 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Custom);
196 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
197 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Custom);
198 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Custom);
199 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Custom);
200 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Custom);
201 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Custom);
202 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Custom);
203 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Custom);
204 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Custom);
205 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
207 // z10 has instructions for signed but not unsigned FP conversion.
208 // Handle unsigned 32-bit types as signed 64-bit types.
209 if (!Subtarget.hasFPExtension()) {
210 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote);
211 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
214 // We have native support for a 64-bit CTLZ, via FLOGR.
215 setOperationAction(ISD::CTLZ, MVT::i32, Promote);
216 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
218 // Give LowerOperation the chance to replace 64-bit ORs with subregs.
219 setOperationAction(ISD::OR, MVT::i64, Custom);
221 // FIXME: Can we support these natively?
222 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
223 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
224 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
226 // We have native instructions for i8, i16 and i32 extensions, but not i1.
227 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
228 for (MVT VT : MVT::integer_valuetypes()) {
229 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
230 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
231 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
234 // Handle the various types of symbolic address.
235 setOperationAction(ISD::ConstantPool, PtrVT, Custom);
236 setOperationAction(ISD::GlobalAddress, PtrVT, Custom);
237 setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom);
238 setOperationAction(ISD::BlockAddress, PtrVT, Custom);
239 setOperationAction(ISD::JumpTable, PtrVT, Custom);
241 // We need to handle dynamic allocations specially because of the
242 // 160-byte area at the bottom of the stack.
243 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
245 // Use custom expanders so that we can force the function to use
247 setOperationAction(ISD::STACKSAVE, MVT::Other, Custom);
248 setOperationAction(ISD::STACKRESTORE, MVT::Other, Custom);
250 // Handle prefetches with PFD or PFDRL.
251 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
253 // Handle floating-point types.
254 for (unsigned I = MVT::FIRST_FP_VALUETYPE;
255 I <= MVT::LAST_FP_VALUETYPE;
257 MVT VT = MVT::SimpleValueType(I);
258 if (isTypeLegal(VT)) {
259 // We can use FI for FRINT.
260 setOperationAction(ISD::FRINT, VT, Legal);
262 // We can use the extended form of FI for other rounding operations.
263 if (Subtarget.hasFPExtension()) {
264 setOperationAction(ISD::FNEARBYINT, VT, Legal);
265 setOperationAction(ISD::FFLOOR, VT, Legal);
266 setOperationAction(ISD::FCEIL, VT, Legal);
267 setOperationAction(ISD::FTRUNC, VT, Legal);
268 setOperationAction(ISD::FROUND, VT, Legal);
271 // No special instructions for these.
272 setOperationAction(ISD::FSIN, VT, Expand);
273 setOperationAction(ISD::FCOS, VT, Expand);
274 setOperationAction(ISD::FREM, VT, Expand);
278 // We have fused multiply-addition for f32 and f64 but not f128.
279 setOperationAction(ISD::FMA, MVT::f32, Legal);
280 setOperationAction(ISD::FMA, MVT::f64, Legal);
281 setOperationAction(ISD::FMA, MVT::f128, Expand);
283 // Needed so that we don't try to implement f128 constant loads using
284 // a load-and-extend of a f80 constant (in cases where the constant
285 // would fit in an f80).
286 for (MVT VT : MVT::fp_valuetypes())
287 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand);
289 // Floating-point truncation and stores need to be done separately.
290 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
291 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
292 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
294 // We have 64-bit FPR<->GPR moves, but need special handling for
296 setOperationAction(ISD::BITCAST, MVT::i32, Custom);
297 setOperationAction(ISD::BITCAST, MVT::f32, Custom);
299 // VASTART and VACOPY need to deal with the SystemZ-specific varargs
300 // structure, but VAEND is a no-op.
301 setOperationAction(ISD::VASTART, MVT::Other, Custom);
302 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
303 setOperationAction(ISD::VAEND, MVT::Other, Expand);
305 // Codes for which we want to perform some z-specific combinations.
306 setTargetDAGCombine(ISD::SIGN_EXTEND);
308 // Handle intrinsics.
309 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
311 // We want to use MVC in preference to even a single load/store pair.
312 MaxStoresPerMemcpy = 0;
313 MaxStoresPerMemcpyOptSize = 0;
315 // The main memset sequence is a byte store followed by an MVC.
316 // Two STC or MV..I stores win over that, but the kind of fused stores
317 // generated by target-independent code don't when the byte value is
318 // variable. E.g. "STC <reg>;MHI <reg>,257;STH <reg>" is not better
319 // than "STC;MVC". Handle the choice in target-specific code instead.
320 MaxStoresPerMemset = 0;
321 MaxStoresPerMemsetOptSize = 0;
324 EVT SystemZTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
327 return VT.changeVectorElementTypeToInteger();
330 bool SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
331 VT = VT.getScalarType();
336 switch (VT.getSimpleVT().SimpleTy) {
349 bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
350 // We can load zero using LZ?R and negative zero using LZ?R;LC?BR.
351 return Imm.isZero() || Imm.isNegZero();
354 bool SystemZTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
355 // We can use CGFI or CLGFI.
356 return isInt<32>(Imm) || isUInt<32>(Imm);
359 bool SystemZTargetLowering::isLegalAddImmediate(int64_t Imm) const {
360 // We can use ALGFI or SLGFI.
361 return isUInt<32>(Imm) || isUInt<32>(-Imm);
364 bool SystemZTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
368 // Unaligned accesses should never be slower than the expanded version.
369 // We check specifically for aligned accesses in the few cases where
370 // they are required.
376 bool SystemZTargetLowering::isLegalAddressingMode(const AddrMode &AM,
378 // Punt on globals for now, although they can be used in limited
379 // RELATIVE LONG cases.
383 // Require a 20-bit signed offset.
384 if (!isInt<20>(AM.BaseOffs))
387 // Indexing is OK but no scale factor can be applied.
388 return AM.Scale == 0 || AM.Scale == 1;
391 bool SystemZTargetLowering::isTruncateFree(Type *FromType, Type *ToType) const {
392 if (!FromType->isIntegerTy() || !ToType->isIntegerTy())
394 unsigned FromBits = FromType->getPrimitiveSizeInBits();
395 unsigned ToBits = ToType->getPrimitiveSizeInBits();
396 return FromBits > ToBits;
399 bool SystemZTargetLowering::isTruncateFree(EVT FromVT, EVT ToVT) const {
400 if (!FromVT.isInteger() || !ToVT.isInteger())
402 unsigned FromBits = FromVT.getSizeInBits();
403 unsigned ToBits = ToVT.getSizeInBits();
404 return FromBits > ToBits;
407 //===----------------------------------------------------------------------===//
408 // Inline asm support
409 //===----------------------------------------------------------------------===//
411 TargetLowering::ConstraintType
412 SystemZTargetLowering::getConstraintType(const std::string &Constraint) const {
413 if (Constraint.size() == 1) {
414 switch (Constraint[0]) {
415 case 'a': // Address register
416 case 'd': // Data register (equivalent to 'r')
417 case 'f': // Floating-point register
418 case 'h': // High-part register
419 case 'r': // General-purpose register
420 return C_RegisterClass;
422 case 'Q': // Memory with base and unsigned 12-bit displacement
423 case 'R': // Likewise, plus an index
424 case 'S': // Memory with base and signed 20-bit displacement
425 case 'T': // Likewise, plus an index
426 case 'm': // Equivalent to 'T'.
429 case 'I': // Unsigned 8-bit constant
430 case 'J': // Unsigned 12-bit constant
431 case 'K': // Signed 16-bit constant
432 case 'L': // Signed 20-bit displacement (on all targets we support)
433 case 'M': // 0x7fffffff
440 return TargetLowering::getConstraintType(Constraint);
443 TargetLowering::ConstraintWeight SystemZTargetLowering::
444 getSingleConstraintMatchWeight(AsmOperandInfo &info,
445 const char *constraint) const {
446 ConstraintWeight weight = CW_Invalid;
447 Value *CallOperandVal = info.CallOperandVal;
448 // If we don't have a value, we can't do a match,
449 // but allow it at the lowest weight.
452 Type *type = CallOperandVal->getType();
453 // Look at the constraint type.
454 switch (*constraint) {
456 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
459 case 'a': // Address register
460 case 'd': // Data register (equivalent to 'r')
461 case 'h': // High-part register
462 case 'r': // General-purpose register
463 if (CallOperandVal->getType()->isIntegerTy())
464 weight = CW_Register;
467 case 'f': // Floating-point register
468 if (type->isFloatingPointTy())
469 weight = CW_Register;
472 case 'I': // Unsigned 8-bit constant
473 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
474 if (isUInt<8>(C->getZExtValue()))
475 weight = CW_Constant;
478 case 'J': // Unsigned 12-bit constant
479 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
480 if (isUInt<12>(C->getZExtValue()))
481 weight = CW_Constant;
484 case 'K': // Signed 16-bit constant
485 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
486 if (isInt<16>(C->getSExtValue()))
487 weight = CW_Constant;
490 case 'L': // Signed 20-bit displacement (on all targets we support)
491 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
492 if (isInt<20>(C->getSExtValue()))
493 weight = CW_Constant;
496 case 'M': // 0x7fffffff
497 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
498 if (C->getZExtValue() == 0x7fffffff)
499 weight = CW_Constant;
505 // Parse a "{tNNN}" register constraint for which the register type "t"
506 // has already been verified. MC is the class associated with "t" and
507 // Map maps 0-based register numbers to LLVM register numbers.
508 static std::pair<unsigned, const TargetRegisterClass *>
509 parseRegisterNumber(const std::string &Constraint,
510 const TargetRegisterClass *RC, const unsigned *Map) {
511 assert(*(Constraint.end()-1) == '}' && "Missing '}'");
512 if (isdigit(Constraint[2])) {
513 std::string Suffix(Constraint.data() + 2, Constraint.size() - 2);
514 unsigned Index = atoi(Suffix.c_str());
515 if (Index < 16 && Map[Index])
516 return std::make_pair(Map[Index], RC);
518 return std::make_pair(0U, nullptr);
521 std::pair<unsigned, const TargetRegisterClass *>
522 SystemZTargetLowering::getRegForInlineAsmConstraint(
523 const TargetRegisterInfo *TRI, const std::string &Constraint,
525 if (Constraint.size() == 1) {
526 // GCC Constraint Letters
527 switch (Constraint[0]) {
529 case 'd': // Data register (equivalent to 'r')
530 case 'r': // General-purpose register
532 return std::make_pair(0U, &SystemZ::GR64BitRegClass);
533 else if (VT == MVT::i128)
534 return std::make_pair(0U, &SystemZ::GR128BitRegClass);
535 return std::make_pair(0U, &SystemZ::GR32BitRegClass);
537 case 'a': // Address register
539 return std::make_pair(0U, &SystemZ::ADDR64BitRegClass);
540 else if (VT == MVT::i128)
541 return std::make_pair(0U, &SystemZ::ADDR128BitRegClass);
542 return std::make_pair(0U, &SystemZ::ADDR32BitRegClass);
544 case 'h': // High-part register (an LLVM extension)
545 return std::make_pair(0U, &SystemZ::GRH32BitRegClass);
547 case 'f': // Floating-point register
549 return std::make_pair(0U, &SystemZ::FP64BitRegClass);
550 else if (VT == MVT::f128)
551 return std::make_pair(0U, &SystemZ::FP128BitRegClass);
552 return std::make_pair(0U, &SystemZ::FP32BitRegClass);
555 if (Constraint[0] == '{') {
556 // We need to override the default register parsing for GPRs and FPRs
557 // because the interpretation depends on VT. The internal names of
558 // the registers are also different from the external names
559 // (F0D and F0S instead of F0, etc.).
560 if (Constraint[1] == 'r') {
562 return parseRegisterNumber(Constraint, &SystemZ::GR32BitRegClass,
563 SystemZMC::GR32Regs);
565 return parseRegisterNumber(Constraint, &SystemZ::GR128BitRegClass,
566 SystemZMC::GR128Regs);
567 return parseRegisterNumber(Constraint, &SystemZ::GR64BitRegClass,
568 SystemZMC::GR64Regs);
570 if (Constraint[1] == 'f') {
572 return parseRegisterNumber(Constraint, &SystemZ::FP32BitRegClass,
573 SystemZMC::FP32Regs);
575 return parseRegisterNumber(Constraint, &SystemZ::FP128BitRegClass,
576 SystemZMC::FP128Regs);
577 return parseRegisterNumber(Constraint, &SystemZ::FP64BitRegClass,
578 SystemZMC::FP64Regs);
581 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
584 void SystemZTargetLowering::
585 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
586 std::vector<SDValue> &Ops,
587 SelectionDAG &DAG) const {
588 // Only support length 1 constraints for now.
589 if (Constraint.length() == 1) {
590 switch (Constraint[0]) {
591 case 'I': // Unsigned 8-bit constant
592 if (auto *C = dyn_cast<ConstantSDNode>(Op))
593 if (isUInt<8>(C->getZExtValue()))
594 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
598 case 'J': // Unsigned 12-bit constant
599 if (auto *C = dyn_cast<ConstantSDNode>(Op))
600 if (isUInt<12>(C->getZExtValue()))
601 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
605 case 'K': // Signed 16-bit constant
606 if (auto *C = dyn_cast<ConstantSDNode>(Op))
607 if (isInt<16>(C->getSExtValue()))
608 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
612 case 'L': // Signed 20-bit displacement (on all targets we support)
613 if (auto *C = dyn_cast<ConstantSDNode>(Op))
614 if (isInt<20>(C->getSExtValue()))
615 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
619 case 'M': // 0x7fffffff
620 if (auto *C = dyn_cast<ConstantSDNode>(Op))
621 if (C->getZExtValue() == 0x7fffffff)
622 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
627 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
630 //===----------------------------------------------------------------------===//
631 // Calling conventions
632 //===----------------------------------------------------------------------===//
634 #include "SystemZGenCallingConv.inc"
636 bool SystemZTargetLowering::allowTruncateForTailCall(Type *FromType,
637 Type *ToType) const {
638 return isTruncateFree(FromType, ToType);
641 bool SystemZTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
642 if (!CI->isTailCall())
647 // Value is a value that has been passed to us in the location described by VA
648 // (and so has type VA.getLocVT()). Convert Value to VA.getValVT(), chaining
649 // any loads onto Chain.
650 static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDLoc DL,
651 CCValAssign &VA, SDValue Chain,
653 // If the argument has been promoted from a smaller type, insert an
654 // assertion to capture this.
655 if (VA.getLocInfo() == CCValAssign::SExt)
656 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value,
657 DAG.getValueType(VA.getValVT()));
658 else if (VA.getLocInfo() == CCValAssign::ZExt)
659 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value,
660 DAG.getValueType(VA.getValVT()));
663 Value = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Value);
664 else if (VA.getLocInfo() == CCValAssign::Indirect)
665 Value = DAG.getLoad(VA.getValVT(), DL, Chain, Value,
666 MachinePointerInfo(), false, false, false, 0);
668 assert(VA.getLocInfo() == CCValAssign::Full && "Unsupported getLocInfo");
672 // Value is a value of type VA.getValVT() that we need to copy into
673 // the location described by VA. Return a copy of Value converted to
674 // VA.getValVT(). The caller is responsible for handling indirect values.
675 static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDLoc DL,
676 CCValAssign &VA, SDValue Value) {
677 switch (VA.getLocInfo()) {
678 case CCValAssign::SExt:
679 return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value);
680 case CCValAssign::ZExt:
681 return DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Value);
682 case CCValAssign::AExt:
683 return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value);
684 case CCValAssign::Full:
687 llvm_unreachable("Unhandled getLocInfo()");
691 SDValue SystemZTargetLowering::
692 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
693 const SmallVectorImpl<ISD::InputArg> &Ins,
694 SDLoc DL, SelectionDAG &DAG,
695 SmallVectorImpl<SDValue> &InVals) const {
696 MachineFunction &MF = DAG.getMachineFunction();
697 MachineFrameInfo *MFI = MF.getFrameInfo();
698 MachineRegisterInfo &MRI = MF.getRegInfo();
699 SystemZMachineFunctionInfo *FuncInfo =
700 MF.getInfo<SystemZMachineFunctionInfo>();
702 static_cast<const SystemZFrameLowering *>(Subtarget.getFrameLowering());
704 // Assign locations to all of the incoming arguments.
705 SmallVector<CCValAssign, 16> ArgLocs;
706 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
707 CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ);
709 unsigned NumFixedGPRs = 0;
710 unsigned NumFixedFPRs = 0;
711 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
713 CCValAssign &VA = ArgLocs[I];
714 EVT LocVT = VA.getLocVT();
716 // Arguments passed in registers
717 const TargetRegisterClass *RC;
718 switch (LocVT.getSimpleVT().SimpleTy) {
720 // Integers smaller than i64 should be promoted to i64.
721 llvm_unreachable("Unexpected argument type");
724 RC = &SystemZ::GR32BitRegClass;
728 RC = &SystemZ::GR64BitRegClass;
732 RC = &SystemZ::FP32BitRegClass;
736 RC = &SystemZ::FP64BitRegClass;
740 unsigned VReg = MRI.createVirtualRegister(RC);
741 MRI.addLiveIn(VA.getLocReg(), VReg);
742 ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
744 assert(VA.isMemLoc() && "Argument not register or memory");
746 // Create the frame index object for this incoming parameter.
747 int FI = MFI->CreateFixedObject(LocVT.getSizeInBits() / 8,
748 VA.getLocMemOffset(), true);
750 // Create the SelectionDAG nodes corresponding to a load
751 // from this parameter. Unpromoted ints and floats are
752 // passed as right-justified 8-byte values.
753 EVT PtrVT = getPointerTy();
754 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
755 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
756 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4));
757 ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN,
758 MachinePointerInfo::getFixedStack(FI),
759 false, false, false, 0);
762 // Convert the value of the argument register into the value that's
764 InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, ArgValue));
768 // Save the number of non-varargs registers for later use by va_start, etc.
769 FuncInfo->setVarArgsFirstGPR(NumFixedGPRs);
770 FuncInfo->setVarArgsFirstFPR(NumFixedFPRs);
772 // Likewise the address (in the form of a frame index) of where the
773 // first stack vararg would be. The 1-byte size here is arbitrary.
774 int64_t StackSize = CCInfo.getNextStackOffset();
775 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize, true));
777 // ...and a similar frame index for the caller-allocated save area
778 // that will be used to store the incoming registers.
779 int64_t RegSaveOffset = TFL->getOffsetOfLocalArea();
780 unsigned RegSaveIndex = MFI->CreateFixedObject(1, RegSaveOffset, true);
781 FuncInfo->setRegSaveFrameIndex(RegSaveIndex);
783 // Store the FPR varargs in the reserved frame slots. (We store the
784 // GPRs as part of the prologue.)
785 if (NumFixedFPRs < SystemZ::NumArgFPRs) {
786 SDValue MemOps[SystemZ::NumArgFPRs];
787 for (unsigned I = NumFixedFPRs; I < SystemZ::NumArgFPRs; ++I) {
788 unsigned Offset = TFL->getRegSpillOffset(SystemZ::ArgFPRs[I]);
789 int FI = MFI->CreateFixedObject(8, RegSaveOffset + Offset, true);
790 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
791 unsigned VReg = MF.addLiveIn(SystemZ::ArgFPRs[I],
792 &SystemZ::FP64BitRegClass);
793 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f64);
794 MemOps[I] = DAG.getStore(ArgValue.getValue(1), DL, ArgValue, FIN,
795 MachinePointerInfo::getFixedStack(FI),
799 // Join the stores, which are independent of one another.
800 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
801 makeArrayRef(&MemOps[NumFixedFPRs],
802 SystemZ::NumArgFPRs-NumFixedFPRs));
809 static bool canUseSiblingCall(const CCState &ArgCCInfo,
810 SmallVectorImpl<CCValAssign> &ArgLocs) {
811 // Punt if there are any indirect or stack arguments, or if the call
812 // needs the call-saved argument register R6.
813 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
814 CCValAssign &VA = ArgLocs[I];
815 if (VA.getLocInfo() == CCValAssign::Indirect)
819 unsigned Reg = VA.getLocReg();
820 if (Reg == SystemZ::R6H || Reg == SystemZ::R6L || Reg == SystemZ::R6D)
827 SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
828 SmallVectorImpl<SDValue> &InVals) const {
829 SelectionDAG &DAG = CLI.DAG;
831 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
832 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
833 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
834 SDValue Chain = CLI.Chain;
835 SDValue Callee = CLI.Callee;
836 bool &IsTailCall = CLI.IsTailCall;
837 CallingConv::ID CallConv = CLI.CallConv;
838 bool IsVarArg = CLI.IsVarArg;
839 MachineFunction &MF = DAG.getMachineFunction();
840 EVT PtrVT = getPointerTy();
842 // Analyze the operands of the call, assigning locations to each operand.
843 SmallVector<CCValAssign, 16> ArgLocs;
844 CCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
845 ArgCCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
847 // We don't support GuaranteedTailCallOpt, only automatically-detected
849 if (IsTailCall && !canUseSiblingCall(ArgCCInfo, ArgLocs))
852 // Get a count of how many bytes are to be pushed on the stack.
853 unsigned NumBytes = ArgCCInfo.getNextStackOffset();
855 // Mark the start of the call.
857 Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes, PtrVT, true),
860 // Copy argument values to their designated locations.
861 SmallVector<std::pair<unsigned, SDValue>, 9> RegsToPass;
862 SmallVector<SDValue, 8> MemOpChains;
864 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
865 CCValAssign &VA = ArgLocs[I];
866 SDValue ArgValue = OutVals[I];
868 if (VA.getLocInfo() == CCValAssign::Indirect) {
869 // Store the argument in a stack slot and pass its address.
870 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
871 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
872 MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, SpillSlot,
873 MachinePointerInfo::getFixedStack(FI),
875 ArgValue = SpillSlot;
877 ArgValue = convertValVTToLocVT(DAG, DL, VA, ArgValue);
880 // Queue up the argument copies and emit them at the end.
881 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));
883 assert(VA.isMemLoc() && "Argument not register or memory");
885 // Work out the address of the stack slot. Unpromoted ints and
886 // floats are passed as right-justified 8-byte values.
887 if (!StackPtr.getNode())
888 StackPtr = DAG.getCopyFromReg(Chain, DL, SystemZ::R15D, PtrVT);
889 unsigned Offset = SystemZMC::CallFrameSize + VA.getLocMemOffset();
890 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
892 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
893 DAG.getIntPtrConstant(Offset));
896 MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, Address,
897 MachinePointerInfo(),
902 // Join the stores, which are independent of one another.
903 if (!MemOpChains.empty())
904 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
906 // Accept direct calls by converting symbolic call addresses to the
907 // associated Target* opcodes. Force %r1 to be used for indirect
910 if (auto *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
911 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT);
912 Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
913 } else if (auto *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
914 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT);
915 Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
916 } else if (IsTailCall) {
917 Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R1D, Callee, Glue);
918 Glue = Chain.getValue(1);
919 Callee = DAG.getRegister(SystemZ::R1D, Callee.getValueType());
922 // Build a sequence of copy-to-reg nodes, chained and glued together.
923 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {
924 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
925 RegsToPass[I].second, Glue);
926 Glue = Chain.getValue(1);
929 // The first call operand is the chain and the second is the target address.
930 SmallVector<SDValue, 8> Ops;
931 Ops.push_back(Chain);
932 Ops.push_back(Callee);
934 // Add argument registers to the end of the list so that they are
935 // known live into the call.
936 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I)
937 Ops.push_back(DAG.getRegister(RegsToPass[I].first,
938 RegsToPass[I].second.getValueType()));
940 // Add a register mask operand representing the call-preserved registers.
941 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
942 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
943 assert(Mask && "Missing call preserved mask for calling convention");
944 Ops.push_back(DAG.getRegisterMask(Mask));
946 // Glue the call to the argument copies, if any.
951 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
953 return DAG.getNode(SystemZISD::SIBCALL, DL, NodeTys, Ops);
954 Chain = DAG.getNode(SystemZISD::CALL, DL, NodeTys, Ops);
955 Glue = Chain.getValue(1);
957 // Mark the end of the call, which is glued to the call itself.
958 Chain = DAG.getCALLSEQ_END(Chain,
959 DAG.getConstant(NumBytes, PtrVT, true),
960 DAG.getConstant(0, PtrVT, true),
962 Glue = Chain.getValue(1);
964 // Assign locations to each value returned by this call.
965 SmallVector<CCValAssign, 16> RetLocs;
966 CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, *DAG.getContext());
967 RetCCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ);
969 // Copy all of the result registers out of their specified physreg.
970 for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
971 CCValAssign &VA = RetLocs[I];
973 // Copy the value out, gluing the copy to the end of the call sequence.
974 SDValue RetValue = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(),
975 VA.getLocVT(), Glue);
976 Chain = RetValue.getValue(1);
977 Glue = RetValue.getValue(2);
979 // Convert the value of the return register into the value that's
981 InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, RetValue));
988 SystemZTargetLowering::LowerReturn(SDValue Chain,
989 CallingConv::ID CallConv, bool IsVarArg,
990 const SmallVectorImpl<ISD::OutputArg> &Outs,
991 const SmallVectorImpl<SDValue> &OutVals,
992 SDLoc DL, SelectionDAG &DAG) const {
993 MachineFunction &MF = DAG.getMachineFunction();
995 // Assign locations to each returned value.
996 SmallVector<CCValAssign, 16> RetLocs;
997 CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, *DAG.getContext());
998 RetCCInfo.AnalyzeReturn(Outs, RetCC_SystemZ);
1000 // Quick exit for void returns
1001 if (RetLocs.empty())
1002 return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, Chain);
1004 // Copy the result values into the output registers.
1006 SmallVector<SDValue, 4> RetOps;
1007 RetOps.push_back(Chain);
1008 for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
1009 CCValAssign &VA = RetLocs[I];
1010 SDValue RetValue = OutVals[I];
1012 // Make the return register live on exit.
1013 assert(VA.isRegLoc() && "Can only return in registers!");
1015 // Promote the value as required.
1016 RetValue = convertValVTToLocVT(DAG, DL, VA, RetValue);
1018 // Chain and glue the copies together.
1019 unsigned Reg = VA.getLocReg();
1020 Chain = DAG.getCopyToReg(Chain, DL, Reg, RetValue, Glue);
1021 Glue = Chain.getValue(1);
1022 RetOps.push_back(DAG.getRegister(Reg, VA.getLocVT()));
1025 // Update chain and glue.
1028 RetOps.push_back(Glue);
1030 return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, RetOps);
1033 SDValue SystemZTargetLowering::
1034 prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL, SelectionDAG &DAG) const {
1035 return DAG.getNode(SystemZISD::SERIALIZE, DL, MVT::Other, Chain);
1038 // Return true if Op is an intrinsic node with chain that returns the CC value
1039 // as its only (other) argument. Provide the associated SystemZISD opcode and
1040 // the mask of valid CC values if so.
1041 static bool isIntrinsicWithCCAndChain(SDValue Op, unsigned &Opcode,
1042 unsigned &CCValid) {
1043 unsigned Id = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1045 case Intrinsic::s390_tbegin:
1046 Opcode = SystemZISD::TBEGIN;
1047 CCValid = SystemZ::CCMASK_TBEGIN;
1050 case Intrinsic::s390_tbegin_nofloat:
1051 Opcode = SystemZISD::TBEGIN_NOFLOAT;
1052 CCValid = SystemZ::CCMASK_TBEGIN;
1055 case Intrinsic::s390_tend:
1056 Opcode = SystemZISD::TEND;
1057 CCValid = SystemZ::CCMASK_TEND;
1065 // Emit an intrinsic with chain with a glued value instead of its CC result.
1066 static SDValue emitIntrinsicWithChainAndGlue(SelectionDAG &DAG, SDValue Op,
1068 // Copy all operands except the intrinsic ID.
1069 unsigned NumOps = Op.getNumOperands();
1070 SmallVector<SDValue, 6> Ops;
1071 Ops.reserve(NumOps - 1);
1072 Ops.push_back(Op.getOperand(0));
1073 for (unsigned I = 2; I < NumOps; ++I)
1074 Ops.push_back(Op.getOperand(I));
1076 assert(Op->getNumValues() == 2 && "Expected only CC result and chain");
1077 SDVTList RawVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1078 SDValue Intr = DAG.getNode(Opcode, SDLoc(Op), RawVTs, Ops);
1079 SDValue OldChain = SDValue(Op.getNode(), 1);
1080 SDValue NewChain = SDValue(Intr.getNode(), 0);
1081 DAG.ReplaceAllUsesOfValueWith(OldChain, NewChain);
1085 // CC is a comparison that will be implemented using an integer or
1086 // floating-point comparison. Return the condition code mask for
1087 // a branch on true. In the integer case, CCMASK_CMP_UO is set for
1088 // unsigned comparisons and clear for signed ones. In the floating-point
1089 // case, CCMASK_CMP_UO has its normal mask meaning (unordered).
1090 static unsigned CCMaskForCondCode(ISD::CondCode CC) {
1092 case ISD::SET##X: return SystemZ::CCMASK_CMP_##X; \
1093 case ISD::SETO##X: return SystemZ::CCMASK_CMP_##X; \
1094 case ISD::SETU##X: return SystemZ::CCMASK_CMP_UO | SystemZ::CCMASK_CMP_##X
1098 llvm_unreachable("Invalid integer condition!");
1107 case ISD::SETO: return SystemZ::CCMASK_CMP_O;
1108 case ISD::SETUO: return SystemZ::CCMASK_CMP_UO;
1113 // Return a sequence for getting a 1 from an IPM result when CC has a
1114 // value in CCMask and a 0 when CC has a value in CCValid & ~CCMask.
1115 // The handling of CC values outside CCValid doesn't matter.
1116 static IPMConversion getIPMConversion(unsigned CCValid, unsigned CCMask) {
1117 // Deal with cases where the result can be taken directly from a bit
1118 // of the IPM result.
1119 if (CCMask == (CCValid & (SystemZ::CCMASK_1 | SystemZ::CCMASK_3)))
1120 return IPMConversion(0, 0, SystemZ::IPM_CC);
1121 if (CCMask == (CCValid & (SystemZ::CCMASK_2 | SystemZ::CCMASK_3)))
1122 return IPMConversion(0, 0, SystemZ::IPM_CC + 1);
1124 // Deal with cases where we can add a value to force the sign bit
1125 // to contain the right value. Putting the bit in 31 means we can
1126 // use SRL rather than RISBG(L), and also makes it easier to get a
1127 // 0/-1 value, so it has priority over the other tests below.
1129 // These sequences rely on the fact that the upper two bits of the
1130 // IPM result are zero.
1131 uint64_t TopBit = uint64_t(1) << 31;
1132 if (CCMask == (CCValid & SystemZ::CCMASK_0))
1133 return IPMConversion(0, -(1 << SystemZ::IPM_CC), 31);
1134 if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_1)))
1135 return IPMConversion(0, -(2 << SystemZ::IPM_CC), 31);
1136 if (CCMask == (CCValid & (SystemZ::CCMASK_0
1138 | SystemZ::CCMASK_2)))
1139 return IPMConversion(0, -(3 << SystemZ::IPM_CC), 31);
1140 if (CCMask == (CCValid & SystemZ::CCMASK_3))
1141 return IPMConversion(0, TopBit - (3 << SystemZ::IPM_CC), 31);
1142 if (CCMask == (CCValid & (SystemZ::CCMASK_1
1144 | SystemZ::CCMASK_3)))
1145 return IPMConversion(0, TopBit - (1 << SystemZ::IPM_CC), 31);
1147 // Next try inverting the value and testing a bit. 0/1 could be
1148 // handled this way too, but we dealt with that case above.
1149 if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_2)))
1150 return IPMConversion(-1, 0, SystemZ::IPM_CC);
1152 // Handle cases where adding a value forces a non-sign bit to contain
1154 if (CCMask == (CCValid & (SystemZ::CCMASK_1 | SystemZ::CCMASK_2)))
1155 return IPMConversion(0, 1 << SystemZ::IPM_CC, SystemZ::IPM_CC + 1);
1156 if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_3)))
1157 return IPMConversion(0, -(1 << SystemZ::IPM_CC), SystemZ::IPM_CC + 1);
1159 // The remaining cases are 1, 2, 0/1/3 and 0/2/3. All these are
1160 // can be done by inverting the low CC bit and applying one of the
1161 // sign-based extractions above.
1162 if (CCMask == (CCValid & SystemZ::CCMASK_1))
1163 return IPMConversion(1 << SystemZ::IPM_CC, -(1 << SystemZ::IPM_CC), 31);
1164 if (CCMask == (CCValid & SystemZ::CCMASK_2))
1165 return IPMConversion(1 << SystemZ::IPM_CC,
1166 TopBit - (3 << SystemZ::IPM_CC), 31);
1167 if (CCMask == (CCValid & (SystemZ::CCMASK_0
1169 | SystemZ::CCMASK_3)))
1170 return IPMConversion(1 << SystemZ::IPM_CC, -(3 << SystemZ::IPM_CC), 31);
1171 if (CCMask == (CCValid & (SystemZ::CCMASK_0
1173 | SystemZ::CCMASK_3)))
1174 return IPMConversion(1 << SystemZ::IPM_CC,
1175 TopBit - (1 << SystemZ::IPM_CC), 31);
1177 llvm_unreachable("Unexpected CC combination");
1180 // If C can be converted to a comparison against zero, adjust the operands
1182 static void adjustZeroCmp(SelectionDAG &DAG, Comparison &C) {
1183 if (C.ICmpType == SystemZICMP::UnsignedOnly)
1186 auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1.getNode());
1190 int64_t Value = ConstOp1->getSExtValue();
1191 if ((Value == -1 && C.CCMask == SystemZ::CCMASK_CMP_GT) ||
1192 (Value == -1 && C.CCMask == SystemZ::CCMASK_CMP_LE) ||
1193 (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_LT) ||
1194 (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_GE)) {
1195 C.CCMask ^= SystemZ::CCMASK_CMP_EQ;
1196 C.Op1 = DAG.getConstant(0, C.Op1.getValueType());
1200 // If a comparison described by C is suitable for CLI(Y), CHHSI or CLHHSI,
1201 // adjust the operands as necessary.
1202 static void adjustSubwordCmp(SelectionDAG &DAG, Comparison &C) {
1203 // For us to make any changes, it must a comparison between a single-use
1204 // load and a constant.
1205 if (!C.Op0.hasOneUse() ||
1206 C.Op0.getOpcode() != ISD::LOAD ||
1207 C.Op1.getOpcode() != ISD::Constant)
1210 // We must have an 8- or 16-bit load.
1211 auto *Load = cast<LoadSDNode>(C.Op0);
1212 unsigned NumBits = Load->getMemoryVT().getStoreSizeInBits();
1213 if (NumBits != 8 && NumBits != 16)
1216 // The load must be an extending one and the constant must be within the
1217 // range of the unextended value.
1218 auto *ConstOp1 = cast<ConstantSDNode>(C.Op1);
1219 uint64_t Value = ConstOp1->getZExtValue();
1220 uint64_t Mask = (1 << NumBits) - 1;
1221 if (Load->getExtensionType() == ISD::SEXTLOAD) {
1222 // Make sure that ConstOp1 is in range of C.Op0.
1223 int64_t SignedValue = ConstOp1->getSExtValue();
1224 if (uint64_t(SignedValue) + (uint64_t(1) << (NumBits - 1)) > Mask)
1226 if (C.ICmpType != SystemZICMP::SignedOnly) {
1227 // Unsigned comparison between two sign-extended values is equivalent
1228 // to unsigned comparison between two zero-extended values.
1230 } else if (NumBits == 8) {
1231 // Try to treat the comparison as unsigned, so that we can use CLI.
1232 // Adjust CCMask and Value as necessary.
1233 if (Value == 0 && C.CCMask == SystemZ::CCMASK_CMP_LT)
1234 // Test whether the high bit of the byte is set.
1235 Value = 127, C.CCMask = SystemZ::CCMASK_CMP_GT;
1236 else if (Value == 0 && C.CCMask == SystemZ::CCMASK_CMP_GE)
1237 // Test whether the high bit of the byte is clear.
1238 Value = 128, C.CCMask = SystemZ::CCMASK_CMP_LT;
1240 // No instruction exists for this combination.
1242 C.ICmpType = SystemZICMP::UnsignedOnly;
1244 } else if (Load->getExtensionType() == ISD::ZEXTLOAD) {
1247 assert(C.ICmpType == SystemZICMP::Any &&
1248 "Signedness shouldn't matter here.");
1252 // Make sure that the first operand is an i32 of the right extension type.
1253 ISD::LoadExtType ExtType = (C.ICmpType == SystemZICMP::SignedOnly ?
1256 if (C.Op0.getValueType() != MVT::i32 ||
1257 Load->getExtensionType() != ExtType)
1258 C.Op0 = DAG.getExtLoad(ExtType, SDLoc(Load), MVT::i32,
1259 Load->getChain(), Load->getBasePtr(),
1260 Load->getPointerInfo(), Load->getMemoryVT(),
1261 Load->isVolatile(), Load->isNonTemporal(),
1262 Load->isInvariant(), Load->getAlignment());
1264 // Make sure that the second operand is an i32 with the right value.
1265 if (C.Op1.getValueType() != MVT::i32 ||
1266 Value != ConstOp1->getZExtValue())
1267 C.Op1 = DAG.getConstant(Value, MVT::i32);
1270 // Return true if Op is either an unextended load, or a load suitable
1271 // for integer register-memory comparisons of type ICmpType.
1272 static bool isNaturalMemoryOperand(SDValue Op, unsigned ICmpType) {
1273 auto *Load = dyn_cast<LoadSDNode>(Op.getNode());
1275 // There are no instructions to compare a register with a memory byte.
1276 if (Load->getMemoryVT() == MVT::i8)
1278 // Otherwise decide on extension type.
1279 switch (Load->getExtensionType()) {
1280 case ISD::NON_EXTLOAD:
1283 return ICmpType != SystemZICMP::UnsignedOnly;
1285 return ICmpType != SystemZICMP::SignedOnly;
1293 // Return true if it is better to swap the operands of C.
1294 static bool shouldSwapCmpOperands(const Comparison &C) {
1295 // Leave f128 comparisons alone, since they have no memory forms.
1296 if (C.Op0.getValueType() == MVT::f128)
1299 // Always keep a floating-point constant second, since comparisons with
1300 // zero can use LOAD TEST and comparisons with other constants make a
1301 // natural memory operand.
1302 if (isa<ConstantFPSDNode>(C.Op1))
1305 // Never swap comparisons with zero since there are many ways to optimize
1307 auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1);
1308 if (ConstOp1 && ConstOp1->getZExtValue() == 0)
1311 // Also keep natural memory operands second if the loaded value is
1312 // only used here. Several comparisons have memory forms.
1313 if (isNaturalMemoryOperand(C.Op1, C.ICmpType) && C.Op1.hasOneUse())
1316 // Look for cases where Cmp0 is a single-use load and Cmp1 isn't.
1317 // In that case we generally prefer the memory to be second.
1318 if (isNaturalMemoryOperand(C.Op0, C.ICmpType) && C.Op0.hasOneUse()) {
1319 // The only exceptions are when the second operand is a constant and
1320 // we can use things like CHHSI.
1323 // The unsigned memory-immediate instructions can handle 16-bit
1324 // unsigned integers.
1325 if (C.ICmpType != SystemZICMP::SignedOnly &&
1326 isUInt<16>(ConstOp1->getZExtValue()))
1328 // The signed memory-immediate instructions can handle 16-bit
1330 if (C.ICmpType != SystemZICMP::UnsignedOnly &&
1331 isInt<16>(ConstOp1->getSExtValue()))
1336 // Try to promote the use of CGFR and CLGFR.
1337 unsigned Opcode0 = C.Op0.getOpcode();
1338 if (C.ICmpType != SystemZICMP::UnsignedOnly && Opcode0 == ISD::SIGN_EXTEND)
1340 if (C.ICmpType != SystemZICMP::SignedOnly && Opcode0 == ISD::ZERO_EXTEND)
1342 if (C.ICmpType != SystemZICMP::SignedOnly &&
1343 Opcode0 == ISD::AND &&
1344 C.Op0.getOperand(1).getOpcode() == ISD::Constant &&
1345 cast<ConstantSDNode>(C.Op0.getOperand(1))->getZExtValue() == 0xffffffff)
1351 // Return a version of comparison CC mask CCMask in which the LT and GT
1352 // actions are swapped.
1353 static unsigned reverseCCMask(unsigned CCMask) {
1354 return ((CCMask & SystemZ::CCMASK_CMP_EQ) |
1355 (CCMask & SystemZ::CCMASK_CMP_GT ? SystemZ::CCMASK_CMP_LT : 0) |
1356 (CCMask & SystemZ::CCMASK_CMP_LT ? SystemZ::CCMASK_CMP_GT : 0) |
1357 (CCMask & SystemZ::CCMASK_CMP_UO));
1360 // Check whether C tests for equality between X and Y and whether X - Y
1361 // or Y - X is also computed. In that case it's better to compare the
1362 // result of the subtraction against zero.
1363 static void adjustForSubtraction(SelectionDAG &DAG, Comparison &C) {
1364 if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
1365 C.CCMask == SystemZ::CCMASK_CMP_NE) {
1366 for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
1368 if (N->getOpcode() == ISD::SUB &&
1369 ((N->getOperand(0) == C.Op0 && N->getOperand(1) == C.Op1) ||
1370 (N->getOperand(0) == C.Op1 && N->getOperand(1) == C.Op0))) {
1371 C.Op0 = SDValue(N, 0);
1372 C.Op1 = DAG.getConstant(0, N->getValueType(0));
1379 // Check whether C compares a floating-point value with zero and if that
1380 // floating-point value is also negated. In this case we can use the
1381 // negation to set CC, so avoiding separate LOAD AND TEST and
1382 // LOAD (NEGATIVE/COMPLEMENT) instructions.
1383 static void adjustForFNeg(Comparison &C) {
1384 auto *C1 = dyn_cast<ConstantFPSDNode>(C.Op1);
1385 if (C1 && C1->isZero()) {
1386 for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
1388 if (N->getOpcode() == ISD::FNEG) {
1389 C.Op0 = SDValue(N, 0);
1390 C.CCMask = reverseCCMask(C.CCMask);
1397 // Check whether C compares (shl X, 32) with 0 and whether X is
1398 // also sign-extended. In that case it is better to test the result
1399 // of the sign extension using LTGFR.
1401 // This case is important because InstCombine transforms a comparison
1402 // with (sext (trunc X)) into a comparison with (shl X, 32).
1403 static void adjustForLTGFR(Comparison &C) {
1404 // Check for a comparison between (shl X, 32) and 0.
1405 if (C.Op0.getOpcode() == ISD::SHL &&
1406 C.Op0.getValueType() == MVT::i64 &&
1407 C.Op1.getOpcode() == ISD::Constant &&
1408 cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
1409 auto *C1 = dyn_cast<ConstantSDNode>(C.Op0.getOperand(1));
1410 if (C1 && C1->getZExtValue() == 32) {
1411 SDValue ShlOp0 = C.Op0.getOperand(0);
1412 // See whether X has any SIGN_EXTEND_INREG uses.
1413 for (auto I = ShlOp0->use_begin(), E = ShlOp0->use_end(); I != E; ++I) {
1415 if (N->getOpcode() == ISD::SIGN_EXTEND_INREG &&
1416 cast<VTSDNode>(N->getOperand(1))->getVT() == MVT::i32) {
1417 C.Op0 = SDValue(N, 0);
1425 // If C compares the truncation of an extending load, try to compare
1426 // the untruncated value instead. This exposes more opportunities to
1428 static void adjustICmpTruncate(SelectionDAG &DAG, Comparison &C) {
1429 if (C.Op0.getOpcode() == ISD::TRUNCATE &&
1430 C.Op0.getOperand(0).getOpcode() == ISD::LOAD &&
1431 C.Op1.getOpcode() == ISD::Constant &&
1432 cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
1433 auto *L = cast<LoadSDNode>(C.Op0.getOperand(0));
1434 if (L->getMemoryVT().getStoreSizeInBits()
1435 <= C.Op0.getValueType().getSizeInBits()) {
1436 unsigned Type = L->getExtensionType();
1437 if ((Type == ISD::ZEXTLOAD && C.ICmpType != SystemZICMP::SignedOnly) ||
1438 (Type == ISD::SEXTLOAD && C.ICmpType != SystemZICMP::UnsignedOnly)) {
1439 C.Op0 = C.Op0.getOperand(0);
1440 C.Op1 = DAG.getConstant(0, C.Op0.getValueType());
1446 // Return true if shift operation N has an in-range constant shift value.
1447 // Store it in ShiftVal if so.
1448 static bool isSimpleShift(SDValue N, unsigned &ShiftVal) {
1449 auto *Shift = dyn_cast<ConstantSDNode>(N.getOperand(1));
1453 uint64_t Amount = Shift->getZExtValue();
1454 if (Amount >= N.getValueType().getSizeInBits())
1461 // Check whether an AND with Mask is suitable for a TEST UNDER MASK
1462 // instruction and whether the CC value is descriptive enough to handle
1463 // a comparison of type Opcode between the AND result and CmpVal.
1464 // CCMask says which comparison result is being tested and BitSize is
1465 // the number of bits in the operands. If TEST UNDER MASK can be used,
1466 // return the corresponding CC mask, otherwise return 0.
1467 static unsigned getTestUnderMaskCond(unsigned BitSize, unsigned CCMask,
1468 uint64_t Mask, uint64_t CmpVal,
1469 unsigned ICmpType) {
1470 assert(Mask != 0 && "ANDs with zero should have been removed by now");
1472 // Check whether the mask is suitable for TMHH, TMHL, TMLH or TMLL.
1473 if (!SystemZ::isImmLL(Mask) && !SystemZ::isImmLH(Mask) &&
1474 !SystemZ::isImmHL(Mask) && !SystemZ::isImmHH(Mask))
1477 // Work out the masks for the lowest and highest bits.
1478 unsigned HighShift = 63 - countLeadingZeros(Mask);
1479 uint64_t High = uint64_t(1) << HighShift;
1480 uint64_t Low = uint64_t(1) << countTrailingZeros(Mask);
1482 // Signed ordered comparisons are effectively unsigned if the sign
1484 bool EffectivelyUnsigned = (ICmpType != SystemZICMP::SignedOnly);
1486 // Check for equality comparisons with 0, or the equivalent.
1488 if (CCMask == SystemZ::CCMASK_CMP_EQ)
1489 return SystemZ::CCMASK_TM_ALL_0;
1490 if (CCMask == SystemZ::CCMASK_CMP_NE)
1491 return SystemZ::CCMASK_TM_SOME_1;
1493 if (EffectivelyUnsigned && CmpVal <= Low) {
1494 if (CCMask == SystemZ::CCMASK_CMP_LT)
1495 return SystemZ::CCMASK_TM_ALL_0;
1496 if (CCMask == SystemZ::CCMASK_CMP_GE)
1497 return SystemZ::CCMASK_TM_SOME_1;
1499 if (EffectivelyUnsigned && CmpVal < Low) {
1500 if (CCMask == SystemZ::CCMASK_CMP_LE)
1501 return SystemZ::CCMASK_TM_ALL_0;
1502 if (CCMask == SystemZ::CCMASK_CMP_GT)
1503 return SystemZ::CCMASK_TM_SOME_1;
1506 // Check for equality comparisons with the mask, or the equivalent.
1507 if (CmpVal == Mask) {
1508 if (CCMask == SystemZ::CCMASK_CMP_EQ)
1509 return SystemZ::CCMASK_TM_ALL_1;
1510 if (CCMask == SystemZ::CCMASK_CMP_NE)
1511 return SystemZ::CCMASK_TM_SOME_0;
1513 if (EffectivelyUnsigned && CmpVal >= Mask - Low && CmpVal < Mask) {
1514 if (CCMask == SystemZ::CCMASK_CMP_GT)
1515 return SystemZ::CCMASK_TM_ALL_1;
1516 if (CCMask == SystemZ::CCMASK_CMP_LE)
1517 return SystemZ::CCMASK_TM_SOME_0;
1519 if (EffectivelyUnsigned && CmpVal > Mask - Low && CmpVal <= Mask) {
1520 if (CCMask == SystemZ::CCMASK_CMP_GE)
1521 return SystemZ::CCMASK_TM_ALL_1;
1522 if (CCMask == SystemZ::CCMASK_CMP_LT)
1523 return SystemZ::CCMASK_TM_SOME_0;
1526 // Check for ordered comparisons with the top bit.
1527 if (EffectivelyUnsigned && CmpVal >= Mask - High && CmpVal < High) {
1528 if (CCMask == SystemZ::CCMASK_CMP_LE)
1529 return SystemZ::CCMASK_TM_MSB_0;
1530 if (CCMask == SystemZ::CCMASK_CMP_GT)
1531 return SystemZ::CCMASK_TM_MSB_1;
1533 if (EffectivelyUnsigned && CmpVal > Mask - High && CmpVal <= High) {
1534 if (CCMask == SystemZ::CCMASK_CMP_LT)
1535 return SystemZ::CCMASK_TM_MSB_0;
1536 if (CCMask == SystemZ::CCMASK_CMP_GE)
1537 return SystemZ::CCMASK_TM_MSB_1;
1540 // If there are just two bits, we can do equality checks for Low and High
1542 if (Mask == Low + High) {
1543 if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == Low)
1544 return SystemZ::CCMASK_TM_MIXED_MSB_0;
1545 if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == Low)
1546 return SystemZ::CCMASK_TM_MIXED_MSB_0 ^ SystemZ::CCMASK_ANY;
1547 if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == High)
1548 return SystemZ::CCMASK_TM_MIXED_MSB_1;
1549 if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == High)
1550 return SystemZ::CCMASK_TM_MIXED_MSB_1 ^ SystemZ::CCMASK_ANY;
1553 // Looks like we've exhausted our options.
1557 // See whether C can be implemented as a TEST UNDER MASK instruction.
1558 // Update the arguments with the TM version if so.
1559 static void adjustForTestUnderMask(SelectionDAG &DAG, Comparison &C) {
1560 // Check that we have a comparison with a constant.
1561 auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1);
1564 uint64_t CmpVal = ConstOp1->getZExtValue();
1566 // Check whether the nonconstant input is an AND with a constant mask.
1569 ConstantSDNode *Mask = nullptr;
1570 if (C.Op0.getOpcode() == ISD::AND) {
1571 NewC.Op0 = C.Op0.getOperand(0);
1572 NewC.Op1 = C.Op0.getOperand(1);
1573 Mask = dyn_cast<ConstantSDNode>(NewC.Op1);
1576 MaskVal = Mask->getZExtValue();
1578 // There is no instruction to compare with a 64-bit immediate
1579 // so use TMHH instead if possible. We need an unsigned ordered
1580 // comparison with an i64 immediate.
1581 if (NewC.Op0.getValueType() != MVT::i64 ||
1582 NewC.CCMask == SystemZ::CCMASK_CMP_EQ ||
1583 NewC.CCMask == SystemZ::CCMASK_CMP_NE ||
1584 NewC.ICmpType == SystemZICMP::SignedOnly)
1586 // Convert LE and GT comparisons into LT and GE.
1587 if (NewC.CCMask == SystemZ::CCMASK_CMP_LE ||
1588 NewC.CCMask == SystemZ::CCMASK_CMP_GT) {
1589 if (CmpVal == uint64_t(-1))
1592 NewC.CCMask ^= SystemZ::CCMASK_CMP_EQ;
1594 // If the low N bits of Op1 are zero than the low N bits of Op0 can
1595 // be masked off without changing the result.
1596 MaskVal = -(CmpVal & -CmpVal);
1597 NewC.ICmpType = SystemZICMP::UnsignedOnly;
1602 // Check whether the combination of mask, comparison value and comparison
1603 // type are suitable.
1604 unsigned BitSize = NewC.Op0.getValueType().getSizeInBits();
1605 unsigned NewCCMask, ShiftVal;
1606 if (NewC.ICmpType != SystemZICMP::SignedOnly &&
1607 NewC.Op0.getOpcode() == ISD::SHL &&
1608 isSimpleShift(NewC.Op0, ShiftVal) &&
1609 (NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask,
1610 MaskVal >> ShiftVal,
1612 SystemZICMP::Any))) {
1613 NewC.Op0 = NewC.Op0.getOperand(0);
1614 MaskVal >>= ShiftVal;
1615 } else if (NewC.ICmpType != SystemZICMP::SignedOnly &&
1616 NewC.Op0.getOpcode() == ISD::SRL &&
1617 isSimpleShift(NewC.Op0, ShiftVal) &&
1618 (NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask,
1619 MaskVal << ShiftVal,
1621 SystemZICMP::UnsignedOnly))) {
1622 NewC.Op0 = NewC.Op0.getOperand(0);
1623 MaskVal <<= ShiftVal;
1625 NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask, MaskVal, CmpVal,
1631 // Go ahead and make the change.
1632 C.Opcode = SystemZISD::TM;
1634 if (Mask && Mask->getZExtValue() == MaskVal)
1635 C.Op1 = SDValue(Mask, 0);
1637 C.Op1 = DAG.getConstant(MaskVal, C.Op0.getValueType());
1638 C.CCValid = SystemZ::CCMASK_TM;
1639 C.CCMask = NewCCMask;
1642 // Return a Comparison that tests the condition-code result of intrinsic
1643 // node Call against constant integer CC using comparison code Cond.
1644 // Opcode is the opcode of the SystemZISD operation for the intrinsic
1645 // and CCValid is the set of possible condition-code results.
1646 static Comparison getIntrinsicCmp(SelectionDAG &DAG, unsigned Opcode,
1647 SDValue Call, unsigned CCValid, uint64_t CC,
1648 ISD::CondCode Cond) {
1649 Comparison C(Call, SDValue());
1651 C.CCValid = CCValid;
1652 if (Cond == ISD::SETEQ)
1653 // bit 3 for CC==0, bit 0 for CC==3, always false for CC>3.
1654 C.CCMask = CC < 4 ? 1 << (3 - CC) : 0;
1655 else if (Cond == ISD::SETNE)
1656 // ...and the inverse of that.
1657 C.CCMask = CC < 4 ? ~(1 << (3 - CC)) : -1;
1658 else if (Cond == ISD::SETLT || Cond == ISD::SETULT)
1659 // bits above bit 3 for CC==0 (always false), bits above bit 0 for CC==3,
1660 // always true for CC>3.
1661 C.CCMask = CC < 4 ? -1 << (4 - CC) : -1;
1662 else if (Cond == ISD::SETGE || Cond == ISD::SETUGE)
1663 // ...and the inverse of that.
1664 C.CCMask = CC < 4 ? ~(-1 << (4 - CC)) : 0;
1665 else if (Cond == ISD::SETLE || Cond == ISD::SETULE)
1666 // bit 3 and above for CC==0, bit 0 and above for CC==3 (always true),
1667 // always true for CC>3.
1668 C.CCMask = CC < 4 ? -1 << (3 - CC) : -1;
1669 else if (Cond == ISD::SETGT || Cond == ISD::SETUGT)
1670 // ...and the inverse of that.
1671 C.CCMask = CC < 4 ? ~(-1 << (3 - CC)) : 0;
1673 llvm_unreachable("Unexpected integer comparison type");
1674 C.CCMask &= CCValid;
1678 // Decide how to implement a comparison of type Cond between CmpOp0 with CmpOp1.
1679 static Comparison getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1,
1680 ISD::CondCode Cond) {
1681 if (CmpOp1.getOpcode() == ISD::Constant) {
1682 uint64_t Constant = cast<ConstantSDNode>(CmpOp1)->getZExtValue();
1683 unsigned Opcode, CCValid;
1684 if (CmpOp0.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
1685 CmpOp0.getResNo() == 0 && CmpOp0->hasNUsesOfValue(1, 0) &&
1686 isIntrinsicWithCCAndChain(CmpOp0, Opcode, CCValid))
1687 return getIntrinsicCmp(DAG, Opcode, CmpOp0, CCValid, Constant, Cond);
1689 Comparison C(CmpOp0, CmpOp1);
1690 C.CCMask = CCMaskForCondCode(Cond);
1691 if (C.Op0.getValueType().isFloatingPoint()) {
1692 C.CCValid = SystemZ::CCMASK_FCMP;
1693 C.Opcode = SystemZISD::FCMP;
1696 C.CCValid = SystemZ::CCMASK_ICMP;
1697 C.Opcode = SystemZISD::ICMP;
1698 // Choose the type of comparison. Equality and inequality tests can
1699 // use either signed or unsigned comparisons. The choice also doesn't
1700 // matter if both sign bits are known to be clear. In those cases we
1701 // want to give the main isel code the freedom to choose whichever
1703 if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
1704 C.CCMask == SystemZ::CCMASK_CMP_NE ||
1705 (DAG.SignBitIsZero(C.Op0) && DAG.SignBitIsZero(C.Op1)))
1706 C.ICmpType = SystemZICMP::Any;
1707 else if (C.CCMask & SystemZ::CCMASK_CMP_UO)
1708 C.ICmpType = SystemZICMP::UnsignedOnly;
1710 C.ICmpType = SystemZICMP::SignedOnly;
1711 C.CCMask &= ~SystemZ::CCMASK_CMP_UO;
1712 adjustZeroCmp(DAG, C);
1713 adjustSubwordCmp(DAG, C);
1714 adjustForSubtraction(DAG, C);
1716 adjustICmpTruncate(DAG, C);
1719 if (shouldSwapCmpOperands(C)) {
1720 std::swap(C.Op0, C.Op1);
1721 C.CCMask = reverseCCMask(C.CCMask);
1724 adjustForTestUnderMask(DAG, C);
1728 // Emit the comparison instruction described by C.
1729 static SDValue emitCmp(SelectionDAG &DAG, SDLoc DL, Comparison &C) {
1730 if (!C.Op1.getNode()) {
1732 switch (C.Op0.getOpcode()) {
1733 case ISD::INTRINSIC_W_CHAIN:
1734 Op = emitIntrinsicWithChainAndGlue(DAG, C.Op0, C.Opcode);
1737 llvm_unreachable("Invalid comparison operands");
1739 return SDValue(Op.getNode(), Op->getNumValues() - 1);
1741 if (C.Opcode == SystemZISD::ICMP)
1742 return DAG.getNode(SystemZISD::ICMP, DL, MVT::Glue, C.Op0, C.Op1,
1743 DAG.getConstant(C.ICmpType, MVT::i32));
1744 if (C.Opcode == SystemZISD::TM) {
1745 bool RegisterOnly = (bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_0) !=
1746 bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_1));
1747 return DAG.getNode(SystemZISD::TM, DL, MVT::Glue, C.Op0, C.Op1,
1748 DAG.getConstant(RegisterOnly, MVT::i32));
1750 return DAG.getNode(C.Opcode, DL, MVT::Glue, C.Op0, C.Op1);
1753 // Implement a 32-bit *MUL_LOHI operation by extending both operands to
1754 // 64 bits. Extend is the extension type to use. Store the high part
1755 // in Hi and the low part in Lo.
1756 static void lowerMUL_LOHI32(SelectionDAG &DAG, SDLoc DL,
1757 unsigned Extend, SDValue Op0, SDValue Op1,
1758 SDValue &Hi, SDValue &Lo) {
1759 Op0 = DAG.getNode(Extend, DL, MVT::i64, Op0);
1760 Op1 = DAG.getNode(Extend, DL, MVT::i64, Op1);
1761 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, Op0, Op1);
1762 Hi = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul, DAG.getConstant(32, MVT::i64));
1763 Hi = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Hi);
1764 Lo = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mul);
1767 // Lower a binary operation that produces two VT results, one in each
1768 // half of a GR128 pair. Op0 and Op1 are the VT operands to the operation,
1769 // Extend extends Op0 to a GR128, and Opcode performs the GR128 operation
1770 // on the extended Op0 and (unextended) Op1. Store the even register result
1771 // in Even and the odd register result in Odd.
1772 static void lowerGR128Binary(SelectionDAG &DAG, SDLoc DL, EVT VT,
1773 unsigned Extend, unsigned Opcode,
1774 SDValue Op0, SDValue Op1,
1775 SDValue &Even, SDValue &Odd) {
1776 SDNode *In128 = DAG.getMachineNode(Extend, DL, MVT::Untyped, Op0);
1777 SDValue Result = DAG.getNode(Opcode, DL, MVT::Untyped,
1778 SDValue(In128, 0), Op1);
1779 bool Is32Bit = is32Bit(VT);
1780 Even = DAG.getTargetExtractSubreg(SystemZ::even128(Is32Bit), DL, VT, Result);
1781 Odd = DAG.getTargetExtractSubreg(SystemZ::odd128(Is32Bit), DL, VT, Result);
1784 // Return an i32 value that is 1 if the CC value produced by Glue is
1785 // in the mask CCMask and 0 otherwise. CC is known to have a value
1786 // in CCValid, so other values can be ignored.
1787 static SDValue emitSETCC(SelectionDAG &DAG, SDLoc DL, SDValue Glue,
1788 unsigned CCValid, unsigned CCMask) {
1789 IPMConversion Conversion = getIPMConversion(CCValid, CCMask);
1790 SDValue Result = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, Glue);
1792 if (Conversion.XORValue)
1793 Result = DAG.getNode(ISD::XOR, DL, MVT::i32, Result,
1794 DAG.getConstant(Conversion.XORValue, MVT::i32));
1796 if (Conversion.AddValue)
1797 Result = DAG.getNode(ISD::ADD, DL, MVT::i32, Result,
1798 DAG.getConstant(Conversion.AddValue, MVT::i32));
1800 // The SHR/AND sequence should get optimized to an RISBG.
1801 Result = DAG.getNode(ISD::SRL, DL, MVT::i32, Result,
1802 DAG.getConstant(Conversion.Bit, MVT::i32));
1803 if (Conversion.Bit != 31)
1804 Result = DAG.getNode(ISD::AND, DL, MVT::i32, Result,
1805 DAG.getConstant(1, MVT::i32));
1809 SDValue SystemZTargetLowering::lowerSETCC(SDValue Op,
1810 SelectionDAG &DAG) const {
1811 SDValue CmpOp0 = Op.getOperand(0);
1812 SDValue CmpOp1 = Op.getOperand(1);
1813 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1816 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC));
1817 SDValue Glue = emitCmp(DAG, DL, C);
1818 return emitSETCC(DAG, DL, Glue, C.CCValid, C.CCMask);
1821 SDValue SystemZTargetLowering::lowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
1822 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1823 SDValue CmpOp0 = Op.getOperand(2);
1824 SDValue CmpOp1 = Op.getOperand(3);
1825 SDValue Dest = Op.getOperand(4);
1828 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC));
1829 SDValue Glue = emitCmp(DAG, DL, C);
1830 return DAG.getNode(SystemZISD::BR_CCMASK, DL, Op.getValueType(),
1831 Op.getOperand(0), DAG.getConstant(C.CCValid, MVT::i32),
1832 DAG.getConstant(C.CCMask, MVT::i32), Dest, Glue);
1835 // Return true if Pos is CmpOp and Neg is the negative of CmpOp,
1836 // allowing Pos and Neg to be wider than CmpOp.
1837 static bool isAbsolute(SDValue CmpOp, SDValue Pos, SDValue Neg) {
1838 return (Neg.getOpcode() == ISD::SUB &&
1839 Neg.getOperand(0).getOpcode() == ISD::Constant &&
1840 cast<ConstantSDNode>(Neg.getOperand(0))->getZExtValue() == 0 &&
1841 Neg.getOperand(1) == Pos &&
1843 (Pos.getOpcode() == ISD::SIGN_EXTEND &&
1844 Pos.getOperand(0) == CmpOp)));
1847 // Return the absolute or negative absolute of Op; IsNegative decides which.
1848 static SDValue getAbsolute(SelectionDAG &DAG, SDLoc DL, SDValue Op,
1850 Op = DAG.getNode(SystemZISD::IABS, DL, Op.getValueType(), Op);
1852 Op = DAG.getNode(ISD::SUB, DL, Op.getValueType(),
1853 DAG.getConstant(0, Op.getValueType()), Op);
1857 SDValue SystemZTargetLowering::lowerSELECT_CC(SDValue Op,
1858 SelectionDAG &DAG) const {
1859 SDValue CmpOp0 = Op.getOperand(0);
1860 SDValue CmpOp1 = Op.getOperand(1);
1861 SDValue TrueOp = Op.getOperand(2);
1862 SDValue FalseOp = Op.getOperand(3);
1863 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1866 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC));
1868 // Check for absolute and negative-absolute selections, including those
1869 // where the comparison value is sign-extended (for LPGFR and LNGFR).
1870 // This check supplements the one in DAGCombiner.
1871 if (C.Opcode == SystemZISD::ICMP &&
1872 C.CCMask != SystemZ::CCMASK_CMP_EQ &&
1873 C.CCMask != SystemZ::CCMASK_CMP_NE &&
1874 C.Op1.getOpcode() == ISD::Constant &&
1875 cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
1876 if (isAbsolute(C.Op0, TrueOp, FalseOp))
1877 return getAbsolute(DAG, DL, TrueOp, C.CCMask & SystemZ::CCMASK_CMP_LT);
1878 if (isAbsolute(C.Op0, FalseOp, TrueOp))
1879 return getAbsolute(DAG, DL, FalseOp, C.CCMask & SystemZ::CCMASK_CMP_GT);
1882 SDValue Glue = emitCmp(DAG, DL, C);
1884 // Special case for handling -1/0 results. The shifts we use here
1885 // should get optimized with the IPM conversion sequence.
1886 auto *TrueC = dyn_cast<ConstantSDNode>(TrueOp);
1887 auto *FalseC = dyn_cast<ConstantSDNode>(FalseOp);
1888 if (TrueC && FalseC) {
1889 int64_t TrueVal = TrueC->getSExtValue();
1890 int64_t FalseVal = FalseC->getSExtValue();
1891 if ((TrueVal == -1 && FalseVal == 0) || (TrueVal == 0 && FalseVal == -1)) {
1892 // Invert the condition if we want -1 on false.
1894 C.CCMask ^= C.CCValid;
1895 SDValue Result = emitSETCC(DAG, DL, Glue, C.CCValid, C.CCMask);
1896 EVT VT = Op.getValueType();
1897 // Extend the result to VT. Upper bits are ignored.
1899 Result = DAG.getNode(ISD::ANY_EXTEND, DL, VT, Result);
1900 // Sign-extend from the low bit.
1901 SDValue ShAmt = DAG.getConstant(VT.getSizeInBits() - 1, MVT::i32);
1902 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, Result, ShAmt);
1903 return DAG.getNode(ISD::SRA, DL, VT, Shl, ShAmt);
1907 SDValue Ops[] = {TrueOp, FalseOp, DAG.getConstant(C.CCValid, MVT::i32),
1908 DAG.getConstant(C.CCMask, MVT::i32), Glue};
1910 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1911 return DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VTs, Ops);
1914 SDValue SystemZTargetLowering::lowerGlobalAddress(GlobalAddressSDNode *Node,
1915 SelectionDAG &DAG) const {
1917 const GlobalValue *GV = Node->getGlobal();
1918 int64_t Offset = Node->getOffset();
1919 EVT PtrVT = getPointerTy();
1920 Reloc::Model RM = DAG.getTarget().getRelocationModel();
1921 CodeModel::Model CM = DAG.getTarget().getCodeModel();
1924 if (Subtarget.isPC32DBLSymbol(GV, RM, CM)) {
1925 // Assign anchors at 1<<12 byte boundaries.
1926 uint64_t Anchor = Offset & ~uint64_t(0xfff);
1927 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor);
1928 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1930 // The offset can be folded into the address if it is aligned to a halfword.
1932 if (Offset != 0 && (Offset & 1) == 0) {
1933 SDValue Full = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor + Offset);
1934 Result = DAG.getNode(SystemZISD::PCREL_OFFSET, DL, PtrVT, Full, Result);
1938 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, SystemZII::MO_GOT);
1939 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1940 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
1941 MachinePointerInfo::getGOT(), false, false, false, 0);
1944 // If there was a non-zero offset that we didn't fold, create an explicit
1947 Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result,
1948 DAG.getConstant(Offset, PtrVT));
1953 SDValue SystemZTargetLowering::lowerTLSGetOffset(GlobalAddressSDNode *Node,
1956 SDValue GOTOffset) const {
1958 EVT PtrVT = getPointerTy();
1959 SDValue Chain = DAG.getEntryNode();
1962 // __tls_get_offset takes the GOT offset in %r2 and the GOT in %r12.
1963 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1964 Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R12D, GOT, Glue);
1965 Glue = Chain.getValue(1);
1966 Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R2D, GOTOffset, Glue);
1967 Glue = Chain.getValue(1);
1969 // The first call operand is the chain and the second is the TLS symbol.
1970 SmallVector<SDValue, 8> Ops;
1971 Ops.push_back(Chain);
1972 Ops.push_back(DAG.getTargetGlobalAddress(Node->getGlobal(), DL,
1973 Node->getValueType(0),
1976 // Add argument registers to the end of the list so that they are
1977 // known live into the call.
1978 Ops.push_back(DAG.getRegister(SystemZ::R2D, PtrVT));
1979 Ops.push_back(DAG.getRegister(SystemZ::R12D, PtrVT));
1981 // Add a register mask operand representing the call-preserved registers.
1982 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1983 const uint32_t *Mask =
1984 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallingConv::C);
1985 assert(Mask && "Missing call preserved mask for calling convention");
1986 Ops.push_back(DAG.getRegisterMask(Mask));
1988 // Glue the call to the argument copies.
1989 Ops.push_back(Glue);
1992 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1993 Chain = DAG.getNode(Opcode, DL, NodeTys, Ops);
1994 Glue = Chain.getValue(1);
1996 // Copy the return value from %r2.
1997 return DAG.getCopyFromReg(Chain, DL, SystemZ::R2D, PtrVT, Glue);
2000 SDValue SystemZTargetLowering::lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
2001 SelectionDAG &DAG) const {
2003 const GlobalValue *GV = Node->getGlobal();
2004 EVT PtrVT = getPointerTy();
2005 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
2007 // The high part of the thread pointer is in access register 0.
2008 SDValue TPHi = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
2009 DAG.getConstant(0, MVT::i32));
2010 TPHi = DAG.getNode(ISD::ANY_EXTEND, DL, PtrVT, TPHi);
2012 // The low part of the thread pointer is in access register 1.
2013 SDValue TPLo = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
2014 DAG.getConstant(1, MVT::i32));
2015 TPLo = DAG.getNode(ISD::ZERO_EXTEND, DL, PtrVT, TPLo);
2017 // Merge them into a single 64-bit address.
2018 SDValue TPHiShifted = DAG.getNode(ISD::SHL, DL, PtrVT, TPHi,
2019 DAG.getConstant(32, PtrVT));
2020 SDValue TP = DAG.getNode(ISD::OR, DL, PtrVT, TPHiShifted, TPLo);
2022 // Get the offset of GA from the thread pointer, based on the TLS model.
2025 case TLSModel::GeneralDynamic: {
2026 // Load the GOT offset of the tls_index (module ID / per-symbol offset).
2027 SystemZConstantPoolValue *CPV =
2028 SystemZConstantPoolValue::Create(GV, SystemZCP::TLSGD);
2030 Offset = DAG.getConstantPool(CPV, PtrVT, 8);
2031 Offset = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(),
2032 Offset, MachinePointerInfo::getConstantPool(),
2033 false, false, false, 0);
2035 // Call __tls_get_offset to retrieve the offset.
2036 Offset = lowerTLSGetOffset(Node, DAG, SystemZISD::TLS_GDCALL, Offset);
2040 case TLSModel::LocalDynamic: {
2041 // Load the GOT offset of the module ID.
2042 SystemZConstantPoolValue *CPV =
2043 SystemZConstantPoolValue::Create(GV, SystemZCP::TLSLDM);
2045 Offset = DAG.getConstantPool(CPV, PtrVT, 8);
2046 Offset = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(),
2047 Offset, MachinePointerInfo::getConstantPool(),
2048 false, false, false, 0);
2050 // Call __tls_get_offset to retrieve the module base offset.
2051 Offset = lowerTLSGetOffset(Node, DAG, SystemZISD::TLS_LDCALL, Offset);
2053 // Note: The SystemZLDCleanupPass will remove redundant computations
2054 // of the module base offset. Count total number of local-dynamic
2055 // accesses to trigger execution of that pass.
2056 SystemZMachineFunctionInfo* MFI =
2057 DAG.getMachineFunction().getInfo<SystemZMachineFunctionInfo>();
2058 MFI->incNumLocalDynamicTLSAccesses();
2060 // Add the per-symbol offset.
2061 CPV = SystemZConstantPoolValue::Create(GV, SystemZCP::DTPOFF);
2063 SDValue DTPOffset = DAG.getConstantPool(CPV, PtrVT, 8);
2064 DTPOffset = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(),
2065 DTPOffset, MachinePointerInfo::getConstantPool(),
2066 false, false, false, 0);
2068 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Offset, DTPOffset);
2072 case TLSModel::InitialExec: {
2073 // Load the offset from the GOT.
2074 Offset = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2075 SystemZII::MO_INDNTPOFF);
2076 Offset = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Offset);
2077 Offset = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(),
2078 Offset, MachinePointerInfo::getGOT(),
2079 false, false, false, 0);
2083 case TLSModel::LocalExec: {
2084 // Force the offset into the constant pool and load it from there.
2085 SystemZConstantPoolValue *CPV =
2086 SystemZConstantPoolValue::Create(GV, SystemZCP::NTPOFF);
2088 Offset = DAG.getConstantPool(CPV, PtrVT, 8);
2089 Offset = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(),
2090 Offset, MachinePointerInfo::getConstantPool(),
2091 false, false, false, 0);
2096 // Add the base and offset together.
2097 return DAG.getNode(ISD::ADD, DL, PtrVT, TP, Offset);
2100 SDValue SystemZTargetLowering::lowerBlockAddress(BlockAddressSDNode *Node,
2101 SelectionDAG &DAG) const {
2103 const BlockAddress *BA = Node->getBlockAddress();
2104 int64_t Offset = Node->getOffset();
2105 EVT PtrVT = getPointerTy();
2107 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset);
2108 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
2112 SDValue SystemZTargetLowering::lowerJumpTable(JumpTableSDNode *JT,
2113 SelectionDAG &DAG) const {
2115 EVT PtrVT = getPointerTy();
2116 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
2118 // Use LARL to load the address of the table.
2119 return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
2122 SDValue SystemZTargetLowering::lowerConstantPool(ConstantPoolSDNode *CP,
2123 SelectionDAG &DAG) const {
2125 EVT PtrVT = getPointerTy();
2128 if (CP->isMachineConstantPoolEntry())
2129 Result = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
2130 CP->getAlignment());
2132 Result = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
2133 CP->getAlignment(), CP->getOffset());
2135 // Use LARL to load the address of the constant pool entry.
2136 return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
2139 SDValue SystemZTargetLowering::lowerBITCAST(SDValue Op,
2140 SelectionDAG &DAG) const {
2142 SDValue In = Op.getOperand(0);
2143 EVT InVT = In.getValueType();
2144 EVT ResVT = Op.getValueType();
2146 if (InVT == MVT::i32 && ResVT == MVT::f32) {
2148 if (Subtarget.hasHighWord()) {
2149 SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL,
2151 In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h32, DL,
2152 MVT::i64, SDValue(U64, 0), In);
2154 In64 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, In);
2155 In64 = DAG.getNode(ISD::SHL, DL, MVT::i64, In64,
2156 DAG.getConstant(32, MVT::i64));
2158 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::f64, In64);
2159 return DAG.getTargetExtractSubreg(SystemZ::subreg_h32,
2160 DL, MVT::f32, Out64);
2162 if (InVT == MVT::f32 && ResVT == MVT::i32) {
2163 SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::f64);
2164 SDValue In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h32, DL,
2165 MVT::f64, SDValue(U64, 0), In);
2166 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::i64, In64);
2167 if (Subtarget.hasHighWord())
2168 return DAG.getTargetExtractSubreg(SystemZ::subreg_h32, DL,
2170 SDValue Shift = DAG.getNode(ISD::SRL, DL, MVT::i64, Out64,
2171 DAG.getConstant(32, MVT::i64));
2172 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Shift);
2174 llvm_unreachable("Unexpected bitcast combination");
2177 SDValue SystemZTargetLowering::lowerVASTART(SDValue Op,
2178 SelectionDAG &DAG) const {
2179 MachineFunction &MF = DAG.getMachineFunction();
2180 SystemZMachineFunctionInfo *FuncInfo =
2181 MF.getInfo<SystemZMachineFunctionInfo>();
2182 EVT PtrVT = getPointerTy();
2184 SDValue Chain = Op.getOperand(0);
2185 SDValue Addr = Op.getOperand(1);
2186 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2189 // The initial values of each field.
2190 const unsigned NumFields = 4;
2191 SDValue Fields[NumFields] = {
2192 DAG.getConstant(FuncInfo->getVarArgsFirstGPR(), PtrVT),
2193 DAG.getConstant(FuncInfo->getVarArgsFirstFPR(), PtrVT),
2194 DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT),
2195 DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT)
2198 // Store each field into its respective slot.
2199 SDValue MemOps[NumFields];
2200 unsigned Offset = 0;
2201 for (unsigned I = 0; I < NumFields; ++I) {
2202 SDValue FieldAddr = Addr;
2204 FieldAddr = DAG.getNode(ISD::ADD, DL, PtrVT, FieldAddr,
2205 DAG.getIntPtrConstant(Offset));
2206 MemOps[I] = DAG.getStore(Chain, DL, Fields[I], FieldAddr,
2207 MachinePointerInfo(SV, Offset),
2211 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
2214 SDValue SystemZTargetLowering::lowerVACOPY(SDValue Op,
2215 SelectionDAG &DAG) const {
2216 SDValue Chain = Op.getOperand(0);
2217 SDValue DstPtr = Op.getOperand(1);
2218 SDValue SrcPtr = Op.getOperand(2);
2219 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
2220 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
2223 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, DAG.getIntPtrConstant(32),
2224 /*Align*/8, /*isVolatile*/false, /*AlwaysInline*/false,
2225 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
2228 SDValue SystemZTargetLowering::
2229 lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
2230 SDValue Chain = Op.getOperand(0);
2231 SDValue Size = Op.getOperand(1);
2234 unsigned SPReg = getStackPointerRegisterToSaveRestore();
2236 // Get a reference to the stack pointer.
2237 SDValue OldSP = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i64);
2239 // Get the new stack pointer value.
2240 SDValue NewSP = DAG.getNode(ISD::SUB, DL, MVT::i64, OldSP, Size);
2242 // Copy the new stack pointer back.
2243 Chain = DAG.getCopyToReg(Chain, DL, SPReg, NewSP);
2245 // The allocated data lives above the 160 bytes allocated for the standard
2246 // frame, plus any outgoing stack arguments. We don't know how much that
2247 // amounts to yet, so emit a special ADJDYNALLOC placeholder.
2248 SDValue ArgAdjust = DAG.getNode(SystemZISD::ADJDYNALLOC, DL, MVT::i64);
2249 SDValue Result = DAG.getNode(ISD::ADD, DL, MVT::i64, NewSP, ArgAdjust);
2251 SDValue Ops[2] = { Result, Chain };
2252 return DAG.getMergeValues(Ops, DL);
2255 SDValue SystemZTargetLowering::lowerSMUL_LOHI(SDValue Op,
2256 SelectionDAG &DAG) const {
2257 EVT VT = Op.getValueType();
2261 // Just do a normal 64-bit multiplication and extract the results.
2262 // We define this so that it can be used for constant division.
2263 lowerMUL_LOHI32(DAG, DL, ISD::SIGN_EXTEND, Op.getOperand(0),
2264 Op.getOperand(1), Ops[1], Ops[0]);
2266 // Do a full 128-bit multiplication based on UMUL_LOHI64:
2268 // (ll * rl) + ((lh * rl) << 64) + ((ll * rh) << 64)
2270 // but using the fact that the upper halves are either all zeros
2273 // (ll * rl) - ((lh & rl) << 64) - ((ll & rh) << 64)
2275 // and grouping the right terms together since they are quicker than the
2278 // (ll * rl) - (((lh & rl) + (ll & rh)) << 64)
2279 SDValue C63 = DAG.getConstant(63, MVT::i64);
2280 SDValue LL = Op.getOperand(0);
2281 SDValue RL = Op.getOperand(1);
2282 SDValue LH = DAG.getNode(ISD::SRA, DL, VT, LL, C63);
2283 SDValue RH = DAG.getNode(ISD::SRA, DL, VT, RL, C63);
2284 // UMUL_LOHI64 returns the low result in the odd register and the high
2285 // result in the even register. SMUL_LOHI is defined to return the
2286 // low half first, so the results are in reverse order.
2287 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
2288 LL, RL, Ops[1], Ops[0]);
2289 SDValue NegLLTimesRH = DAG.getNode(ISD::AND, DL, VT, LL, RH);
2290 SDValue NegLHTimesRL = DAG.getNode(ISD::AND, DL, VT, LH, RL);
2291 SDValue NegSum = DAG.getNode(ISD::ADD, DL, VT, NegLLTimesRH, NegLHTimesRL);
2292 Ops[1] = DAG.getNode(ISD::SUB, DL, VT, Ops[1], NegSum);
2294 return DAG.getMergeValues(Ops, DL);
2297 SDValue SystemZTargetLowering::lowerUMUL_LOHI(SDValue Op,
2298 SelectionDAG &DAG) const {
2299 EVT VT = Op.getValueType();
2303 // Just do a normal 64-bit multiplication and extract the results.
2304 // We define this so that it can be used for constant division.
2305 lowerMUL_LOHI32(DAG, DL, ISD::ZERO_EXTEND, Op.getOperand(0),
2306 Op.getOperand(1), Ops[1], Ops[0]);
2308 // UMUL_LOHI64 returns the low result in the odd register and the high
2309 // result in the even register. UMUL_LOHI is defined to return the
2310 // low half first, so the results are in reverse order.
2311 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
2312 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
2313 return DAG.getMergeValues(Ops, DL);
2316 SDValue SystemZTargetLowering::lowerSDIVREM(SDValue Op,
2317 SelectionDAG &DAG) const {
2318 SDValue Op0 = Op.getOperand(0);
2319 SDValue Op1 = Op.getOperand(1);
2320 EVT VT = Op.getValueType();
2324 // We use DSGF for 32-bit division.
2326 Op0 = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op0);
2327 Opcode = SystemZISD::SDIVREM32;
2328 } else if (DAG.ComputeNumSignBits(Op1) > 32) {
2329 Op1 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op1);
2330 Opcode = SystemZISD::SDIVREM32;
2332 Opcode = SystemZISD::SDIVREM64;
2334 // DSG(F) takes a 64-bit dividend, so the even register in the GR128
2335 // input is "don't care". The instruction returns the remainder in
2336 // the even register and the quotient in the odd register.
2338 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, Opcode,
2339 Op0, Op1, Ops[1], Ops[0]);
2340 return DAG.getMergeValues(Ops, DL);
2343 SDValue SystemZTargetLowering::lowerUDIVREM(SDValue Op,
2344 SelectionDAG &DAG) const {
2345 EVT VT = Op.getValueType();
2348 // DL(G) uses a double-width dividend, so we need to clear the even
2349 // register in the GR128 input. The instruction returns the remainder
2350 // in the even register and the quotient in the odd register.
2353 lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_32, SystemZISD::UDIVREM32,
2354 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
2356 lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_64, SystemZISD::UDIVREM64,
2357 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
2358 return DAG.getMergeValues(Ops, DL);
2361 SDValue SystemZTargetLowering::lowerOR(SDValue Op, SelectionDAG &DAG) const {
2362 assert(Op.getValueType() == MVT::i64 && "Should be 64-bit operation");
2364 // Get the known-zero masks for each operand.
2365 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1) };
2366 APInt KnownZero[2], KnownOne[2];
2367 DAG.computeKnownBits(Ops[0], KnownZero[0], KnownOne[0]);
2368 DAG.computeKnownBits(Ops[1], KnownZero[1], KnownOne[1]);
2370 // See if the upper 32 bits of one operand and the lower 32 bits of the
2371 // other are known zero. They are the low and high operands respectively.
2372 uint64_t Masks[] = { KnownZero[0].getZExtValue(),
2373 KnownZero[1].getZExtValue() };
2375 if ((Masks[0] >> 32) == 0xffffffff && uint32_t(Masks[1]) == 0xffffffff)
2377 else if ((Masks[1] >> 32) == 0xffffffff && uint32_t(Masks[0]) == 0xffffffff)
2382 SDValue LowOp = Ops[Low];
2383 SDValue HighOp = Ops[High];
2385 // If the high part is a constant, we're better off using IILH.
2386 if (HighOp.getOpcode() == ISD::Constant)
2389 // If the low part is a constant that is outside the range of LHI,
2390 // then we're better off using IILF.
2391 if (LowOp.getOpcode() == ISD::Constant) {
2392 int64_t Value = int32_t(cast<ConstantSDNode>(LowOp)->getZExtValue());
2393 if (!isInt<16>(Value))
2397 // Check whether the high part is an AND that doesn't change the
2398 // high 32 bits and just masks out low bits. We can skip it if so.
2399 if (HighOp.getOpcode() == ISD::AND &&
2400 HighOp.getOperand(1).getOpcode() == ISD::Constant) {
2401 SDValue HighOp0 = HighOp.getOperand(0);
2402 uint64_t Mask = cast<ConstantSDNode>(HighOp.getOperand(1))->getZExtValue();
2403 if (DAG.MaskedValueIsZero(HighOp0, APInt(64, ~(Mask | 0xffffffff))))
2407 // Take advantage of the fact that all GR32 operations only change the
2408 // low 32 bits by truncating Low to an i32 and inserting it directly
2409 // using a subreg. The interesting cases are those where the truncation
2412 SDValue Low32 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, LowOp);
2413 return DAG.getTargetInsertSubreg(SystemZ::subreg_l32, DL,
2414 MVT::i64, HighOp, Low32);
2417 SDValue SystemZTargetLowering::lowerCTPOP(SDValue Op,
2418 SelectionDAG &DAG) const {
2419 EVT VT = Op.getValueType();
2420 int64_t OrigBitSize = VT.getSizeInBits();
2423 // Get the known-zero mask for the operand.
2424 Op = Op.getOperand(0);
2425 APInt KnownZero, KnownOne;
2426 DAG.computeKnownBits(Op, KnownZero, KnownOne);
2427 unsigned NumSignificantBits = (~KnownZero).getActiveBits();
2428 if (NumSignificantBits == 0)
2429 return DAG.getConstant(0, VT);
2431 // Skip known-zero high parts of the operand.
2432 int64_t BitSize = (int64_t)1 << Log2_32_Ceil(NumSignificantBits);
2433 BitSize = std::min(BitSize, OrigBitSize);
2435 // The POPCNT instruction counts the number of bits in each byte.
2436 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op);
2437 Op = DAG.getNode(SystemZISD::POPCNT, DL, MVT::i64, Op);
2438 Op = DAG.getNode(ISD::TRUNCATE, DL, VT, Op);
2440 // Add up per-byte counts in a binary tree. All bits of Op at
2441 // position larger than BitSize remain zero throughout.
2442 for (int64_t I = BitSize / 2; I >= 8; I = I / 2) {
2443 SDValue Tmp = DAG.getNode(ISD::SHL, DL, VT, Op, DAG.getConstant(I, VT));
2444 if (BitSize != OrigBitSize)
2445 Tmp = DAG.getNode(ISD::AND, DL, VT, Tmp,
2446 DAG.getConstant(((uint64_t)1 << BitSize) - 1, VT));
2447 Op = DAG.getNode(ISD::ADD, DL, VT, Op, Tmp);
2450 // Extract overall result from high byte.
2452 Op = DAG.getNode(ISD::SRL, DL, VT, Op, DAG.getConstant(BitSize - 8, VT));
2457 // Op is an atomic load. Lower it into a normal volatile load.
2458 SDValue SystemZTargetLowering::lowerATOMIC_LOAD(SDValue Op,
2459 SelectionDAG &DAG) const {
2460 auto *Node = cast<AtomicSDNode>(Op.getNode());
2461 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), Op.getValueType(),
2462 Node->getChain(), Node->getBasePtr(),
2463 Node->getMemoryVT(), Node->getMemOperand());
2466 // Op is an atomic store. Lower it into a normal volatile store followed
2467 // by a serialization.
2468 SDValue SystemZTargetLowering::lowerATOMIC_STORE(SDValue Op,
2469 SelectionDAG &DAG) const {
2470 auto *Node = cast<AtomicSDNode>(Op.getNode());
2471 SDValue Chain = DAG.getTruncStore(Node->getChain(), SDLoc(Op), Node->getVal(),
2472 Node->getBasePtr(), Node->getMemoryVT(),
2473 Node->getMemOperand());
2474 return SDValue(DAG.getMachineNode(SystemZ::Serialize, SDLoc(Op), MVT::Other,
2478 // Op is an 8-, 16-bit or 32-bit ATOMIC_LOAD_* operation. Lower the first
2479 // two into the fullword ATOMIC_LOADW_* operation given by Opcode.
2480 SDValue SystemZTargetLowering::lowerATOMIC_LOAD_OP(SDValue Op,
2482 unsigned Opcode) const {
2483 auto *Node = cast<AtomicSDNode>(Op.getNode());
2485 // 32-bit operations need no code outside the main loop.
2486 EVT NarrowVT = Node->getMemoryVT();
2487 EVT WideVT = MVT::i32;
2488 if (NarrowVT == WideVT)
2491 int64_t BitSize = NarrowVT.getSizeInBits();
2492 SDValue ChainIn = Node->getChain();
2493 SDValue Addr = Node->getBasePtr();
2494 SDValue Src2 = Node->getVal();
2495 MachineMemOperand *MMO = Node->getMemOperand();
2497 EVT PtrVT = Addr.getValueType();
2499 // Convert atomic subtracts of constants into additions.
2500 if (Opcode == SystemZISD::ATOMIC_LOADW_SUB)
2501 if (auto *Const = dyn_cast<ConstantSDNode>(Src2)) {
2502 Opcode = SystemZISD::ATOMIC_LOADW_ADD;
2503 Src2 = DAG.getConstant(-Const->getSExtValue(), Src2.getValueType());
2506 // Get the address of the containing word.
2507 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
2508 DAG.getConstant(-4, PtrVT));
2510 // Get the number of bits that the word must be rotated left in order
2511 // to bring the field to the top bits of a GR32.
2512 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
2513 DAG.getConstant(3, PtrVT));
2514 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
2516 // Get the complementing shift amount, for rotating a field in the top
2517 // bits back to its proper position.
2518 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
2519 DAG.getConstant(0, WideVT), BitShift);
2521 // Extend the source operand to 32 bits and prepare it for the inner loop.
2522 // ATOMIC_SWAPW uses RISBG to rotate the field left, but all other
2523 // operations require the source to be shifted in advance. (This shift
2524 // can be folded if the source is constant.) For AND and NAND, the lower
2525 // bits must be set, while for other opcodes they should be left clear.
2526 if (Opcode != SystemZISD::ATOMIC_SWAPW)
2527 Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2,
2528 DAG.getConstant(32 - BitSize, WideVT));
2529 if (Opcode == SystemZISD::ATOMIC_LOADW_AND ||
2530 Opcode == SystemZISD::ATOMIC_LOADW_NAND)
2531 Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2,
2532 DAG.getConstant(uint32_t(-1) >> BitSize, WideVT));
2534 // Construct the ATOMIC_LOADW_* node.
2535 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
2536 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift,
2537 DAG.getConstant(BitSize, WideVT) };
2538 SDValue AtomicOp = DAG.getMemIntrinsicNode(Opcode, DL, VTList, Ops,
2541 // Rotate the result of the final CS so that the field is in the lower
2542 // bits of a GR32, then truncate it.
2543 SDValue ResultShift = DAG.getNode(ISD::ADD, DL, WideVT, BitShift,
2544 DAG.getConstant(BitSize, WideVT));
2545 SDValue Result = DAG.getNode(ISD::ROTL, DL, WideVT, AtomicOp, ResultShift);
2547 SDValue RetOps[2] = { Result, AtomicOp.getValue(1) };
2548 return DAG.getMergeValues(RetOps, DL);
2551 // Op is an ATOMIC_LOAD_SUB operation. Lower 8- and 16-bit operations
2552 // into ATOMIC_LOADW_SUBs and decide whether to convert 32- and 64-bit
2553 // operations into additions.
2554 SDValue SystemZTargetLowering::lowerATOMIC_LOAD_SUB(SDValue Op,
2555 SelectionDAG &DAG) const {
2556 auto *Node = cast<AtomicSDNode>(Op.getNode());
2557 EVT MemVT = Node->getMemoryVT();
2558 if (MemVT == MVT::i32 || MemVT == MVT::i64) {
2559 // A full-width operation.
2560 assert(Op.getValueType() == MemVT && "Mismatched VTs");
2561 SDValue Src2 = Node->getVal();
2565 if (auto *Op2 = dyn_cast<ConstantSDNode>(Src2)) {
2566 // Use an addition if the operand is constant and either LAA(G) is
2567 // available or the negative value is in the range of A(G)FHI.
2568 int64_t Value = (-Op2->getAPIntValue()).getSExtValue();
2569 if (isInt<32>(Value) || Subtarget.hasInterlockedAccess1())
2570 NegSrc2 = DAG.getConstant(Value, MemVT);
2571 } else if (Subtarget.hasInterlockedAccess1())
2572 // Use LAA(G) if available.
2573 NegSrc2 = DAG.getNode(ISD::SUB, DL, MemVT, DAG.getConstant(0, MemVT),
2576 if (NegSrc2.getNode())
2577 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, DL, MemVT,
2578 Node->getChain(), Node->getBasePtr(), NegSrc2,
2579 Node->getMemOperand(), Node->getOrdering(),
2580 Node->getSynchScope());
2582 // Use the node as-is.
2586 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_SUB);
2589 // Node is an 8- or 16-bit ATOMIC_CMP_SWAP operation. Lower the first two
2590 // into a fullword ATOMIC_CMP_SWAPW operation.
2591 SDValue SystemZTargetLowering::lowerATOMIC_CMP_SWAP(SDValue Op,
2592 SelectionDAG &DAG) const {
2593 auto *Node = cast<AtomicSDNode>(Op.getNode());
2595 // We have native support for 32-bit compare and swap.
2596 EVT NarrowVT = Node->getMemoryVT();
2597 EVT WideVT = MVT::i32;
2598 if (NarrowVT == WideVT)
2601 int64_t BitSize = NarrowVT.getSizeInBits();
2602 SDValue ChainIn = Node->getOperand(0);
2603 SDValue Addr = Node->getOperand(1);
2604 SDValue CmpVal = Node->getOperand(2);
2605 SDValue SwapVal = Node->getOperand(3);
2606 MachineMemOperand *MMO = Node->getMemOperand();
2608 EVT PtrVT = Addr.getValueType();
2610 // Get the address of the containing word.
2611 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
2612 DAG.getConstant(-4, PtrVT));
2614 // Get the number of bits that the word must be rotated left in order
2615 // to bring the field to the top bits of a GR32.
2616 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
2617 DAG.getConstant(3, PtrVT));
2618 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
2620 // Get the complementing shift amount, for rotating a field in the top
2621 // bits back to its proper position.
2622 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
2623 DAG.getConstant(0, WideVT), BitShift);
2625 // Construct the ATOMIC_CMP_SWAPW node.
2626 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
2627 SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift,
2628 NegBitShift, DAG.getConstant(BitSize, WideVT) };
2629 SDValue AtomicOp = DAG.getMemIntrinsicNode(SystemZISD::ATOMIC_CMP_SWAPW, DL,
2630 VTList, Ops, NarrowVT, MMO);
2634 SDValue SystemZTargetLowering::lowerSTACKSAVE(SDValue Op,
2635 SelectionDAG &DAG) const {
2636 MachineFunction &MF = DAG.getMachineFunction();
2637 MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
2638 return DAG.getCopyFromReg(Op.getOperand(0), SDLoc(Op),
2639 SystemZ::R15D, Op.getValueType());
2642 SDValue SystemZTargetLowering::lowerSTACKRESTORE(SDValue Op,
2643 SelectionDAG &DAG) const {
2644 MachineFunction &MF = DAG.getMachineFunction();
2645 MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
2646 return DAG.getCopyToReg(Op.getOperand(0), SDLoc(Op),
2647 SystemZ::R15D, Op.getOperand(1));
2650 SDValue SystemZTargetLowering::lowerPREFETCH(SDValue Op,
2651 SelectionDAG &DAG) const {
2652 bool IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
2654 // Just preserve the chain.
2655 return Op.getOperand(0);
2657 bool IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
2658 unsigned Code = IsWrite ? SystemZ::PFD_WRITE : SystemZ::PFD_READ;
2659 auto *Node = cast<MemIntrinsicSDNode>(Op.getNode());
2662 DAG.getConstant(Code, MVT::i32),
2665 return DAG.getMemIntrinsicNode(SystemZISD::PREFETCH, SDLoc(Op),
2666 Node->getVTList(), Ops,
2667 Node->getMemoryVT(), Node->getMemOperand());
2670 // Return an i32 that contains the value of CC immediately after After,
2671 // whose final operand must be MVT::Glue.
2672 static SDValue getCCResult(SelectionDAG &DAG, SDNode *After) {
2673 SDValue Glue = SDValue(After, After->getNumValues() - 1);
2674 SDValue IPM = DAG.getNode(SystemZISD::IPM, SDLoc(After), MVT::i32, Glue);
2675 return DAG.getNode(ISD::SRL, SDLoc(After), MVT::i32, IPM,
2676 DAG.getConstant(SystemZ::IPM_CC, MVT::i32));
2680 SystemZTargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
2681 SelectionDAG &DAG) const {
2682 unsigned Opcode, CCValid;
2683 if (isIntrinsicWithCCAndChain(Op, Opcode, CCValid)) {
2684 assert(Op->getNumValues() == 2 && "Expected only CC result and chain");
2685 SDValue Glued = emitIntrinsicWithChainAndGlue(DAG, Op, Opcode);
2686 SDValue CC = getCCResult(DAG, Glued.getNode());
2687 DAG.ReplaceAllUsesOfValueWith(SDValue(Op.getNode(), 0), CC);
2694 SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
2695 SelectionDAG &DAG) const {
2696 switch (Op.getOpcode()) {
2698 return lowerBR_CC(Op, DAG);
2699 case ISD::SELECT_CC:
2700 return lowerSELECT_CC(Op, DAG);
2702 return lowerSETCC(Op, DAG);
2703 case ISD::GlobalAddress:
2704 return lowerGlobalAddress(cast<GlobalAddressSDNode>(Op), DAG);
2705 case ISD::GlobalTLSAddress:
2706 return lowerGlobalTLSAddress(cast<GlobalAddressSDNode>(Op), DAG);
2707 case ISD::BlockAddress:
2708 return lowerBlockAddress(cast<BlockAddressSDNode>(Op), DAG);
2709 case ISD::JumpTable:
2710 return lowerJumpTable(cast<JumpTableSDNode>(Op), DAG);
2711 case ISD::ConstantPool:
2712 return lowerConstantPool(cast<ConstantPoolSDNode>(Op), DAG);
2714 return lowerBITCAST(Op, DAG);
2716 return lowerVASTART(Op, DAG);
2718 return lowerVACOPY(Op, DAG);
2719 case ISD::DYNAMIC_STACKALLOC:
2720 return lowerDYNAMIC_STACKALLOC(Op, DAG);
2721 case ISD::SMUL_LOHI:
2722 return lowerSMUL_LOHI(Op, DAG);
2723 case ISD::UMUL_LOHI:
2724 return lowerUMUL_LOHI(Op, DAG);
2726 return lowerSDIVREM(Op, DAG);
2728 return lowerUDIVREM(Op, DAG);
2730 return lowerOR(Op, DAG);
2732 return lowerCTPOP(Op, DAG);
2733 case ISD::ATOMIC_SWAP:
2734 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_SWAPW);
2735 case ISD::ATOMIC_STORE:
2736 return lowerATOMIC_STORE(Op, DAG);
2737 case ISD::ATOMIC_LOAD:
2738 return lowerATOMIC_LOAD(Op, DAG);
2739 case ISD::ATOMIC_LOAD_ADD:
2740 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_ADD);
2741 case ISD::ATOMIC_LOAD_SUB:
2742 return lowerATOMIC_LOAD_SUB(Op, DAG);
2743 case ISD::ATOMIC_LOAD_AND:
2744 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_AND);
2745 case ISD::ATOMIC_LOAD_OR:
2746 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_OR);
2747 case ISD::ATOMIC_LOAD_XOR:
2748 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_XOR);
2749 case ISD::ATOMIC_LOAD_NAND:
2750 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_NAND);
2751 case ISD::ATOMIC_LOAD_MIN:
2752 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_MIN);
2753 case ISD::ATOMIC_LOAD_MAX:
2754 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_MAX);
2755 case ISD::ATOMIC_LOAD_UMIN:
2756 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_UMIN);
2757 case ISD::ATOMIC_LOAD_UMAX:
2758 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_UMAX);
2759 case ISD::ATOMIC_CMP_SWAP:
2760 return lowerATOMIC_CMP_SWAP(Op, DAG);
2761 case ISD::STACKSAVE:
2762 return lowerSTACKSAVE(Op, DAG);
2763 case ISD::STACKRESTORE:
2764 return lowerSTACKRESTORE(Op, DAG);
2766 return lowerPREFETCH(Op, DAG);
2767 case ISD::INTRINSIC_W_CHAIN:
2768 return lowerINTRINSIC_W_CHAIN(Op, DAG);
2770 llvm_unreachable("Unexpected node to lower");
2774 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
2775 #define OPCODE(NAME) case SystemZISD::NAME: return "SystemZISD::" #NAME
2780 OPCODE(PCREL_WRAPPER);
2781 OPCODE(PCREL_OFFSET);
2787 OPCODE(SELECT_CCMASK);
2788 OPCODE(ADJDYNALLOC);
2789 OPCODE(EXTRACT_ACCESS);
2790 OPCODE(UMUL_LOHI64);
2806 OPCODE(SEARCH_STRING);
2810 OPCODE(TBEGIN_NOFLOAT);
2812 OPCODE(ATOMIC_SWAPW);
2813 OPCODE(ATOMIC_LOADW_ADD);
2814 OPCODE(ATOMIC_LOADW_SUB);
2815 OPCODE(ATOMIC_LOADW_AND);
2816 OPCODE(ATOMIC_LOADW_OR);
2817 OPCODE(ATOMIC_LOADW_XOR);
2818 OPCODE(ATOMIC_LOADW_NAND);
2819 OPCODE(ATOMIC_LOADW_MIN);
2820 OPCODE(ATOMIC_LOADW_MAX);
2821 OPCODE(ATOMIC_LOADW_UMIN);
2822 OPCODE(ATOMIC_LOADW_UMAX);
2823 OPCODE(ATOMIC_CMP_SWAPW);
2830 SDValue SystemZTargetLowering::PerformDAGCombine(SDNode *N,
2831 DAGCombinerInfo &DCI) const {
2832 SelectionDAG &DAG = DCI.DAG;
2833 unsigned Opcode = N->getOpcode();
2834 if (Opcode == ISD::SIGN_EXTEND) {
2835 // Convert (sext (ashr (shl X, C1), C2)) to
2836 // (ashr (shl (anyext X), C1'), C2')), since wider shifts are as
2837 // cheap as narrower ones.
2838 SDValue N0 = N->getOperand(0);
2839 EVT VT = N->getValueType(0);
2840 if (N0.hasOneUse() && N0.getOpcode() == ISD::SRA) {
2841 auto *SraAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2842 SDValue Inner = N0.getOperand(0);
2843 if (SraAmt && Inner.hasOneUse() && Inner.getOpcode() == ISD::SHL) {
2844 if (auto *ShlAmt = dyn_cast<ConstantSDNode>(Inner.getOperand(1))) {
2845 unsigned Extra = (VT.getSizeInBits() -
2846 N0.getValueType().getSizeInBits());
2847 unsigned NewShlAmt = ShlAmt->getZExtValue() + Extra;
2848 unsigned NewSraAmt = SraAmt->getZExtValue() + Extra;
2849 EVT ShiftVT = N0.getOperand(1).getValueType();
2850 SDValue Ext = DAG.getNode(ISD::ANY_EXTEND, SDLoc(Inner), VT,
2851 Inner.getOperand(0));
2852 SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(Inner), VT, Ext,
2853 DAG.getConstant(NewShlAmt, ShiftVT));
2854 return DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl,
2855 DAG.getConstant(NewSraAmt, ShiftVT));
2863 //===----------------------------------------------------------------------===//
2865 //===----------------------------------------------------------------------===//
2867 // Create a new basic block after MBB.
2868 static MachineBasicBlock *emitBlockAfter(MachineBasicBlock *MBB) {
2869 MachineFunction &MF = *MBB->getParent();
2870 MachineBasicBlock *NewMBB = MF.CreateMachineBasicBlock(MBB->getBasicBlock());
2871 MF.insert(std::next(MachineFunction::iterator(MBB)), NewMBB);
2875 // Split MBB after MI and return the new block (the one that contains
2876 // instructions after MI).
2877 static MachineBasicBlock *splitBlockAfter(MachineInstr *MI,
2878 MachineBasicBlock *MBB) {
2879 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
2880 NewMBB->splice(NewMBB->begin(), MBB,
2881 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
2882 NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
2886 // Split MBB before MI and return the new block (the one that contains MI).
2887 static MachineBasicBlock *splitBlockBefore(MachineInstr *MI,
2888 MachineBasicBlock *MBB) {
2889 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
2890 NewMBB->splice(NewMBB->begin(), MBB, MI, MBB->end());
2891 NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
2895 // Force base value Base into a register before MI. Return the register.
2896 static unsigned forceReg(MachineInstr *MI, MachineOperand &Base,
2897 const SystemZInstrInfo *TII) {
2899 return Base.getReg();
2901 MachineBasicBlock *MBB = MI->getParent();
2902 MachineFunction &MF = *MBB->getParent();
2903 MachineRegisterInfo &MRI = MF.getRegInfo();
2905 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
2906 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LA), Reg)
2907 .addOperand(Base).addImm(0).addReg(0);
2911 // Implement EmitInstrWithCustomInserter for pseudo Select* instruction MI.
2913 SystemZTargetLowering::emitSelect(MachineInstr *MI,
2914 MachineBasicBlock *MBB) const {
2915 const SystemZInstrInfo *TII =
2916 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
2918 unsigned DestReg = MI->getOperand(0).getReg();
2919 unsigned TrueReg = MI->getOperand(1).getReg();
2920 unsigned FalseReg = MI->getOperand(2).getReg();
2921 unsigned CCValid = MI->getOperand(3).getImm();
2922 unsigned CCMask = MI->getOperand(4).getImm();
2923 DebugLoc DL = MI->getDebugLoc();
2925 MachineBasicBlock *StartMBB = MBB;
2926 MachineBasicBlock *JoinMBB = splitBlockBefore(MI, MBB);
2927 MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
2930 // BRC CCMask, JoinMBB
2931 // # fallthrough to FalseMBB
2933 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2934 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
2935 MBB->addSuccessor(JoinMBB);
2936 MBB->addSuccessor(FalseMBB);
2939 // # fallthrough to JoinMBB
2941 MBB->addSuccessor(JoinMBB);
2944 // %Result = phi [ %FalseReg, FalseMBB ], [ %TrueReg, StartMBB ]
2947 BuildMI(*MBB, MI, DL, TII->get(SystemZ::PHI), DestReg)
2948 .addReg(TrueReg).addMBB(StartMBB)
2949 .addReg(FalseReg).addMBB(FalseMBB);
2951 MI->eraseFromParent();
2955 // Implement EmitInstrWithCustomInserter for pseudo CondStore* instruction MI.
2956 // StoreOpcode is the store to use and Invert says whether the store should
2957 // happen when the condition is false rather than true. If a STORE ON
2958 // CONDITION is available, STOCOpcode is its opcode, otherwise it is 0.
2960 SystemZTargetLowering::emitCondStore(MachineInstr *MI,
2961 MachineBasicBlock *MBB,
2962 unsigned StoreOpcode, unsigned STOCOpcode,
2963 bool Invert) const {
2964 const SystemZInstrInfo *TII =
2965 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
2967 unsigned SrcReg = MI->getOperand(0).getReg();
2968 MachineOperand Base = MI->getOperand(1);
2969 int64_t Disp = MI->getOperand(2).getImm();
2970 unsigned IndexReg = MI->getOperand(3).getReg();
2971 unsigned CCValid = MI->getOperand(4).getImm();
2972 unsigned CCMask = MI->getOperand(5).getImm();
2973 DebugLoc DL = MI->getDebugLoc();
2975 StoreOpcode = TII->getOpcodeForOffset(StoreOpcode, Disp);
2977 // Use STOCOpcode if possible. We could use different store patterns in
2978 // order to avoid matching the index register, but the performance trade-offs
2979 // might be more complicated in that case.
2980 if (STOCOpcode && !IndexReg && Subtarget.hasLoadStoreOnCond()) {
2983 BuildMI(*MBB, MI, DL, TII->get(STOCOpcode))
2984 .addReg(SrcReg).addOperand(Base).addImm(Disp)
2985 .addImm(CCValid).addImm(CCMask);
2986 MI->eraseFromParent();
2990 // Get the condition needed to branch around the store.
2994 MachineBasicBlock *StartMBB = MBB;
2995 MachineBasicBlock *JoinMBB = splitBlockBefore(MI, MBB);
2996 MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
2999 // BRC CCMask, JoinMBB
3000 // # fallthrough to FalseMBB
3002 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
3003 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
3004 MBB->addSuccessor(JoinMBB);
3005 MBB->addSuccessor(FalseMBB);
3008 // store %SrcReg, %Disp(%Index,%Base)
3009 // # fallthrough to JoinMBB
3011 BuildMI(MBB, DL, TII->get(StoreOpcode))
3012 .addReg(SrcReg).addOperand(Base).addImm(Disp).addReg(IndexReg);
3013 MBB->addSuccessor(JoinMBB);
3015 MI->eraseFromParent();
3019 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_LOAD{,W}_*
3020 // or ATOMIC_SWAP{,W} instruction MI. BinOpcode is the instruction that
3021 // performs the binary operation elided by "*", or 0 for ATOMIC_SWAP{,W}.
3022 // BitSize is the width of the field in bits, or 0 if this is a partword
3023 // ATOMIC_LOADW_* or ATOMIC_SWAPW instruction, in which case the bitsize
3024 // is one of the operands. Invert says whether the field should be
3025 // inverted after performing BinOpcode (e.g. for NAND).
3027 SystemZTargetLowering::emitAtomicLoadBinary(MachineInstr *MI,
3028 MachineBasicBlock *MBB,
3031 bool Invert) const {
3032 MachineFunction &MF = *MBB->getParent();
3033 const SystemZInstrInfo *TII =
3034 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
3035 MachineRegisterInfo &MRI = MF.getRegInfo();
3036 bool IsSubWord = (BitSize < 32);
3038 // Extract the operands. Base can be a register or a frame index.
3039 // Src2 can be a register or immediate.
3040 unsigned Dest = MI->getOperand(0).getReg();
3041 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
3042 int64_t Disp = MI->getOperand(2).getImm();
3043 MachineOperand Src2 = earlyUseOperand(MI->getOperand(3));
3044 unsigned BitShift = (IsSubWord ? MI->getOperand(4).getReg() : 0);
3045 unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0);
3046 DebugLoc DL = MI->getDebugLoc();
3048 BitSize = MI->getOperand(6).getImm();
3050 // Subword operations use 32-bit registers.
3051 const TargetRegisterClass *RC = (BitSize <= 32 ?
3052 &SystemZ::GR32BitRegClass :
3053 &SystemZ::GR64BitRegClass);
3054 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
3055 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
3057 // Get the right opcodes for the displacement.
3058 LOpcode = TII->getOpcodeForOffset(LOpcode, Disp);
3059 CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
3060 assert(LOpcode && CSOpcode && "Displacement out of range");
3062 // Create virtual registers for temporary results.
3063 unsigned OrigVal = MRI.createVirtualRegister(RC);
3064 unsigned OldVal = MRI.createVirtualRegister(RC);
3065 unsigned NewVal = (BinOpcode || IsSubWord ?
3066 MRI.createVirtualRegister(RC) : Src2.getReg());
3067 unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
3068 unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
3070 // Insert a basic block for the main loop.
3071 MachineBasicBlock *StartMBB = MBB;
3072 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
3073 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
3077 // %OrigVal = L Disp(%Base)
3078 // # fall through to LoopMMB
3080 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
3081 .addOperand(Base).addImm(Disp).addReg(0);
3082 MBB->addSuccessor(LoopMBB);
3085 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, LoopMBB ]
3086 // %RotatedOldVal = RLL %OldVal, 0(%BitShift)
3087 // %RotatedNewVal = OP %RotatedOldVal, %Src2
3088 // %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
3089 // %Dest = CS %OldVal, %NewVal, Disp(%Base)
3091 // # fall through to DoneMMB
3093 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
3094 .addReg(OrigVal).addMBB(StartMBB)
3095 .addReg(Dest).addMBB(LoopMBB);
3097 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
3098 .addReg(OldVal).addReg(BitShift).addImm(0);
3100 // Perform the operation normally and then invert every bit of the field.
3101 unsigned Tmp = MRI.createVirtualRegister(RC);
3102 BuildMI(MBB, DL, TII->get(BinOpcode), Tmp)
3103 .addReg(RotatedOldVal).addOperand(Src2);
3105 // XILF with the upper BitSize bits set.
3106 BuildMI(MBB, DL, TII->get(SystemZ::XILF), RotatedNewVal)
3107 .addReg(Tmp).addImm(-1U << (32 - BitSize));
3109 // Use LCGR and add -1 to the result, which is more compact than
3110 // an XILF, XILH pair.
3111 unsigned Tmp2 = MRI.createVirtualRegister(RC);
3112 BuildMI(MBB, DL, TII->get(SystemZ::LCGR), Tmp2).addReg(Tmp);
3113 BuildMI(MBB, DL, TII->get(SystemZ::AGHI), RotatedNewVal)
3114 .addReg(Tmp2).addImm(-1);
3116 } else if (BinOpcode)
3117 // A simply binary operation.
3118 BuildMI(MBB, DL, TII->get(BinOpcode), RotatedNewVal)
3119 .addReg(RotatedOldVal).addOperand(Src2);
3121 // Use RISBG to rotate Src2 into position and use it to replace the
3122 // field in RotatedOldVal.
3123 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedNewVal)
3124 .addReg(RotatedOldVal).addReg(Src2.getReg())
3125 .addImm(32).addImm(31 + BitSize).addImm(32 - BitSize);
3127 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
3128 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
3129 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
3130 .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
3131 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
3132 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
3133 MBB->addSuccessor(LoopMBB);
3134 MBB->addSuccessor(DoneMBB);
3136 MI->eraseFromParent();
3140 // Implement EmitInstrWithCustomInserter for pseudo
3141 // ATOMIC_LOAD{,W}_{,U}{MIN,MAX} instruction MI. CompareOpcode is the
3142 // instruction that should be used to compare the current field with the
3143 // minimum or maximum value. KeepOldMask is the BRC condition-code mask
3144 // for when the current field should be kept. BitSize is the width of
3145 // the field in bits, or 0 if this is a partword ATOMIC_LOADW_* instruction.
3147 SystemZTargetLowering::emitAtomicLoadMinMax(MachineInstr *MI,
3148 MachineBasicBlock *MBB,
3149 unsigned CompareOpcode,
3150 unsigned KeepOldMask,
3151 unsigned BitSize) const {
3152 MachineFunction &MF = *MBB->getParent();
3153 const SystemZInstrInfo *TII =
3154 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
3155 MachineRegisterInfo &MRI = MF.getRegInfo();
3156 bool IsSubWord = (BitSize < 32);
3158 // Extract the operands. Base can be a register or a frame index.
3159 unsigned Dest = MI->getOperand(0).getReg();
3160 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
3161 int64_t Disp = MI->getOperand(2).getImm();
3162 unsigned Src2 = MI->getOperand(3).getReg();
3163 unsigned BitShift = (IsSubWord ? MI->getOperand(4).getReg() : 0);
3164 unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0);
3165 DebugLoc DL = MI->getDebugLoc();
3167 BitSize = MI->getOperand(6).getImm();
3169 // Subword operations use 32-bit registers.
3170 const TargetRegisterClass *RC = (BitSize <= 32 ?
3171 &SystemZ::GR32BitRegClass :
3172 &SystemZ::GR64BitRegClass);
3173 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
3174 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
3176 // Get the right opcodes for the displacement.
3177 LOpcode = TII->getOpcodeForOffset(LOpcode, Disp);
3178 CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
3179 assert(LOpcode && CSOpcode && "Displacement out of range");
3181 // Create virtual registers for temporary results.
3182 unsigned OrigVal = MRI.createVirtualRegister(RC);
3183 unsigned OldVal = MRI.createVirtualRegister(RC);
3184 unsigned NewVal = MRI.createVirtualRegister(RC);
3185 unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
3186 unsigned RotatedAltVal = (IsSubWord ? MRI.createVirtualRegister(RC) : Src2);
3187 unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
3189 // Insert 3 basic blocks for the loop.
3190 MachineBasicBlock *StartMBB = MBB;
3191 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
3192 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
3193 MachineBasicBlock *UseAltMBB = emitBlockAfter(LoopMBB);
3194 MachineBasicBlock *UpdateMBB = emitBlockAfter(UseAltMBB);
3198 // %OrigVal = L Disp(%Base)
3199 // # fall through to LoopMMB
3201 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
3202 .addOperand(Base).addImm(Disp).addReg(0);
3203 MBB->addSuccessor(LoopMBB);
3206 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, UpdateMBB ]
3207 // %RotatedOldVal = RLL %OldVal, 0(%BitShift)
3208 // CompareOpcode %RotatedOldVal, %Src2
3209 // BRC KeepOldMask, UpdateMBB
3211 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
3212 .addReg(OrigVal).addMBB(StartMBB)
3213 .addReg(Dest).addMBB(UpdateMBB);
3215 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
3216 .addReg(OldVal).addReg(BitShift).addImm(0);
3217 BuildMI(MBB, DL, TII->get(CompareOpcode))
3218 .addReg(RotatedOldVal).addReg(Src2);
3219 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
3220 .addImm(SystemZ::CCMASK_ICMP).addImm(KeepOldMask).addMBB(UpdateMBB);
3221 MBB->addSuccessor(UpdateMBB);
3222 MBB->addSuccessor(UseAltMBB);
3225 // %RotatedAltVal = RISBG %RotatedOldVal, %Src2, 32, 31 + BitSize, 0
3226 // # fall through to UpdateMMB
3229 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedAltVal)
3230 .addReg(RotatedOldVal).addReg(Src2)
3231 .addImm(32).addImm(31 + BitSize).addImm(0);
3232 MBB->addSuccessor(UpdateMBB);
3235 // %RotatedNewVal = PHI [ %RotatedOldVal, LoopMBB ],
3236 // [ %RotatedAltVal, UseAltMBB ]
3237 // %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
3238 // %Dest = CS %OldVal, %NewVal, Disp(%Base)
3240 // # fall through to DoneMMB
3242 BuildMI(MBB, DL, TII->get(SystemZ::PHI), RotatedNewVal)
3243 .addReg(RotatedOldVal).addMBB(LoopMBB)
3244 .addReg(RotatedAltVal).addMBB(UseAltMBB);
3246 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
3247 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
3248 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
3249 .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
3250 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
3251 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
3252 MBB->addSuccessor(LoopMBB);
3253 MBB->addSuccessor(DoneMBB);
3255 MI->eraseFromParent();
3259 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_CMP_SWAPW
3262 SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr *MI,
3263 MachineBasicBlock *MBB) const {
3264 MachineFunction &MF = *MBB->getParent();
3265 const SystemZInstrInfo *TII =
3266 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
3267 MachineRegisterInfo &MRI = MF.getRegInfo();
3269 // Extract the operands. Base can be a register or a frame index.
3270 unsigned Dest = MI->getOperand(0).getReg();
3271 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
3272 int64_t Disp = MI->getOperand(2).getImm();
3273 unsigned OrigCmpVal = MI->getOperand(3).getReg();
3274 unsigned OrigSwapVal = MI->getOperand(4).getReg();
3275 unsigned BitShift = MI->getOperand(5).getReg();
3276 unsigned NegBitShift = MI->getOperand(6).getReg();
3277 int64_t BitSize = MI->getOperand(7).getImm();
3278 DebugLoc DL = MI->getDebugLoc();
3280 const TargetRegisterClass *RC = &SystemZ::GR32BitRegClass;
3282 // Get the right opcodes for the displacement.
3283 unsigned LOpcode = TII->getOpcodeForOffset(SystemZ::L, Disp);
3284 unsigned CSOpcode = TII->getOpcodeForOffset(SystemZ::CS, Disp);
3285 assert(LOpcode && CSOpcode && "Displacement out of range");
3287 // Create virtual registers for temporary results.
3288 unsigned OrigOldVal = MRI.createVirtualRegister(RC);
3289 unsigned OldVal = MRI.createVirtualRegister(RC);
3290 unsigned CmpVal = MRI.createVirtualRegister(RC);
3291 unsigned SwapVal = MRI.createVirtualRegister(RC);
3292 unsigned StoreVal = MRI.createVirtualRegister(RC);
3293 unsigned RetryOldVal = MRI.createVirtualRegister(RC);
3294 unsigned RetryCmpVal = MRI.createVirtualRegister(RC);
3295 unsigned RetrySwapVal = MRI.createVirtualRegister(RC);
3297 // Insert 2 basic blocks for the loop.
3298 MachineBasicBlock *StartMBB = MBB;
3299 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
3300 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
3301 MachineBasicBlock *SetMBB = emitBlockAfter(LoopMBB);
3305 // %OrigOldVal = L Disp(%Base)
3306 // # fall through to LoopMMB
3308 BuildMI(MBB, DL, TII->get(LOpcode), OrigOldVal)
3309 .addOperand(Base).addImm(Disp).addReg(0);
3310 MBB->addSuccessor(LoopMBB);
3313 // %OldVal = phi [ %OrigOldVal, EntryBB ], [ %RetryOldVal, SetMBB ]
3314 // %CmpVal = phi [ %OrigCmpVal, EntryBB ], [ %RetryCmpVal, SetMBB ]
3315 // %SwapVal = phi [ %OrigSwapVal, EntryBB ], [ %RetrySwapVal, SetMBB ]
3316 // %Dest = RLL %OldVal, BitSize(%BitShift)
3317 // ^^ The low BitSize bits contain the field
3319 // %RetryCmpVal = RISBG32 %CmpVal, %Dest, 32, 63-BitSize, 0
3320 // ^^ Replace the upper 32-BitSize bits of the
3321 // comparison value with those that we loaded,
3322 // so that we can use a full word comparison.
3323 // CR %Dest, %RetryCmpVal
3325 // # Fall through to SetMBB
3327 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
3328 .addReg(OrigOldVal).addMBB(StartMBB)
3329 .addReg(RetryOldVal).addMBB(SetMBB);
3330 BuildMI(MBB, DL, TII->get(SystemZ::PHI), CmpVal)
3331 .addReg(OrigCmpVal).addMBB(StartMBB)
3332 .addReg(RetryCmpVal).addMBB(SetMBB);
3333 BuildMI(MBB, DL, TII->get(SystemZ::PHI), SwapVal)
3334 .addReg(OrigSwapVal).addMBB(StartMBB)
3335 .addReg(RetrySwapVal).addMBB(SetMBB);
3336 BuildMI(MBB, DL, TII->get(SystemZ::RLL), Dest)
3337 .addReg(OldVal).addReg(BitShift).addImm(BitSize);
3338 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetryCmpVal)
3339 .addReg(CmpVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
3340 BuildMI(MBB, DL, TII->get(SystemZ::CR))
3341 .addReg(Dest).addReg(RetryCmpVal);
3342 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
3343 .addImm(SystemZ::CCMASK_ICMP)
3344 .addImm(SystemZ::CCMASK_CMP_NE).addMBB(DoneMBB);
3345 MBB->addSuccessor(DoneMBB);
3346 MBB->addSuccessor(SetMBB);
3349 // %RetrySwapVal = RISBG32 %SwapVal, %Dest, 32, 63-BitSize, 0
3350 // ^^ Replace the upper 32-BitSize bits of the new
3351 // value with those that we loaded.
3352 // %StoreVal = RLL %RetrySwapVal, -BitSize(%NegBitShift)
3353 // ^^ Rotate the new field to its proper position.
3354 // %RetryOldVal = CS %Dest, %StoreVal, Disp(%Base)
3356 // # fall through to ExitMMB
3358 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetrySwapVal)
3359 .addReg(SwapVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
3360 BuildMI(MBB, DL, TII->get(SystemZ::RLL), StoreVal)
3361 .addReg(RetrySwapVal).addReg(NegBitShift).addImm(-BitSize);
3362 BuildMI(MBB, DL, TII->get(CSOpcode), RetryOldVal)
3363 .addReg(OldVal).addReg(StoreVal).addOperand(Base).addImm(Disp);
3364 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
3365 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
3366 MBB->addSuccessor(LoopMBB);
3367 MBB->addSuccessor(DoneMBB);
3369 MI->eraseFromParent();
3373 // Emit an extension from a GR32 or GR64 to a GR128. ClearEven is true
3374 // if the high register of the GR128 value must be cleared or false if
3375 // it's "don't care". SubReg is subreg_l32 when extending a GR32
3376 // and subreg_l64 when extending a GR64.
3378 SystemZTargetLowering::emitExt128(MachineInstr *MI,
3379 MachineBasicBlock *MBB,
3380 bool ClearEven, unsigned SubReg) const {
3381 MachineFunction &MF = *MBB->getParent();
3382 const SystemZInstrInfo *TII =
3383 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
3384 MachineRegisterInfo &MRI = MF.getRegInfo();
3385 DebugLoc DL = MI->getDebugLoc();
3387 unsigned Dest = MI->getOperand(0).getReg();
3388 unsigned Src = MI->getOperand(1).getReg();
3389 unsigned In128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
3391 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::IMPLICIT_DEF), In128);
3393 unsigned NewIn128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
3394 unsigned Zero64 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
3396 BuildMI(*MBB, MI, DL, TII->get(SystemZ::LLILL), Zero64)
3398 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), NewIn128)
3399 .addReg(In128).addReg(Zero64).addImm(SystemZ::subreg_h64);
3402 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dest)
3403 .addReg(In128).addReg(Src).addImm(SubReg);
3405 MI->eraseFromParent();
3410 SystemZTargetLowering::emitMemMemWrapper(MachineInstr *MI,
3411 MachineBasicBlock *MBB,
3412 unsigned Opcode) const {
3413 MachineFunction &MF = *MBB->getParent();
3414 const SystemZInstrInfo *TII =
3415 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
3416 MachineRegisterInfo &MRI = MF.getRegInfo();
3417 DebugLoc DL = MI->getDebugLoc();
3419 MachineOperand DestBase = earlyUseOperand(MI->getOperand(0));
3420 uint64_t DestDisp = MI->getOperand(1).getImm();
3421 MachineOperand SrcBase = earlyUseOperand(MI->getOperand(2));
3422 uint64_t SrcDisp = MI->getOperand(3).getImm();
3423 uint64_t Length = MI->getOperand(4).getImm();
3425 // When generating more than one CLC, all but the last will need to
3426 // branch to the end when a difference is found.
3427 MachineBasicBlock *EndMBB = (Length > 256 && Opcode == SystemZ::CLC ?
3428 splitBlockAfter(MI, MBB) : nullptr);
3430 // Check for the loop form, in which operand 5 is the trip count.
3431 if (MI->getNumExplicitOperands() > 5) {
3432 bool HaveSingleBase = DestBase.isIdenticalTo(SrcBase);
3434 uint64_t StartCountReg = MI->getOperand(5).getReg();
3435 uint64_t StartSrcReg = forceReg(MI, SrcBase, TII);
3436 uint64_t StartDestReg = (HaveSingleBase ? StartSrcReg :
3437 forceReg(MI, DestBase, TII));
3439 const TargetRegisterClass *RC = &SystemZ::ADDR64BitRegClass;
3440 uint64_t ThisSrcReg = MRI.createVirtualRegister(RC);
3441 uint64_t ThisDestReg = (HaveSingleBase ? ThisSrcReg :
3442 MRI.createVirtualRegister(RC));
3443 uint64_t NextSrcReg = MRI.createVirtualRegister(RC);
3444 uint64_t NextDestReg = (HaveSingleBase ? NextSrcReg :
3445 MRI.createVirtualRegister(RC));
3447 RC = &SystemZ::GR64BitRegClass;
3448 uint64_t ThisCountReg = MRI.createVirtualRegister(RC);
3449 uint64_t NextCountReg = MRI.createVirtualRegister(RC);
3451 MachineBasicBlock *StartMBB = MBB;
3452 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
3453 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
3454 MachineBasicBlock *NextMBB = (EndMBB ? emitBlockAfter(LoopMBB) : LoopMBB);
3457 // # fall through to LoopMMB
3458 MBB->addSuccessor(LoopMBB);
3461 // %ThisDestReg = phi [ %StartDestReg, StartMBB ],
3462 // [ %NextDestReg, NextMBB ]
3463 // %ThisSrcReg = phi [ %StartSrcReg, StartMBB ],
3464 // [ %NextSrcReg, NextMBB ]
3465 // %ThisCountReg = phi [ %StartCountReg, StartMBB ],
3466 // [ %NextCountReg, NextMBB ]
3467 // ( PFD 2, 768+DestDisp(%ThisDestReg) )
3468 // Opcode DestDisp(256,%ThisDestReg), SrcDisp(%ThisSrcReg)
3471 // The prefetch is used only for MVC. The JLH is used only for CLC.
3474 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisDestReg)
3475 .addReg(StartDestReg).addMBB(StartMBB)
3476 .addReg(NextDestReg).addMBB(NextMBB);
3477 if (!HaveSingleBase)
3478 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisSrcReg)
3479 .addReg(StartSrcReg).addMBB(StartMBB)
3480 .addReg(NextSrcReg).addMBB(NextMBB);
3481 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisCountReg)
3482 .addReg(StartCountReg).addMBB(StartMBB)
3483 .addReg(NextCountReg).addMBB(NextMBB);
3484 if (Opcode == SystemZ::MVC)
3485 BuildMI(MBB, DL, TII->get(SystemZ::PFD))
3486 .addImm(SystemZ::PFD_WRITE)
3487 .addReg(ThisDestReg).addImm(DestDisp + 768).addReg(0);
3488 BuildMI(MBB, DL, TII->get(Opcode))
3489 .addReg(ThisDestReg).addImm(DestDisp).addImm(256)
3490 .addReg(ThisSrcReg).addImm(SrcDisp);
3492 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
3493 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
3495 MBB->addSuccessor(EndMBB);
3496 MBB->addSuccessor(NextMBB);
3500 // %NextDestReg = LA 256(%ThisDestReg)
3501 // %NextSrcReg = LA 256(%ThisSrcReg)
3502 // %NextCountReg = AGHI %ThisCountReg, -1
3503 // CGHI %NextCountReg, 0
3505 // # fall through to DoneMMB
3507 // The AGHI, CGHI and JLH should be converted to BRCTG by later passes.
3510 BuildMI(MBB, DL, TII->get(SystemZ::LA), NextDestReg)
3511 .addReg(ThisDestReg).addImm(256).addReg(0);
3512 if (!HaveSingleBase)
3513 BuildMI(MBB, DL, TII->get(SystemZ::LA), NextSrcReg)
3514 .addReg(ThisSrcReg).addImm(256).addReg(0);
3515 BuildMI(MBB, DL, TII->get(SystemZ::AGHI), NextCountReg)
3516 .addReg(ThisCountReg).addImm(-1);
3517 BuildMI(MBB, DL, TII->get(SystemZ::CGHI))
3518 .addReg(NextCountReg).addImm(0);
3519 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
3520 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
3522 MBB->addSuccessor(LoopMBB);
3523 MBB->addSuccessor(DoneMBB);
3525 DestBase = MachineOperand::CreateReg(NextDestReg, false);
3526 SrcBase = MachineOperand::CreateReg(NextSrcReg, false);
3530 // Handle any remaining bytes with straight-line code.
3531 while (Length > 0) {
3532 uint64_t ThisLength = std::min(Length, uint64_t(256));
3533 // The previous iteration might have created out-of-range displacements.
3534 // Apply them using LAY if so.
3535 if (!isUInt<12>(DestDisp)) {
3536 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
3537 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LAY), Reg)
3538 .addOperand(DestBase).addImm(DestDisp).addReg(0);
3539 DestBase = MachineOperand::CreateReg(Reg, false);
3542 if (!isUInt<12>(SrcDisp)) {
3543 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
3544 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LAY), Reg)
3545 .addOperand(SrcBase).addImm(SrcDisp).addReg(0);
3546 SrcBase = MachineOperand::CreateReg(Reg, false);
3549 BuildMI(*MBB, MI, DL, TII->get(Opcode))
3550 .addOperand(DestBase).addImm(DestDisp).addImm(ThisLength)
3551 .addOperand(SrcBase).addImm(SrcDisp);
3552 DestDisp += ThisLength;
3553 SrcDisp += ThisLength;
3554 Length -= ThisLength;
3555 // If there's another CLC to go, branch to the end if a difference
3557 if (EndMBB && Length > 0) {
3558 MachineBasicBlock *NextMBB = splitBlockBefore(MI, MBB);
3559 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
3560 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
3562 MBB->addSuccessor(EndMBB);
3563 MBB->addSuccessor(NextMBB);
3568 MBB->addSuccessor(EndMBB);
3570 MBB->addLiveIn(SystemZ::CC);
3573 MI->eraseFromParent();
3577 // Decompose string pseudo-instruction MI into a loop that continually performs
3578 // Opcode until CC != 3.
3580 SystemZTargetLowering::emitStringWrapper(MachineInstr *MI,
3581 MachineBasicBlock *MBB,
3582 unsigned Opcode) const {
3583 MachineFunction &MF = *MBB->getParent();
3584 const SystemZInstrInfo *TII =
3585 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
3586 MachineRegisterInfo &MRI = MF.getRegInfo();
3587 DebugLoc DL = MI->getDebugLoc();
3589 uint64_t End1Reg = MI->getOperand(0).getReg();
3590 uint64_t Start1Reg = MI->getOperand(1).getReg();
3591 uint64_t Start2Reg = MI->getOperand(2).getReg();
3592 uint64_t CharReg = MI->getOperand(3).getReg();
3594 const TargetRegisterClass *RC = &SystemZ::GR64BitRegClass;
3595 uint64_t This1Reg = MRI.createVirtualRegister(RC);
3596 uint64_t This2Reg = MRI.createVirtualRegister(RC);
3597 uint64_t End2Reg = MRI.createVirtualRegister(RC);
3599 MachineBasicBlock *StartMBB = MBB;
3600 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
3601 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
3604 // # fall through to LoopMMB
3605 MBB->addSuccessor(LoopMBB);
3608 // %This1Reg = phi [ %Start1Reg, StartMBB ], [ %End1Reg, LoopMBB ]
3609 // %This2Reg = phi [ %Start2Reg, StartMBB ], [ %End2Reg, LoopMBB ]
3611 // %End1Reg, %End2Reg = CLST %This1Reg, %This2Reg -- uses R0L
3613 // # fall through to DoneMMB
3615 // The load of R0L can be hoisted by post-RA LICM.
3618 BuildMI(MBB, DL, TII->get(SystemZ::PHI), This1Reg)
3619 .addReg(Start1Reg).addMBB(StartMBB)
3620 .addReg(End1Reg).addMBB(LoopMBB);
3621 BuildMI(MBB, DL, TII->get(SystemZ::PHI), This2Reg)
3622 .addReg(Start2Reg).addMBB(StartMBB)
3623 .addReg(End2Reg).addMBB(LoopMBB);
3624 BuildMI(MBB, DL, TII->get(TargetOpcode::COPY), SystemZ::R0L).addReg(CharReg);
3625 BuildMI(MBB, DL, TII->get(Opcode))
3626 .addReg(End1Reg, RegState::Define).addReg(End2Reg, RegState::Define)
3627 .addReg(This1Reg).addReg(This2Reg);
3628 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
3629 .addImm(SystemZ::CCMASK_ANY).addImm(SystemZ::CCMASK_3).addMBB(LoopMBB);
3630 MBB->addSuccessor(LoopMBB);
3631 MBB->addSuccessor(DoneMBB);
3633 DoneMBB->addLiveIn(SystemZ::CC);
3635 MI->eraseFromParent();
3639 // Update TBEGIN instruction with final opcode and register clobbers.
3641 SystemZTargetLowering::emitTransactionBegin(MachineInstr *MI,
3642 MachineBasicBlock *MBB,
3644 bool NoFloat) const {
3645 MachineFunction &MF = *MBB->getParent();
3646 const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
3647 const SystemZInstrInfo *TII = Subtarget.getInstrInfo();
3650 MI->setDesc(TII->get(Opcode));
3652 // We cannot handle a TBEGIN that clobbers the stack or frame pointer.
3653 // Make sure to add the corresponding GRSM bits if they are missing.
3654 uint64_t Control = MI->getOperand(2).getImm();
3655 static const unsigned GPRControlBit[16] = {
3656 0x8000, 0x8000, 0x4000, 0x4000, 0x2000, 0x2000, 0x1000, 0x1000,
3657 0x0800, 0x0800, 0x0400, 0x0400, 0x0200, 0x0200, 0x0100, 0x0100
3659 Control |= GPRControlBit[15];
3661 Control |= GPRControlBit[11];
3662 MI->getOperand(2).setImm(Control);
3664 // Add GPR clobbers.
3665 for (int I = 0; I < 16; I++) {
3666 if ((Control & GPRControlBit[I]) == 0) {
3667 unsigned Reg = SystemZMC::GR64Regs[I];
3668 MI->addOperand(MachineOperand::CreateReg(Reg, true, true));
3672 // Add FPR clobbers.
3673 if (!NoFloat && (Control & 4) != 0) {
3674 for (int I = 0; I < 16; I++) {
3675 unsigned Reg = SystemZMC::FP64Regs[I];
3676 MI->addOperand(MachineOperand::CreateReg(Reg, true, true));
3683 MachineBasicBlock *SystemZTargetLowering::
3684 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const {
3685 switch (MI->getOpcode()) {
3686 case SystemZ::Select32Mux:
3687 case SystemZ::Select32:
3688 case SystemZ::SelectF32:
3689 case SystemZ::Select64:
3690 case SystemZ::SelectF64:
3691 case SystemZ::SelectF128:
3692 return emitSelect(MI, MBB);
3694 case SystemZ::CondStore8Mux:
3695 return emitCondStore(MI, MBB, SystemZ::STCMux, 0, false);
3696 case SystemZ::CondStore8MuxInv:
3697 return emitCondStore(MI, MBB, SystemZ::STCMux, 0, true);
3698 case SystemZ::CondStore16Mux:
3699 return emitCondStore(MI, MBB, SystemZ::STHMux, 0, false);
3700 case SystemZ::CondStore16MuxInv:
3701 return emitCondStore(MI, MBB, SystemZ::STHMux, 0, true);
3702 case SystemZ::CondStore8:
3703 return emitCondStore(MI, MBB, SystemZ::STC, 0, false);
3704 case SystemZ::CondStore8Inv:
3705 return emitCondStore(MI, MBB, SystemZ::STC, 0, true);
3706 case SystemZ::CondStore16:
3707 return emitCondStore(MI, MBB, SystemZ::STH, 0, false);
3708 case SystemZ::CondStore16Inv:
3709 return emitCondStore(MI, MBB, SystemZ::STH, 0, true);
3710 case SystemZ::CondStore32:
3711 return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, false);
3712 case SystemZ::CondStore32Inv:
3713 return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, true);
3714 case SystemZ::CondStore64:
3715 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, false);
3716 case SystemZ::CondStore64Inv:
3717 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, true);
3718 case SystemZ::CondStoreF32:
3719 return emitCondStore(MI, MBB, SystemZ::STE, 0, false);
3720 case SystemZ::CondStoreF32Inv:
3721 return emitCondStore(MI, MBB, SystemZ::STE, 0, true);
3722 case SystemZ::CondStoreF64:
3723 return emitCondStore(MI, MBB, SystemZ::STD, 0, false);
3724 case SystemZ::CondStoreF64Inv:
3725 return emitCondStore(MI, MBB, SystemZ::STD, 0, true);
3727 case SystemZ::AEXT128_64:
3728 return emitExt128(MI, MBB, false, SystemZ::subreg_l64);
3729 case SystemZ::ZEXT128_32:
3730 return emitExt128(MI, MBB, true, SystemZ::subreg_l32);
3731 case SystemZ::ZEXT128_64:
3732 return emitExt128(MI, MBB, true, SystemZ::subreg_l64);
3734 case SystemZ::ATOMIC_SWAPW:
3735 return emitAtomicLoadBinary(MI, MBB, 0, 0);
3736 case SystemZ::ATOMIC_SWAP_32:
3737 return emitAtomicLoadBinary(MI, MBB, 0, 32);
3738 case SystemZ::ATOMIC_SWAP_64:
3739 return emitAtomicLoadBinary(MI, MBB, 0, 64);
3741 case SystemZ::ATOMIC_LOADW_AR:
3742 return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 0);
3743 case SystemZ::ATOMIC_LOADW_AFI:
3744 return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 0);
3745 case SystemZ::ATOMIC_LOAD_AR:
3746 return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 32);
3747 case SystemZ::ATOMIC_LOAD_AHI:
3748 return emitAtomicLoadBinary(MI, MBB, SystemZ::AHI, 32);
3749 case SystemZ::ATOMIC_LOAD_AFI:
3750 return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 32);
3751 case SystemZ::ATOMIC_LOAD_AGR:
3752 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGR, 64);
3753 case SystemZ::ATOMIC_LOAD_AGHI:
3754 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGHI, 64);
3755 case SystemZ::ATOMIC_LOAD_AGFI:
3756 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGFI, 64);
3758 case SystemZ::ATOMIC_LOADW_SR:
3759 return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 0);
3760 case SystemZ::ATOMIC_LOAD_SR:
3761 return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 32);
3762 case SystemZ::ATOMIC_LOAD_SGR:
3763 return emitAtomicLoadBinary(MI, MBB, SystemZ::SGR, 64);
3765 case SystemZ::ATOMIC_LOADW_NR:
3766 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0);
3767 case SystemZ::ATOMIC_LOADW_NILH:
3768 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 0);
3769 case SystemZ::ATOMIC_LOAD_NR:
3770 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32);
3771 case SystemZ::ATOMIC_LOAD_NILL:
3772 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 32);
3773 case SystemZ::ATOMIC_LOAD_NILH:
3774 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 32);
3775 case SystemZ::ATOMIC_LOAD_NILF:
3776 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 32);
3777 case SystemZ::ATOMIC_LOAD_NGR:
3778 return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64);
3779 case SystemZ::ATOMIC_LOAD_NILL64:
3780 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL64, 64);
3781 case SystemZ::ATOMIC_LOAD_NILH64:
3782 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH64, 64);
3783 case SystemZ::ATOMIC_LOAD_NIHL64:
3784 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL64, 64);
3785 case SystemZ::ATOMIC_LOAD_NIHH64:
3786 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH64, 64);
3787 case SystemZ::ATOMIC_LOAD_NILF64:
3788 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF64, 64);
3789 case SystemZ::ATOMIC_LOAD_NIHF64:
3790 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF64, 64);
3792 case SystemZ::ATOMIC_LOADW_OR:
3793 return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 0);
3794 case SystemZ::ATOMIC_LOADW_OILH:
3795 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 0);
3796 case SystemZ::ATOMIC_LOAD_OR:
3797 return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 32);
3798 case SystemZ::ATOMIC_LOAD_OILL:
3799 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL, 32);
3800 case SystemZ::ATOMIC_LOAD_OILH:
3801 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 32);
3802 case SystemZ::ATOMIC_LOAD_OILF:
3803 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF, 32);
3804 case SystemZ::ATOMIC_LOAD_OGR:
3805 return emitAtomicLoadBinary(MI, MBB, SystemZ::OGR, 64);
3806 case SystemZ::ATOMIC_LOAD_OILL64:
3807 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL64, 64);
3808 case SystemZ::ATOMIC_LOAD_OILH64:
3809 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH64, 64);
3810 case SystemZ::ATOMIC_LOAD_OIHL64:
3811 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHL64, 64);
3812 case SystemZ::ATOMIC_LOAD_OIHH64:
3813 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHH64, 64);
3814 case SystemZ::ATOMIC_LOAD_OILF64:
3815 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF64, 64);
3816 case SystemZ::ATOMIC_LOAD_OIHF64:
3817 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHF64, 64);
3819 case SystemZ::ATOMIC_LOADW_XR:
3820 return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 0);
3821 case SystemZ::ATOMIC_LOADW_XILF:
3822 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 0);
3823 case SystemZ::ATOMIC_LOAD_XR:
3824 return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 32);
3825 case SystemZ::ATOMIC_LOAD_XILF:
3826 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 32);
3827 case SystemZ::ATOMIC_LOAD_XGR:
3828 return emitAtomicLoadBinary(MI, MBB, SystemZ::XGR, 64);
3829 case SystemZ::ATOMIC_LOAD_XILF64:
3830 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF64, 64);
3831 case SystemZ::ATOMIC_LOAD_XIHF64:
3832 return emitAtomicLoadBinary(MI, MBB, SystemZ::XIHF64, 64);
3834 case SystemZ::ATOMIC_LOADW_NRi:
3835 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0, true);
3836 case SystemZ::ATOMIC_LOADW_NILHi:
3837 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 0, true);
3838 case SystemZ::ATOMIC_LOAD_NRi:
3839 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32, true);
3840 case SystemZ::ATOMIC_LOAD_NILLi:
3841 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 32, true);
3842 case SystemZ::ATOMIC_LOAD_NILHi:
3843 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 32, true);
3844 case SystemZ::ATOMIC_LOAD_NILFi:
3845 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 32, true);
3846 case SystemZ::ATOMIC_LOAD_NGRi:
3847 return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64, true);
3848 case SystemZ::ATOMIC_LOAD_NILL64i:
3849 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL64, 64, true);
3850 case SystemZ::ATOMIC_LOAD_NILH64i:
3851 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH64, 64, true);
3852 case SystemZ::ATOMIC_LOAD_NIHL64i:
3853 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL64, 64, true);
3854 case SystemZ::ATOMIC_LOAD_NIHH64i:
3855 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH64, 64, true);
3856 case SystemZ::ATOMIC_LOAD_NILF64i:
3857 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF64, 64, true);
3858 case SystemZ::ATOMIC_LOAD_NIHF64i:
3859 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF64, 64, true);
3861 case SystemZ::ATOMIC_LOADW_MIN:
3862 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
3863 SystemZ::CCMASK_CMP_LE, 0);
3864 case SystemZ::ATOMIC_LOAD_MIN_32:
3865 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
3866 SystemZ::CCMASK_CMP_LE, 32);
3867 case SystemZ::ATOMIC_LOAD_MIN_64:
3868 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
3869 SystemZ::CCMASK_CMP_LE, 64);
3871 case SystemZ::ATOMIC_LOADW_MAX:
3872 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
3873 SystemZ::CCMASK_CMP_GE, 0);
3874 case SystemZ::ATOMIC_LOAD_MAX_32:
3875 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
3876 SystemZ::CCMASK_CMP_GE, 32);
3877 case SystemZ::ATOMIC_LOAD_MAX_64:
3878 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
3879 SystemZ::CCMASK_CMP_GE, 64);
3881 case SystemZ::ATOMIC_LOADW_UMIN:
3882 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
3883 SystemZ::CCMASK_CMP_LE, 0);
3884 case SystemZ::ATOMIC_LOAD_UMIN_32:
3885 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
3886 SystemZ::CCMASK_CMP_LE, 32);
3887 case SystemZ::ATOMIC_LOAD_UMIN_64:
3888 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
3889 SystemZ::CCMASK_CMP_LE, 64);
3891 case SystemZ::ATOMIC_LOADW_UMAX:
3892 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
3893 SystemZ::CCMASK_CMP_GE, 0);
3894 case SystemZ::ATOMIC_LOAD_UMAX_32:
3895 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
3896 SystemZ::CCMASK_CMP_GE, 32);
3897 case SystemZ::ATOMIC_LOAD_UMAX_64:
3898 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
3899 SystemZ::CCMASK_CMP_GE, 64);
3901 case SystemZ::ATOMIC_CMP_SWAPW:
3902 return emitAtomicCmpSwapW(MI, MBB);
3903 case SystemZ::MVCSequence:
3904 case SystemZ::MVCLoop:
3905 return emitMemMemWrapper(MI, MBB, SystemZ::MVC);
3906 case SystemZ::NCSequence:
3907 case SystemZ::NCLoop:
3908 return emitMemMemWrapper(MI, MBB, SystemZ::NC);
3909 case SystemZ::OCSequence:
3910 case SystemZ::OCLoop:
3911 return emitMemMemWrapper(MI, MBB, SystemZ::OC);
3912 case SystemZ::XCSequence:
3913 case SystemZ::XCLoop:
3914 return emitMemMemWrapper(MI, MBB, SystemZ::XC);
3915 case SystemZ::CLCSequence:
3916 case SystemZ::CLCLoop:
3917 return emitMemMemWrapper(MI, MBB, SystemZ::CLC);
3918 case SystemZ::CLSTLoop:
3919 return emitStringWrapper(MI, MBB, SystemZ::CLST);
3920 case SystemZ::MVSTLoop:
3921 return emitStringWrapper(MI, MBB, SystemZ::MVST);
3922 case SystemZ::SRSTLoop:
3923 return emitStringWrapper(MI, MBB, SystemZ::SRST);
3924 case SystemZ::TBEGIN:
3925 return emitTransactionBegin(MI, MBB, SystemZ::TBEGIN, false);
3926 case SystemZ::TBEGIN_nofloat:
3927 return emitTransactionBegin(MI, MBB, SystemZ::TBEGIN, true);
3928 case SystemZ::TBEGINC:
3929 return emitTransactionBegin(MI, MBB, SystemZ::TBEGINC, true);
3931 llvm_unreachable("Unexpected instr type to insert");