1 //===-- SystemZISelLowering.cpp - SystemZ DAG lowering implementation -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SystemZTargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "systemz-lower"
16 #include "SystemZISelLowering.h"
17 #include "SystemZCallingConv.h"
18 #include "SystemZConstantPoolValue.h"
19 #include "SystemZMachineFunctionInfo.h"
20 #include "SystemZTargetMachine.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30 // Represents a sequence for extracting a 0/1 value from an IPM result:
31 // (((X ^ XORValue) + AddValue) >> Bit)
32 struct IPMConversion {
33 IPMConversion(unsigned xorValue, int64_t addValue, unsigned bit)
34 : XORValue(xorValue), AddValue(addValue), Bit(bit) {}
41 // Represents information about a comparison.
43 Comparison(SDValue Op0In, SDValue Op1In)
44 : Op0(Op0In), Op1(Op1In), Opcode(0), ICmpType(0), CCValid(0), CCMask(0) {}
46 // The operands to the comparison.
49 // The opcode that should be used to compare Op0 and Op1.
52 // A SystemZICMP value. Only used for integer comparisons.
55 // The mask of CC values that Opcode can produce.
58 // The mask of CC values for which the original condition is true.
61 } // end anonymous namespace
63 // Classify VT as either 32 or 64 bit.
64 static bool is32Bit(EVT VT) {
65 switch (VT.getSimpleVT().SimpleTy) {
71 llvm_unreachable("Unsupported type");
75 // Return a version of MachineOperand that can be safely used before the
77 static MachineOperand earlyUseOperand(MachineOperand Op) {
83 SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm)
84 : TargetLowering(tm, new TargetLoweringObjectFileELF()),
85 Subtarget(*tm.getSubtargetImpl()), TM(tm) {
86 MVT PtrVT = getPointerTy();
88 // Set up the register classes.
89 if (Subtarget.hasHighWord())
90 addRegisterClass(MVT::i32, &SystemZ::GRX32BitRegClass);
92 addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass);
93 addRegisterClass(MVT::i64, &SystemZ::GR64BitRegClass);
94 addRegisterClass(MVT::f32, &SystemZ::FP32BitRegClass);
95 addRegisterClass(MVT::f64, &SystemZ::FP64BitRegClass);
96 addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass);
98 // Compute derived properties from the register classes
99 computeRegisterProperties();
101 // Set up special registers.
102 setExceptionPointerRegister(SystemZ::R6D);
103 setExceptionSelectorRegister(SystemZ::R7D);
104 setStackPointerRegisterToSaveRestore(SystemZ::R15D);
106 // TODO: It may be better to default to latency-oriented scheduling, however
107 // LLVM's current latency-oriented scheduler can't handle physreg definitions
108 // such as SystemZ has with CC, so set this to the register-pressure
109 // scheduler, because it can.
110 setSchedulingPreference(Sched::RegPressure);
112 setBooleanContents(ZeroOrOneBooleanContent);
113 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
115 // Instructions are strings of 2-byte aligned 2-byte values.
116 setMinFunctionAlignment(2);
118 // Handle operations that are handled in a similar way for all types.
119 for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
120 I <= MVT::LAST_FP_VALUETYPE;
122 MVT VT = MVT::SimpleValueType(I);
123 if (isTypeLegal(VT)) {
124 // Lower SET_CC into an IPM-based sequence.
125 setOperationAction(ISD::SETCC, VT, Custom);
127 // Expand SELECT(C, A, B) into SELECT_CC(X, 0, A, B, NE).
128 setOperationAction(ISD::SELECT, VT, Expand);
130 // Lower SELECT_CC and BR_CC into separate comparisons and branches.
131 setOperationAction(ISD::SELECT_CC, VT, Custom);
132 setOperationAction(ISD::BR_CC, VT, Custom);
136 // Expand jump table branches as address arithmetic followed by an
138 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
140 // Expand BRCOND into a BR_CC (see above).
141 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
143 // Handle integer types.
144 for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
145 I <= MVT::LAST_INTEGER_VALUETYPE;
147 MVT VT = MVT::SimpleValueType(I);
148 if (isTypeLegal(VT)) {
149 // Expand individual DIV and REMs into DIVREMs.
150 setOperationAction(ISD::SDIV, VT, Expand);
151 setOperationAction(ISD::UDIV, VT, Expand);
152 setOperationAction(ISD::SREM, VT, Expand);
153 setOperationAction(ISD::UREM, VT, Expand);
154 setOperationAction(ISD::SDIVREM, VT, Custom);
155 setOperationAction(ISD::UDIVREM, VT, Custom);
157 // Lower ATOMIC_LOAD and ATOMIC_STORE into normal volatile loads and
158 // stores, putting a serialization instruction after the stores.
159 setOperationAction(ISD::ATOMIC_LOAD, VT, Custom);
160 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
162 // Lower ATOMIC_LOAD_SUB into ATOMIC_LOAD_ADD if LAA and LAAG are
163 // available, or if the operand is constant.
164 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
166 // No special instructions for these.
167 setOperationAction(ISD::CTPOP, VT, Expand);
168 setOperationAction(ISD::CTTZ, VT, Expand);
169 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
170 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
171 setOperationAction(ISD::ROTR, VT, Expand);
173 // Use *MUL_LOHI where possible instead of MULH*.
174 setOperationAction(ISD::MULHS, VT, Expand);
175 setOperationAction(ISD::MULHU, VT, Expand);
176 setOperationAction(ISD::SMUL_LOHI, VT, Custom);
177 setOperationAction(ISD::UMUL_LOHI, VT, Custom);
179 // Only z196 and above have native support for conversions to unsigned.
180 if (!Subtarget.hasFPExtension())
181 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
185 // Type legalization will convert 8- and 16-bit atomic operations into
186 // forms that operate on i32s (but still keeping the original memory VT).
187 // Lower them into full i32 operations.
188 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Custom);
189 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Custom);
190 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
191 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Custom);
192 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Custom);
193 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Custom);
194 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Custom);
195 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Custom);
196 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Custom);
197 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Custom);
198 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Custom);
199 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
201 // z10 has instructions for signed but not unsigned FP conversion.
202 // Handle unsigned 32-bit types as signed 64-bit types.
203 if (!Subtarget.hasFPExtension()) {
204 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote);
205 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
208 // We have native support for a 64-bit CTLZ, via FLOGR.
209 setOperationAction(ISD::CTLZ, MVT::i32, Promote);
210 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
212 // Give LowerOperation the chance to replace 64-bit ORs with subregs.
213 setOperationAction(ISD::OR, MVT::i64, Custom);
215 // FIXME: Can we support these natively?
216 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
217 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
218 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
220 // We have native instructions for i8, i16 and i32 extensions, but not i1.
221 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
222 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
223 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
224 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
226 // Handle the various types of symbolic address.
227 setOperationAction(ISD::ConstantPool, PtrVT, Custom);
228 setOperationAction(ISD::GlobalAddress, PtrVT, Custom);
229 setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom);
230 setOperationAction(ISD::BlockAddress, PtrVT, Custom);
231 setOperationAction(ISD::JumpTable, PtrVT, Custom);
233 // We need to handle dynamic allocations specially because of the
234 // 160-byte area at the bottom of the stack.
235 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
237 // Use custom expanders so that we can force the function to use
239 setOperationAction(ISD::STACKSAVE, MVT::Other, Custom);
240 setOperationAction(ISD::STACKRESTORE, MVT::Other, Custom);
242 // Handle prefetches with PFD or PFDRL.
243 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
245 // Handle floating-point types.
246 for (unsigned I = MVT::FIRST_FP_VALUETYPE;
247 I <= MVT::LAST_FP_VALUETYPE;
249 MVT VT = MVT::SimpleValueType(I);
250 if (isTypeLegal(VT)) {
251 // We can use FI for FRINT.
252 setOperationAction(ISD::FRINT, VT, Legal);
254 // We can use the extended form of FI for other rounding operations.
255 if (Subtarget.hasFPExtension()) {
256 setOperationAction(ISD::FNEARBYINT, VT, Legal);
257 setOperationAction(ISD::FFLOOR, VT, Legal);
258 setOperationAction(ISD::FCEIL, VT, Legal);
259 setOperationAction(ISD::FTRUNC, VT, Legal);
260 setOperationAction(ISD::FROUND, VT, Legal);
263 // No special instructions for these.
264 setOperationAction(ISD::FSIN, VT, Expand);
265 setOperationAction(ISD::FCOS, VT, Expand);
266 setOperationAction(ISD::FREM, VT, Expand);
270 // We have fused multiply-addition for f32 and f64 but not f128.
271 setOperationAction(ISD::FMA, MVT::f32, Legal);
272 setOperationAction(ISD::FMA, MVT::f64, Legal);
273 setOperationAction(ISD::FMA, MVT::f128, Expand);
275 // Needed so that we don't try to implement f128 constant loads using
276 // a load-and-extend of a f80 constant (in cases where the constant
277 // would fit in an f80).
278 setLoadExtAction(ISD::EXTLOAD, MVT::f80, Expand);
280 // Floating-point truncation and stores need to be done separately.
281 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
282 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
283 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
285 // We have 64-bit FPR<->GPR moves, but need special handling for
287 setOperationAction(ISD::BITCAST, MVT::i32, Custom);
288 setOperationAction(ISD::BITCAST, MVT::f32, Custom);
290 // VASTART and VACOPY need to deal with the SystemZ-specific varargs
291 // structure, but VAEND is a no-op.
292 setOperationAction(ISD::VASTART, MVT::Other, Custom);
293 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
294 setOperationAction(ISD::VAEND, MVT::Other, Expand);
296 // Codes for which we want to perform some z-specific combinations.
297 setTargetDAGCombine(ISD::SIGN_EXTEND);
299 // We want to use MVC in preference to even a single load/store pair.
300 MaxStoresPerMemcpy = 0;
301 MaxStoresPerMemcpyOptSize = 0;
303 // The main memset sequence is a byte store followed by an MVC.
304 // Two STC or MV..I stores win over that, but the kind of fused stores
305 // generated by target-independent code don't when the byte value is
306 // variable. E.g. "STC <reg>;MHI <reg>,257;STH <reg>" is not better
307 // than "STC;MVC". Handle the choice in target-specific code instead.
308 MaxStoresPerMemset = 0;
309 MaxStoresPerMemsetOptSize = 0;
312 EVT SystemZTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
315 return VT.changeVectorElementTypeToInteger();
318 bool SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
319 VT = VT.getScalarType();
324 switch (VT.getSimpleVT().SimpleTy) {
337 bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
338 // We can load zero using LZ?R and negative zero using LZ?R;LC?BR.
339 return Imm.isZero() || Imm.isNegZero();
342 bool SystemZTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
345 // Unaligned accesses should never be slower than the expanded version.
346 // We check specifically for aligned accesses in the few cases where
347 // they are required.
353 bool SystemZTargetLowering::isLegalAddressingMode(const AddrMode &AM,
355 // Punt on globals for now, although they can be used in limited
356 // RELATIVE LONG cases.
360 // Require a 20-bit signed offset.
361 if (!isInt<20>(AM.BaseOffs))
364 // Indexing is OK but no scale factor can be applied.
365 return AM.Scale == 0 || AM.Scale == 1;
368 bool SystemZTargetLowering::isTruncateFree(Type *FromType, Type *ToType) const {
369 if (!FromType->isIntegerTy() || !ToType->isIntegerTy())
371 unsigned FromBits = FromType->getPrimitiveSizeInBits();
372 unsigned ToBits = ToType->getPrimitiveSizeInBits();
373 return FromBits > ToBits;
376 bool SystemZTargetLowering::isTruncateFree(EVT FromVT, EVT ToVT) const {
377 if (!FromVT.isInteger() || !ToVT.isInteger())
379 unsigned FromBits = FromVT.getSizeInBits();
380 unsigned ToBits = ToVT.getSizeInBits();
381 return FromBits > ToBits;
384 //===----------------------------------------------------------------------===//
385 // Inline asm support
386 //===----------------------------------------------------------------------===//
388 TargetLowering::ConstraintType
389 SystemZTargetLowering::getConstraintType(const std::string &Constraint) const {
390 if (Constraint.size() == 1) {
391 switch (Constraint[0]) {
392 case 'a': // Address register
393 case 'd': // Data register (equivalent to 'r')
394 case 'f': // Floating-point register
395 case 'h': // High-part register
396 case 'r': // General-purpose register
397 return C_RegisterClass;
399 case 'Q': // Memory with base and unsigned 12-bit displacement
400 case 'R': // Likewise, plus an index
401 case 'S': // Memory with base and signed 20-bit displacement
402 case 'T': // Likewise, plus an index
403 case 'm': // Equivalent to 'T'.
406 case 'I': // Unsigned 8-bit constant
407 case 'J': // Unsigned 12-bit constant
408 case 'K': // Signed 16-bit constant
409 case 'L': // Signed 20-bit displacement (on all targets we support)
410 case 'M': // 0x7fffffff
417 return TargetLowering::getConstraintType(Constraint);
420 TargetLowering::ConstraintWeight SystemZTargetLowering::
421 getSingleConstraintMatchWeight(AsmOperandInfo &info,
422 const char *constraint) const {
423 ConstraintWeight weight = CW_Invalid;
424 Value *CallOperandVal = info.CallOperandVal;
425 // If we don't have a value, we can't do a match,
426 // but allow it at the lowest weight.
427 if (CallOperandVal == NULL)
429 Type *type = CallOperandVal->getType();
430 // Look at the constraint type.
431 switch (*constraint) {
433 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
436 case 'a': // Address register
437 case 'd': // Data register (equivalent to 'r')
438 case 'h': // High-part register
439 case 'r': // General-purpose register
440 if (CallOperandVal->getType()->isIntegerTy())
441 weight = CW_Register;
444 case 'f': // Floating-point register
445 if (type->isFloatingPointTy())
446 weight = CW_Register;
449 case 'I': // Unsigned 8-bit constant
450 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
451 if (isUInt<8>(C->getZExtValue()))
452 weight = CW_Constant;
455 case 'J': // Unsigned 12-bit constant
456 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
457 if (isUInt<12>(C->getZExtValue()))
458 weight = CW_Constant;
461 case 'K': // Signed 16-bit constant
462 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
463 if (isInt<16>(C->getSExtValue()))
464 weight = CW_Constant;
467 case 'L': // Signed 20-bit displacement (on all targets we support)
468 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
469 if (isInt<20>(C->getSExtValue()))
470 weight = CW_Constant;
473 case 'M': // 0x7fffffff
474 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
475 if (C->getZExtValue() == 0x7fffffff)
476 weight = CW_Constant;
482 // Parse a "{tNNN}" register constraint for which the register type "t"
483 // has already been verified. MC is the class associated with "t" and
484 // Map maps 0-based register numbers to LLVM register numbers.
485 static std::pair<unsigned, const TargetRegisterClass *>
486 parseRegisterNumber(const std::string &Constraint,
487 const TargetRegisterClass *RC, const unsigned *Map) {
488 assert(*(Constraint.end()-1) == '}' && "Missing '}'");
489 if (isdigit(Constraint[2])) {
490 std::string Suffix(Constraint.data() + 2, Constraint.size() - 2);
491 unsigned Index = atoi(Suffix.c_str());
492 if (Index < 16 && Map[Index])
493 return std::make_pair(Map[Index], RC);
495 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
498 std::pair<unsigned, const TargetRegisterClass *> SystemZTargetLowering::
499 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const {
500 if (Constraint.size() == 1) {
501 // GCC Constraint Letters
502 switch (Constraint[0]) {
504 case 'd': // Data register (equivalent to 'r')
505 case 'r': // General-purpose register
507 return std::make_pair(0U, &SystemZ::GR64BitRegClass);
508 else if (VT == MVT::i128)
509 return std::make_pair(0U, &SystemZ::GR128BitRegClass);
510 return std::make_pair(0U, &SystemZ::GR32BitRegClass);
512 case 'a': // Address register
514 return std::make_pair(0U, &SystemZ::ADDR64BitRegClass);
515 else if (VT == MVT::i128)
516 return std::make_pair(0U, &SystemZ::ADDR128BitRegClass);
517 return std::make_pair(0U, &SystemZ::ADDR32BitRegClass);
519 case 'h': // High-part register (an LLVM extension)
520 return std::make_pair(0U, &SystemZ::GRH32BitRegClass);
522 case 'f': // Floating-point register
524 return std::make_pair(0U, &SystemZ::FP64BitRegClass);
525 else if (VT == MVT::f128)
526 return std::make_pair(0U, &SystemZ::FP128BitRegClass);
527 return std::make_pair(0U, &SystemZ::FP32BitRegClass);
530 if (Constraint[0] == '{') {
531 // We need to override the default register parsing for GPRs and FPRs
532 // because the interpretation depends on VT. The internal names of
533 // the registers are also different from the external names
534 // (F0D and F0S instead of F0, etc.).
535 if (Constraint[1] == 'r') {
537 return parseRegisterNumber(Constraint, &SystemZ::GR32BitRegClass,
538 SystemZMC::GR32Regs);
540 return parseRegisterNumber(Constraint, &SystemZ::GR128BitRegClass,
541 SystemZMC::GR128Regs);
542 return parseRegisterNumber(Constraint, &SystemZ::GR64BitRegClass,
543 SystemZMC::GR64Regs);
545 if (Constraint[1] == 'f') {
547 return parseRegisterNumber(Constraint, &SystemZ::FP32BitRegClass,
548 SystemZMC::FP32Regs);
550 return parseRegisterNumber(Constraint, &SystemZ::FP128BitRegClass,
551 SystemZMC::FP128Regs);
552 return parseRegisterNumber(Constraint, &SystemZ::FP64BitRegClass,
553 SystemZMC::FP64Regs);
556 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
559 void SystemZTargetLowering::
560 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
561 std::vector<SDValue> &Ops,
562 SelectionDAG &DAG) const {
563 // Only support length 1 constraints for now.
564 if (Constraint.length() == 1) {
565 switch (Constraint[0]) {
566 case 'I': // Unsigned 8-bit constant
567 if (auto *C = dyn_cast<ConstantSDNode>(Op))
568 if (isUInt<8>(C->getZExtValue()))
569 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
573 case 'J': // Unsigned 12-bit constant
574 if (auto *C = dyn_cast<ConstantSDNode>(Op))
575 if (isUInt<12>(C->getZExtValue()))
576 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
580 case 'K': // Signed 16-bit constant
581 if (auto *C = dyn_cast<ConstantSDNode>(Op))
582 if (isInt<16>(C->getSExtValue()))
583 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
587 case 'L': // Signed 20-bit displacement (on all targets we support)
588 if (auto *C = dyn_cast<ConstantSDNode>(Op))
589 if (isInt<20>(C->getSExtValue()))
590 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
594 case 'M': // 0x7fffffff
595 if (auto *C = dyn_cast<ConstantSDNode>(Op))
596 if (C->getZExtValue() == 0x7fffffff)
597 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
602 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
605 //===----------------------------------------------------------------------===//
606 // Calling conventions
607 //===----------------------------------------------------------------------===//
609 #include "SystemZGenCallingConv.inc"
611 bool SystemZTargetLowering::allowTruncateForTailCall(Type *FromType,
612 Type *ToType) const {
613 return isTruncateFree(FromType, ToType);
616 bool SystemZTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
617 if (!CI->isTailCall())
622 // Value is a value that has been passed to us in the location described by VA
623 // (and so has type VA.getLocVT()). Convert Value to VA.getValVT(), chaining
624 // any loads onto Chain.
625 static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDLoc DL,
626 CCValAssign &VA, SDValue Chain,
628 // If the argument has been promoted from a smaller type, insert an
629 // assertion to capture this.
630 if (VA.getLocInfo() == CCValAssign::SExt)
631 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value,
632 DAG.getValueType(VA.getValVT()));
633 else if (VA.getLocInfo() == CCValAssign::ZExt)
634 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value,
635 DAG.getValueType(VA.getValVT()));
638 Value = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Value);
639 else if (VA.getLocInfo() == CCValAssign::Indirect)
640 Value = DAG.getLoad(VA.getValVT(), DL, Chain, Value,
641 MachinePointerInfo(), false, false, false, 0);
643 assert(VA.getLocInfo() == CCValAssign::Full && "Unsupported getLocInfo");
647 // Value is a value of type VA.getValVT() that we need to copy into
648 // the location described by VA. Return a copy of Value converted to
649 // VA.getValVT(). The caller is responsible for handling indirect values.
650 static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDLoc DL,
651 CCValAssign &VA, SDValue Value) {
652 switch (VA.getLocInfo()) {
653 case CCValAssign::SExt:
654 return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value);
655 case CCValAssign::ZExt:
656 return DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Value);
657 case CCValAssign::AExt:
658 return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value);
659 case CCValAssign::Full:
662 llvm_unreachable("Unhandled getLocInfo()");
666 SDValue SystemZTargetLowering::
667 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
668 const SmallVectorImpl<ISD::InputArg> &Ins,
669 SDLoc DL, SelectionDAG &DAG,
670 SmallVectorImpl<SDValue> &InVals) const {
671 MachineFunction &MF = DAG.getMachineFunction();
672 MachineFrameInfo *MFI = MF.getFrameInfo();
673 MachineRegisterInfo &MRI = MF.getRegInfo();
674 SystemZMachineFunctionInfo *FuncInfo =
675 MF.getInfo<SystemZMachineFunctionInfo>();
676 auto *TFL = static_cast<const SystemZFrameLowering *>(TM.getFrameLowering());
678 // Assign locations to all of the incoming arguments.
679 SmallVector<CCValAssign, 16> ArgLocs;
680 CCState CCInfo(CallConv, IsVarArg, MF, TM, ArgLocs, *DAG.getContext());
681 CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ);
683 unsigned NumFixedGPRs = 0;
684 unsigned NumFixedFPRs = 0;
685 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
687 CCValAssign &VA = ArgLocs[I];
688 EVT LocVT = VA.getLocVT();
690 // Arguments passed in registers
691 const TargetRegisterClass *RC;
692 switch (LocVT.getSimpleVT().SimpleTy) {
694 // Integers smaller than i64 should be promoted to i64.
695 llvm_unreachable("Unexpected argument type");
698 RC = &SystemZ::GR32BitRegClass;
702 RC = &SystemZ::GR64BitRegClass;
706 RC = &SystemZ::FP32BitRegClass;
710 RC = &SystemZ::FP64BitRegClass;
714 unsigned VReg = MRI.createVirtualRegister(RC);
715 MRI.addLiveIn(VA.getLocReg(), VReg);
716 ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
718 assert(VA.isMemLoc() && "Argument not register or memory");
720 // Create the frame index object for this incoming parameter.
721 int FI = MFI->CreateFixedObject(LocVT.getSizeInBits() / 8,
722 VA.getLocMemOffset(), true);
724 // Create the SelectionDAG nodes corresponding to a load
725 // from this parameter. Unpromoted ints and floats are
726 // passed as right-justified 8-byte values.
727 EVT PtrVT = getPointerTy();
728 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
729 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
730 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4));
731 ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN,
732 MachinePointerInfo::getFixedStack(FI),
733 false, false, false, 0);
736 // Convert the value of the argument register into the value that's
738 InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, ArgValue));
742 // Save the number of non-varargs registers for later use by va_start, etc.
743 FuncInfo->setVarArgsFirstGPR(NumFixedGPRs);
744 FuncInfo->setVarArgsFirstFPR(NumFixedFPRs);
746 // Likewise the address (in the form of a frame index) of where the
747 // first stack vararg would be. The 1-byte size here is arbitrary.
748 int64_t StackSize = CCInfo.getNextStackOffset();
749 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize, true));
751 // ...and a similar frame index for the caller-allocated save area
752 // that will be used to store the incoming registers.
753 int64_t RegSaveOffset = TFL->getOffsetOfLocalArea();
754 unsigned RegSaveIndex = MFI->CreateFixedObject(1, RegSaveOffset, true);
755 FuncInfo->setRegSaveFrameIndex(RegSaveIndex);
757 // Store the FPR varargs in the reserved frame slots. (We store the
758 // GPRs as part of the prologue.)
759 if (NumFixedFPRs < SystemZ::NumArgFPRs) {
760 SDValue MemOps[SystemZ::NumArgFPRs];
761 for (unsigned I = NumFixedFPRs; I < SystemZ::NumArgFPRs; ++I) {
762 unsigned Offset = TFL->getRegSpillOffset(SystemZ::ArgFPRs[I]);
763 int FI = MFI->CreateFixedObject(8, RegSaveOffset + Offset, true);
764 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
765 unsigned VReg = MF.addLiveIn(SystemZ::ArgFPRs[I],
766 &SystemZ::FP64BitRegClass);
767 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f64);
768 MemOps[I] = DAG.getStore(ArgValue.getValue(1), DL, ArgValue, FIN,
769 MachinePointerInfo::getFixedStack(FI),
773 // Join the stores, which are independent of one another.
774 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
775 &MemOps[NumFixedFPRs],
776 SystemZ::NumArgFPRs - NumFixedFPRs);
783 static bool canUseSiblingCall(CCState ArgCCInfo,
784 SmallVectorImpl<CCValAssign> &ArgLocs) {
785 // Punt if there are any indirect or stack arguments, or if the call
786 // needs the call-saved argument register R6.
787 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
788 CCValAssign &VA = ArgLocs[I];
789 if (VA.getLocInfo() == CCValAssign::Indirect)
793 unsigned Reg = VA.getLocReg();
794 if (Reg == SystemZ::R6H || Reg == SystemZ::R6L || Reg == SystemZ::R6D)
801 SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
802 SmallVectorImpl<SDValue> &InVals) const {
803 SelectionDAG &DAG = CLI.DAG;
805 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
806 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
807 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
808 SDValue Chain = CLI.Chain;
809 SDValue Callee = CLI.Callee;
810 bool &IsTailCall = CLI.IsTailCall;
811 CallingConv::ID CallConv = CLI.CallConv;
812 bool IsVarArg = CLI.IsVarArg;
813 MachineFunction &MF = DAG.getMachineFunction();
814 EVT PtrVT = getPointerTy();
816 // Analyze the operands of the call, assigning locations to each operand.
817 SmallVector<CCValAssign, 16> ArgLocs;
818 CCState ArgCCInfo(CallConv, IsVarArg, MF, TM, ArgLocs, *DAG.getContext());
819 ArgCCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
821 // We don't support GuaranteedTailCallOpt, only automatically-detected
823 if (IsTailCall && !canUseSiblingCall(ArgCCInfo, ArgLocs))
826 // Get a count of how many bytes are to be pushed on the stack.
827 unsigned NumBytes = ArgCCInfo.getNextStackOffset();
829 // Mark the start of the call.
831 Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes, PtrVT, true),
834 // Copy argument values to their designated locations.
835 SmallVector<std::pair<unsigned, SDValue>, 9> RegsToPass;
836 SmallVector<SDValue, 8> MemOpChains;
838 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
839 CCValAssign &VA = ArgLocs[I];
840 SDValue ArgValue = OutVals[I];
842 if (VA.getLocInfo() == CCValAssign::Indirect) {
843 // Store the argument in a stack slot and pass its address.
844 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
845 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
846 MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, SpillSlot,
847 MachinePointerInfo::getFixedStack(FI),
849 ArgValue = SpillSlot;
851 ArgValue = convertValVTToLocVT(DAG, DL, VA, ArgValue);
854 // Queue up the argument copies and emit them at the end.
855 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));
857 assert(VA.isMemLoc() && "Argument not register or memory");
859 // Work out the address of the stack slot. Unpromoted ints and
860 // floats are passed as right-justified 8-byte values.
861 if (!StackPtr.getNode())
862 StackPtr = DAG.getCopyFromReg(Chain, DL, SystemZ::R15D, PtrVT);
863 unsigned Offset = SystemZMC::CallFrameSize + VA.getLocMemOffset();
864 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
866 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
867 DAG.getIntPtrConstant(Offset));
870 MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, Address,
871 MachinePointerInfo(),
876 // Join the stores, which are independent of one another.
877 if (!MemOpChains.empty())
878 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
879 &MemOpChains[0], MemOpChains.size());
881 // Accept direct calls by converting symbolic call addresses to the
882 // associated Target* opcodes. Force %r1 to be used for indirect
885 if (auto *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
886 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT);
887 Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
888 } else if (auto *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
889 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT);
890 Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
891 } else if (IsTailCall) {
892 Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R1D, Callee, Glue);
893 Glue = Chain.getValue(1);
894 Callee = DAG.getRegister(SystemZ::R1D, Callee.getValueType());
897 // Build a sequence of copy-to-reg nodes, chained and glued together.
898 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {
899 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
900 RegsToPass[I].second, Glue);
901 Glue = Chain.getValue(1);
904 // The first call operand is the chain and the second is the target address.
905 SmallVector<SDValue, 8> Ops;
906 Ops.push_back(Chain);
907 Ops.push_back(Callee);
909 // Add argument registers to the end of the list so that they are
910 // known live into the call.
911 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I)
912 Ops.push_back(DAG.getRegister(RegsToPass[I].first,
913 RegsToPass[I].second.getValueType()));
915 // Glue the call to the argument copies, if any.
920 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
922 return DAG.getNode(SystemZISD::SIBCALL, DL, NodeTys, &Ops[0], Ops.size());
923 Chain = DAG.getNode(SystemZISD::CALL, DL, NodeTys, &Ops[0], Ops.size());
924 Glue = Chain.getValue(1);
926 // Mark the end of the call, which is glued to the call itself.
927 Chain = DAG.getCALLSEQ_END(Chain,
928 DAG.getConstant(NumBytes, PtrVT, true),
929 DAG.getConstant(0, PtrVT, true),
931 Glue = Chain.getValue(1);
933 // Assign locations to each value returned by this call.
934 SmallVector<CCValAssign, 16> RetLocs;
935 CCState RetCCInfo(CallConv, IsVarArg, MF, TM, RetLocs, *DAG.getContext());
936 RetCCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ);
938 // Copy all of the result registers out of their specified physreg.
939 for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
940 CCValAssign &VA = RetLocs[I];
942 // Copy the value out, gluing the copy to the end of the call sequence.
943 SDValue RetValue = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(),
944 VA.getLocVT(), Glue);
945 Chain = RetValue.getValue(1);
946 Glue = RetValue.getValue(2);
948 // Convert the value of the return register into the value that's
950 InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, RetValue));
957 SystemZTargetLowering::LowerReturn(SDValue Chain,
958 CallingConv::ID CallConv, bool IsVarArg,
959 const SmallVectorImpl<ISD::OutputArg> &Outs,
960 const SmallVectorImpl<SDValue> &OutVals,
961 SDLoc DL, SelectionDAG &DAG) const {
962 MachineFunction &MF = DAG.getMachineFunction();
964 // Assign locations to each returned value.
965 SmallVector<CCValAssign, 16> RetLocs;
966 CCState RetCCInfo(CallConv, IsVarArg, MF, TM, RetLocs, *DAG.getContext());
967 RetCCInfo.AnalyzeReturn(Outs, RetCC_SystemZ);
969 // Quick exit for void returns
971 return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, Chain);
973 // Copy the result values into the output registers.
975 SmallVector<SDValue, 4> RetOps;
976 RetOps.push_back(Chain);
977 for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
978 CCValAssign &VA = RetLocs[I];
979 SDValue RetValue = OutVals[I];
981 // Make the return register live on exit.
982 assert(VA.isRegLoc() && "Can only return in registers!");
984 // Promote the value as required.
985 RetValue = convertValVTToLocVT(DAG, DL, VA, RetValue);
987 // Chain and glue the copies together.
988 unsigned Reg = VA.getLocReg();
989 Chain = DAG.getCopyToReg(Chain, DL, Reg, RetValue, Glue);
990 Glue = Chain.getValue(1);
991 RetOps.push_back(DAG.getRegister(Reg, VA.getLocVT()));
994 // Update chain and glue.
997 RetOps.push_back(Glue);
999 return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other,
1000 RetOps.data(), RetOps.size());
1003 SDValue SystemZTargetLowering::
1004 prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL, SelectionDAG &DAG) const {
1005 return DAG.getNode(SystemZISD::SERIALIZE, DL, MVT::Other, Chain);
1008 // CC is a comparison that will be implemented using an integer or
1009 // floating-point comparison. Return the condition code mask for
1010 // a branch on true. In the integer case, CCMASK_CMP_UO is set for
1011 // unsigned comparisons and clear for signed ones. In the floating-point
1012 // case, CCMASK_CMP_UO has its normal mask meaning (unordered).
1013 static unsigned CCMaskForCondCode(ISD::CondCode CC) {
1015 case ISD::SET##X: return SystemZ::CCMASK_CMP_##X; \
1016 case ISD::SETO##X: return SystemZ::CCMASK_CMP_##X; \
1017 case ISD::SETU##X: return SystemZ::CCMASK_CMP_UO | SystemZ::CCMASK_CMP_##X
1021 llvm_unreachable("Invalid integer condition!");
1030 case ISD::SETO: return SystemZ::CCMASK_CMP_O;
1031 case ISD::SETUO: return SystemZ::CCMASK_CMP_UO;
1036 // Return a sequence for getting a 1 from an IPM result when CC has a
1037 // value in CCMask and a 0 when CC has a value in CCValid & ~CCMask.
1038 // The handling of CC values outside CCValid doesn't matter.
1039 static IPMConversion getIPMConversion(unsigned CCValid, unsigned CCMask) {
1040 // Deal with cases where the result can be taken directly from a bit
1041 // of the IPM result.
1042 if (CCMask == (CCValid & (SystemZ::CCMASK_1 | SystemZ::CCMASK_3)))
1043 return IPMConversion(0, 0, SystemZ::IPM_CC);
1044 if (CCMask == (CCValid & (SystemZ::CCMASK_2 | SystemZ::CCMASK_3)))
1045 return IPMConversion(0, 0, SystemZ::IPM_CC + 1);
1047 // Deal with cases where we can add a value to force the sign bit
1048 // to contain the right value. Putting the bit in 31 means we can
1049 // use SRL rather than RISBG(L), and also makes it easier to get a
1050 // 0/-1 value, so it has priority over the other tests below.
1052 // These sequences rely on the fact that the upper two bits of the
1053 // IPM result are zero.
1054 uint64_t TopBit = uint64_t(1) << 31;
1055 if (CCMask == (CCValid & SystemZ::CCMASK_0))
1056 return IPMConversion(0, -(1 << SystemZ::IPM_CC), 31);
1057 if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_1)))
1058 return IPMConversion(0, -(2 << SystemZ::IPM_CC), 31);
1059 if (CCMask == (CCValid & (SystemZ::CCMASK_0
1061 | SystemZ::CCMASK_2)))
1062 return IPMConversion(0, -(3 << SystemZ::IPM_CC), 31);
1063 if (CCMask == (CCValid & SystemZ::CCMASK_3))
1064 return IPMConversion(0, TopBit - (3 << SystemZ::IPM_CC), 31);
1065 if (CCMask == (CCValid & (SystemZ::CCMASK_1
1067 | SystemZ::CCMASK_3)))
1068 return IPMConversion(0, TopBit - (1 << SystemZ::IPM_CC), 31);
1070 // Next try inverting the value and testing a bit. 0/1 could be
1071 // handled this way too, but we dealt with that case above.
1072 if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_2)))
1073 return IPMConversion(-1, 0, SystemZ::IPM_CC);
1075 // Handle cases where adding a value forces a non-sign bit to contain
1077 if (CCMask == (CCValid & (SystemZ::CCMASK_1 | SystemZ::CCMASK_2)))
1078 return IPMConversion(0, 1 << SystemZ::IPM_CC, SystemZ::IPM_CC + 1);
1079 if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_3)))
1080 return IPMConversion(0, -(1 << SystemZ::IPM_CC), SystemZ::IPM_CC + 1);
1082 // The remaining cases are 1, 2, 0/1/3 and 0/2/3. All these are
1083 // can be done by inverting the low CC bit and applying one of the
1084 // sign-based extractions above.
1085 if (CCMask == (CCValid & SystemZ::CCMASK_1))
1086 return IPMConversion(1 << SystemZ::IPM_CC, -(1 << SystemZ::IPM_CC), 31);
1087 if (CCMask == (CCValid & SystemZ::CCMASK_2))
1088 return IPMConversion(1 << SystemZ::IPM_CC,
1089 TopBit - (3 << SystemZ::IPM_CC), 31);
1090 if (CCMask == (CCValid & (SystemZ::CCMASK_0
1092 | SystemZ::CCMASK_3)))
1093 return IPMConversion(1 << SystemZ::IPM_CC, -(3 << SystemZ::IPM_CC), 31);
1094 if (CCMask == (CCValid & (SystemZ::CCMASK_0
1096 | SystemZ::CCMASK_3)))
1097 return IPMConversion(1 << SystemZ::IPM_CC,
1098 TopBit - (1 << SystemZ::IPM_CC), 31);
1100 llvm_unreachable("Unexpected CC combination");
1103 // If C can be converted to a comparison against zero, adjust the operands
1105 static void adjustZeroCmp(SelectionDAG &DAG, Comparison &C) {
1106 if (C.ICmpType == SystemZICMP::UnsignedOnly)
1109 auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1.getNode());
1113 int64_t Value = ConstOp1->getSExtValue();
1114 if ((Value == -1 && C.CCMask == SystemZ::CCMASK_CMP_GT) ||
1115 (Value == -1 && C.CCMask == SystemZ::CCMASK_CMP_LE) ||
1116 (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_LT) ||
1117 (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_GE)) {
1118 C.CCMask ^= SystemZ::CCMASK_CMP_EQ;
1119 C.Op1 = DAG.getConstant(0, C.Op1.getValueType());
1123 // If a comparison described by C is suitable for CLI(Y), CHHSI or CLHHSI,
1124 // adjust the operands as necessary.
1125 static void adjustSubwordCmp(SelectionDAG &DAG, Comparison &C) {
1126 // For us to make any changes, it must a comparison between a single-use
1127 // load and a constant.
1128 if (!C.Op0.hasOneUse() ||
1129 C.Op0.getOpcode() != ISD::LOAD ||
1130 C.Op1.getOpcode() != ISD::Constant)
1133 // We must have an 8- or 16-bit load.
1134 auto *Load = cast<LoadSDNode>(C.Op0);
1135 unsigned NumBits = Load->getMemoryVT().getStoreSizeInBits();
1136 if (NumBits != 8 && NumBits != 16)
1139 // The load must be an extending one and the constant must be within the
1140 // range of the unextended value.
1141 auto *ConstOp1 = cast<ConstantSDNode>(C.Op1);
1142 uint64_t Value = ConstOp1->getZExtValue();
1143 uint64_t Mask = (1 << NumBits) - 1;
1144 if (Load->getExtensionType() == ISD::SEXTLOAD) {
1145 // Make sure that ConstOp1 is in range of C.Op0.
1146 int64_t SignedValue = ConstOp1->getSExtValue();
1147 if (uint64_t(SignedValue) + (uint64_t(1) << (NumBits - 1)) > Mask)
1149 if (C.ICmpType != SystemZICMP::SignedOnly) {
1150 // Unsigned comparison between two sign-extended values is equivalent
1151 // to unsigned comparison between two zero-extended values.
1153 } else if (NumBits == 8) {
1154 // Try to treat the comparison as unsigned, so that we can use CLI.
1155 // Adjust CCMask and Value as necessary.
1156 if (Value == 0 && C.CCMask == SystemZ::CCMASK_CMP_LT)
1157 // Test whether the high bit of the byte is set.
1158 Value = 127, C.CCMask = SystemZ::CCMASK_CMP_GT;
1159 else if (Value == 0 && C.CCMask == SystemZ::CCMASK_CMP_GE)
1160 // Test whether the high bit of the byte is clear.
1161 Value = 128, C.CCMask = SystemZ::CCMASK_CMP_LT;
1163 // No instruction exists for this combination.
1165 C.ICmpType = SystemZICMP::UnsignedOnly;
1167 } else if (Load->getExtensionType() == ISD::ZEXTLOAD) {
1170 assert(C.ICmpType == SystemZICMP::Any &&
1171 "Signedness shouldn't matter here.");
1175 // Make sure that the first operand is an i32 of the right extension type.
1176 ISD::LoadExtType ExtType = (C.ICmpType == SystemZICMP::SignedOnly ?
1179 if (C.Op0.getValueType() != MVT::i32 ||
1180 Load->getExtensionType() != ExtType)
1181 C.Op0 = DAG.getExtLoad(ExtType, SDLoc(Load), MVT::i32,
1182 Load->getChain(), Load->getBasePtr(),
1183 Load->getPointerInfo(), Load->getMemoryVT(),
1184 Load->isVolatile(), Load->isNonTemporal(),
1185 Load->getAlignment());
1187 // Make sure that the second operand is an i32 with the right value.
1188 if (C.Op1.getValueType() != MVT::i32 ||
1189 Value != ConstOp1->getZExtValue())
1190 C.Op1 = DAG.getConstant(Value, MVT::i32);
1193 // Return true if Op is either an unextended load, or a load suitable
1194 // for integer register-memory comparisons of type ICmpType.
1195 static bool isNaturalMemoryOperand(SDValue Op, unsigned ICmpType) {
1196 auto *Load = dyn_cast<LoadSDNode>(Op.getNode());
1198 // There are no instructions to compare a register with a memory byte.
1199 if (Load->getMemoryVT() == MVT::i8)
1201 // Otherwise decide on extension type.
1202 switch (Load->getExtensionType()) {
1203 case ISD::NON_EXTLOAD:
1206 return ICmpType != SystemZICMP::UnsignedOnly;
1208 return ICmpType != SystemZICMP::SignedOnly;
1216 // Return true if it is better to swap the operands of C.
1217 static bool shouldSwapCmpOperands(const Comparison &C) {
1218 // Leave f128 comparisons alone, since they have no memory forms.
1219 if (C.Op0.getValueType() == MVT::f128)
1222 // Always keep a floating-point constant second, since comparisons with
1223 // zero can use LOAD TEST and comparisons with other constants make a
1224 // natural memory operand.
1225 if (isa<ConstantFPSDNode>(C.Op1))
1228 // Never swap comparisons with zero since there are many ways to optimize
1230 auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1);
1231 if (ConstOp1 && ConstOp1->getZExtValue() == 0)
1234 // Also keep natural memory operands second if the loaded value is
1235 // only used here. Several comparisons have memory forms.
1236 if (isNaturalMemoryOperand(C.Op1, C.ICmpType) && C.Op1.hasOneUse())
1239 // Look for cases where Cmp0 is a single-use load and Cmp1 isn't.
1240 // In that case we generally prefer the memory to be second.
1241 if (isNaturalMemoryOperand(C.Op0, C.ICmpType) && C.Op0.hasOneUse()) {
1242 // The only exceptions are when the second operand is a constant and
1243 // we can use things like CHHSI.
1246 // The unsigned memory-immediate instructions can handle 16-bit
1247 // unsigned integers.
1248 if (C.ICmpType != SystemZICMP::SignedOnly &&
1249 isUInt<16>(ConstOp1->getZExtValue()))
1251 // The signed memory-immediate instructions can handle 16-bit
1253 if (C.ICmpType != SystemZICMP::UnsignedOnly &&
1254 isInt<16>(ConstOp1->getSExtValue()))
1259 // Try to promote the use of CGFR and CLGFR.
1260 unsigned Opcode0 = C.Op0.getOpcode();
1261 if (C.ICmpType != SystemZICMP::UnsignedOnly && Opcode0 == ISD::SIGN_EXTEND)
1263 if (C.ICmpType != SystemZICMP::SignedOnly && Opcode0 == ISD::ZERO_EXTEND)
1265 if (C.ICmpType != SystemZICMP::SignedOnly &&
1266 Opcode0 == ISD::AND &&
1267 C.Op0.getOperand(1).getOpcode() == ISD::Constant &&
1268 cast<ConstantSDNode>(C.Op0.getOperand(1))->getZExtValue() == 0xffffffff)
1274 // Return a version of comparison CC mask CCMask in which the LT and GT
1275 // actions are swapped.
1276 static unsigned reverseCCMask(unsigned CCMask) {
1277 return ((CCMask & SystemZ::CCMASK_CMP_EQ) |
1278 (CCMask & SystemZ::CCMASK_CMP_GT ? SystemZ::CCMASK_CMP_LT : 0) |
1279 (CCMask & SystemZ::CCMASK_CMP_LT ? SystemZ::CCMASK_CMP_GT : 0) |
1280 (CCMask & SystemZ::CCMASK_CMP_UO));
1283 // Check whether C tests for equality between X and Y and whether X - Y
1284 // or Y - X is also computed. In that case it's better to compare the
1285 // result of the subtraction against zero.
1286 static void adjustForSubtraction(SelectionDAG &DAG, Comparison &C) {
1287 if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
1288 C.CCMask == SystemZ::CCMASK_CMP_NE) {
1289 for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
1291 if (N->getOpcode() == ISD::SUB &&
1292 ((N->getOperand(0) == C.Op0 && N->getOperand(1) == C.Op1) ||
1293 (N->getOperand(0) == C.Op1 && N->getOperand(1) == C.Op0))) {
1294 C.Op0 = SDValue(N, 0);
1295 C.Op1 = DAG.getConstant(0, N->getValueType(0));
1302 // Check whether C compares a floating-point value with zero and if that
1303 // floating-point value is also negated. In this case we can use the
1304 // negation to set CC, so avoiding separate LOAD AND TEST and
1305 // LOAD (NEGATIVE/COMPLEMENT) instructions.
1306 static void adjustForFNeg(Comparison &C) {
1307 auto *C1 = dyn_cast<ConstantFPSDNode>(C.Op1);
1308 if (C1 && C1->isZero()) {
1309 for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
1311 if (N->getOpcode() == ISD::FNEG) {
1312 C.Op0 = SDValue(N, 0);
1313 C.CCMask = reverseCCMask(C.CCMask);
1320 // Check whether C compares (shl X, 32) with 0 and whether X is
1321 // also sign-extended. In that case it is better to test the result
1322 // of the sign extension using LTGFR.
1324 // This case is important because InstCombine transforms a comparison
1325 // with (sext (trunc X)) into a comparison with (shl X, 32).
1326 static void adjustForLTGFR(Comparison &C) {
1327 // Check for a comparison between (shl X, 32) and 0.
1328 if (C.Op0.getOpcode() == ISD::SHL &&
1329 C.Op0.getValueType() == MVT::i64 &&
1330 C.Op1.getOpcode() == ISD::Constant &&
1331 cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
1332 auto *C1 = dyn_cast<ConstantSDNode>(C.Op0.getOperand(1));
1333 if (C1 && C1->getZExtValue() == 32) {
1334 SDValue ShlOp0 = C.Op0.getOperand(0);
1335 // See whether X has any SIGN_EXTEND_INREG uses.
1336 for (auto I = ShlOp0->use_begin(), E = ShlOp0->use_end(); I != E; ++I) {
1338 if (N->getOpcode() == ISD::SIGN_EXTEND_INREG &&
1339 cast<VTSDNode>(N->getOperand(1))->getVT() == MVT::i32) {
1340 C.Op0 = SDValue(N, 0);
1348 // If C compares the truncation of an extending load, try to compare
1349 // the untruncated value instead. This exposes more opportunities to
1351 static void adjustICmpTruncate(SelectionDAG &DAG, Comparison &C) {
1352 if (C.Op0.getOpcode() == ISD::TRUNCATE &&
1353 C.Op0.getOperand(0).getOpcode() == ISD::LOAD &&
1354 C.Op1.getOpcode() == ISD::Constant &&
1355 cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
1356 auto *L = cast<LoadSDNode>(C.Op0.getOperand(0));
1357 if (L->getMemoryVT().getStoreSizeInBits()
1358 <= C.Op0.getValueType().getSizeInBits()) {
1359 unsigned Type = L->getExtensionType();
1360 if ((Type == ISD::ZEXTLOAD && C.ICmpType != SystemZICMP::SignedOnly) ||
1361 (Type == ISD::SEXTLOAD && C.ICmpType != SystemZICMP::UnsignedOnly)) {
1362 C.Op0 = C.Op0.getOperand(0);
1363 C.Op1 = DAG.getConstant(0, C.Op0.getValueType());
1369 // Return true if shift operation N has an in-range constant shift value.
1370 // Store it in ShiftVal if so.
1371 static bool isSimpleShift(SDValue N, unsigned &ShiftVal) {
1372 auto *Shift = dyn_cast<ConstantSDNode>(N.getOperand(1));
1376 uint64_t Amount = Shift->getZExtValue();
1377 if (Amount >= N.getValueType().getSizeInBits())
1384 // Check whether an AND with Mask is suitable for a TEST UNDER MASK
1385 // instruction and whether the CC value is descriptive enough to handle
1386 // a comparison of type Opcode between the AND result and CmpVal.
1387 // CCMask says which comparison result is being tested and BitSize is
1388 // the number of bits in the operands. If TEST UNDER MASK can be used,
1389 // return the corresponding CC mask, otherwise return 0.
1390 static unsigned getTestUnderMaskCond(unsigned BitSize, unsigned CCMask,
1391 uint64_t Mask, uint64_t CmpVal,
1392 unsigned ICmpType) {
1393 assert(Mask != 0 && "ANDs with zero should have been removed by now");
1395 // Check whether the mask is suitable for TMHH, TMHL, TMLH or TMLL.
1396 if (!SystemZ::isImmLL(Mask) && !SystemZ::isImmLH(Mask) &&
1397 !SystemZ::isImmHL(Mask) && !SystemZ::isImmHH(Mask))
1400 // Work out the masks for the lowest and highest bits.
1401 unsigned HighShift = 63 - countLeadingZeros(Mask);
1402 uint64_t High = uint64_t(1) << HighShift;
1403 uint64_t Low = uint64_t(1) << countTrailingZeros(Mask);
1405 // Signed ordered comparisons are effectively unsigned if the sign
1407 bool EffectivelyUnsigned = (ICmpType != SystemZICMP::SignedOnly);
1409 // Check for equality comparisons with 0, or the equivalent.
1411 if (CCMask == SystemZ::CCMASK_CMP_EQ)
1412 return SystemZ::CCMASK_TM_ALL_0;
1413 if (CCMask == SystemZ::CCMASK_CMP_NE)
1414 return SystemZ::CCMASK_TM_SOME_1;
1416 if (EffectivelyUnsigned && CmpVal <= Low) {
1417 if (CCMask == SystemZ::CCMASK_CMP_LT)
1418 return SystemZ::CCMASK_TM_ALL_0;
1419 if (CCMask == SystemZ::CCMASK_CMP_GE)
1420 return SystemZ::CCMASK_TM_SOME_1;
1422 if (EffectivelyUnsigned && CmpVal < Low) {
1423 if (CCMask == SystemZ::CCMASK_CMP_LE)
1424 return SystemZ::CCMASK_TM_ALL_0;
1425 if (CCMask == SystemZ::CCMASK_CMP_GT)
1426 return SystemZ::CCMASK_TM_SOME_1;
1429 // Check for equality comparisons with the mask, or the equivalent.
1430 if (CmpVal == Mask) {
1431 if (CCMask == SystemZ::CCMASK_CMP_EQ)
1432 return SystemZ::CCMASK_TM_ALL_1;
1433 if (CCMask == SystemZ::CCMASK_CMP_NE)
1434 return SystemZ::CCMASK_TM_SOME_0;
1436 if (EffectivelyUnsigned && CmpVal >= Mask - Low && CmpVal < Mask) {
1437 if (CCMask == SystemZ::CCMASK_CMP_GT)
1438 return SystemZ::CCMASK_TM_ALL_1;
1439 if (CCMask == SystemZ::CCMASK_CMP_LE)
1440 return SystemZ::CCMASK_TM_SOME_0;
1442 if (EffectivelyUnsigned && CmpVal > Mask - Low && CmpVal <= Mask) {
1443 if (CCMask == SystemZ::CCMASK_CMP_GE)
1444 return SystemZ::CCMASK_TM_ALL_1;
1445 if (CCMask == SystemZ::CCMASK_CMP_LT)
1446 return SystemZ::CCMASK_TM_SOME_0;
1449 // Check for ordered comparisons with the top bit.
1450 if (EffectivelyUnsigned && CmpVal >= Mask - High && CmpVal < High) {
1451 if (CCMask == SystemZ::CCMASK_CMP_LE)
1452 return SystemZ::CCMASK_TM_MSB_0;
1453 if (CCMask == SystemZ::CCMASK_CMP_GT)
1454 return SystemZ::CCMASK_TM_MSB_1;
1456 if (EffectivelyUnsigned && CmpVal > Mask - High && CmpVal <= High) {
1457 if (CCMask == SystemZ::CCMASK_CMP_LT)
1458 return SystemZ::CCMASK_TM_MSB_0;
1459 if (CCMask == SystemZ::CCMASK_CMP_GE)
1460 return SystemZ::CCMASK_TM_MSB_1;
1463 // If there are just two bits, we can do equality checks for Low and High
1465 if (Mask == Low + High) {
1466 if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == Low)
1467 return SystemZ::CCMASK_TM_MIXED_MSB_0;
1468 if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == Low)
1469 return SystemZ::CCMASK_TM_MIXED_MSB_0 ^ SystemZ::CCMASK_ANY;
1470 if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == High)
1471 return SystemZ::CCMASK_TM_MIXED_MSB_1;
1472 if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == High)
1473 return SystemZ::CCMASK_TM_MIXED_MSB_1 ^ SystemZ::CCMASK_ANY;
1476 // Looks like we've exhausted our options.
1480 // See whether C can be implemented as a TEST UNDER MASK instruction.
1481 // Update the arguments with the TM version if so.
1482 static void adjustForTestUnderMask(SelectionDAG &DAG, Comparison &C) {
1483 // Check that we have a comparison with a constant.
1484 auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1);
1487 uint64_t CmpVal = ConstOp1->getZExtValue();
1489 // Check whether the nonconstant input is an AND with a constant mask.
1492 ConstantSDNode *Mask = 0;
1493 if (C.Op0.getOpcode() == ISD::AND) {
1494 NewC.Op0 = C.Op0.getOperand(0);
1495 NewC.Op1 = C.Op0.getOperand(1);
1496 Mask = dyn_cast<ConstantSDNode>(NewC.Op1);
1499 MaskVal = Mask->getZExtValue();
1501 // There is no instruction to compare with a 64-bit immediate
1502 // so use TMHH instead if possible. We need an unsigned ordered
1503 // comparison with an i64 immediate.
1504 if (NewC.Op0.getValueType() != MVT::i64 ||
1505 NewC.CCMask == SystemZ::CCMASK_CMP_EQ ||
1506 NewC.CCMask == SystemZ::CCMASK_CMP_NE ||
1507 NewC.ICmpType == SystemZICMP::SignedOnly)
1509 // Convert LE and GT comparisons into LT and GE.
1510 if (NewC.CCMask == SystemZ::CCMASK_CMP_LE ||
1511 NewC.CCMask == SystemZ::CCMASK_CMP_GT) {
1512 if (CmpVal == uint64_t(-1))
1515 NewC.CCMask ^= SystemZ::CCMASK_CMP_EQ;
1517 // If the low N bits of Op1 are zero than the low N bits of Op0 can
1518 // be masked off without changing the result.
1519 MaskVal = -(CmpVal & -CmpVal);
1520 NewC.ICmpType = SystemZICMP::UnsignedOnly;
1523 // Check whether the combination of mask, comparison value and comparison
1524 // type are suitable.
1525 unsigned BitSize = NewC.Op0.getValueType().getSizeInBits();
1526 unsigned NewCCMask, ShiftVal;
1527 if (NewC.ICmpType != SystemZICMP::SignedOnly &&
1528 NewC.Op0.getOpcode() == ISD::SHL &&
1529 isSimpleShift(NewC.Op0, ShiftVal) &&
1530 (NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask,
1531 MaskVal >> ShiftVal,
1533 SystemZICMP::Any))) {
1534 NewC.Op0 = NewC.Op0.getOperand(0);
1535 MaskVal >>= ShiftVal;
1536 } else if (NewC.ICmpType != SystemZICMP::SignedOnly &&
1537 NewC.Op0.getOpcode() == ISD::SRL &&
1538 isSimpleShift(NewC.Op0, ShiftVal) &&
1539 (NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask,
1540 MaskVal << ShiftVal,
1542 SystemZICMP::UnsignedOnly))) {
1543 NewC.Op0 = NewC.Op0.getOperand(0);
1544 MaskVal <<= ShiftVal;
1546 NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask, MaskVal, CmpVal,
1552 // Go ahead and make the change.
1553 C.Opcode = SystemZISD::TM;
1555 if (Mask && Mask->getZExtValue() == MaskVal)
1556 C.Op1 = SDValue(Mask, 0);
1558 C.Op1 = DAG.getConstant(MaskVal, C.Op0.getValueType());
1559 C.CCValid = SystemZ::CCMASK_TM;
1560 C.CCMask = NewCCMask;
1563 // Decide how to implement a comparison of type Cond between CmpOp0 with CmpOp1.
1564 static Comparison getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1,
1565 ISD::CondCode Cond) {
1566 Comparison C(CmpOp0, CmpOp1);
1567 C.CCMask = CCMaskForCondCode(Cond);
1568 if (C.Op0.getValueType().isFloatingPoint()) {
1569 C.CCValid = SystemZ::CCMASK_FCMP;
1570 C.Opcode = SystemZISD::FCMP;
1573 C.CCValid = SystemZ::CCMASK_ICMP;
1574 C.Opcode = SystemZISD::ICMP;
1575 // Choose the type of comparison. Equality and inequality tests can
1576 // use either signed or unsigned comparisons. The choice also doesn't
1577 // matter if both sign bits are known to be clear. In those cases we
1578 // want to give the main isel code the freedom to choose whichever
1580 if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
1581 C.CCMask == SystemZ::CCMASK_CMP_NE ||
1582 (DAG.SignBitIsZero(C.Op0) && DAG.SignBitIsZero(C.Op1)))
1583 C.ICmpType = SystemZICMP::Any;
1584 else if (C.CCMask & SystemZ::CCMASK_CMP_UO)
1585 C.ICmpType = SystemZICMP::UnsignedOnly;
1587 C.ICmpType = SystemZICMP::SignedOnly;
1588 C.CCMask &= ~SystemZ::CCMASK_CMP_UO;
1589 adjustZeroCmp(DAG, C);
1590 adjustSubwordCmp(DAG, C);
1591 adjustForSubtraction(DAG, C);
1593 adjustICmpTruncate(DAG, C);
1596 if (shouldSwapCmpOperands(C)) {
1597 std::swap(C.Op0, C.Op1);
1598 C.CCMask = reverseCCMask(C.CCMask);
1601 adjustForTestUnderMask(DAG, C);
1605 // Emit the comparison instruction described by C.
1606 static SDValue emitCmp(SelectionDAG &DAG, SDLoc DL, Comparison &C) {
1607 if (C.Opcode == SystemZISD::ICMP)
1608 return DAG.getNode(SystemZISD::ICMP, DL, MVT::Glue, C.Op0, C.Op1,
1609 DAG.getConstant(C.ICmpType, MVT::i32));
1610 if (C.Opcode == SystemZISD::TM) {
1611 bool RegisterOnly = (bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_0) !=
1612 bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_1));
1613 return DAG.getNode(SystemZISD::TM, DL, MVT::Glue, C.Op0, C.Op1,
1614 DAG.getConstant(RegisterOnly, MVT::i32));
1616 return DAG.getNode(C.Opcode, DL, MVT::Glue, C.Op0, C.Op1);
1619 // Implement a 32-bit *MUL_LOHI operation by extending both operands to
1620 // 64 bits. Extend is the extension type to use. Store the high part
1621 // in Hi and the low part in Lo.
1622 static void lowerMUL_LOHI32(SelectionDAG &DAG, SDLoc DL,
1623 unsigned Extend, SDValue Op0, SDValue Op1,
1624 SDValue &Hi, SDValue &Lo) {
1625 Op0 = DAG.getNode(Extend, DL, MVT::i64, Op0);
1626 Op1 = DAG.getNode(Extend, DL, MVT::i64, Op1);
1627 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, Op0, Op1);
1628 Hi = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul, DAG.getConstant(32, MVT::i64));
1629 Hi = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Hi);
1630 Lo = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mul);
1633 // Lower a binary operation that produces two VT results, one in each
1634 // half of a GR128 pair. Op0 and Op1 are the VT operands to the operation,
1635 // Extend extends Op0 to a GR128, and Opcode performs the GR128 operation
1636 // on the extended Op0 and (unextended) Op1. Store the even register result
1637 // in Even and the odd register result in Odd.
1638 static void lowerGR128Binary(SelectionDAG &DAG, SDLoc DL, EVT VT,
1639 unsigned Extend, unsigned Opcode,
1640 SDValue Op0, SDValue Op1,
1641 SDValue &Even, SDValue &Odd) {
1642 SDNode *In128 = DAG.getMachineNode(Extend, DL, MVT::Untyped, Op0);
1643 SDValue Result = DAG.getNode(Opcode, DL, MVT::Untyped,
1644 SDValue(In128, 0), Op1);
1645 bool Is32Bit = is32Bit(VT);
1646 Even = DAG.getTargetExtractSubreg(SystemZ::even128(Is32Bit), DL, VT, Result);
1647 Odd = DAG.getTargetExtractSubreg(SystemZ::odd128(Is32Bit), DL, VT, Result);
1650 // Return an i32 value that is 1 if the CC value produced by Glue is
1651 // in the mask CCMask and 0 otherwise. CC is known to have a value
1652 // in CCValid, so other values can be ignored.
1653 static SDValue emitSETCC(SelectionDAG &DAG, SDLoc DL, SDValue Glue,
1654 unsigned CCValid, unsigned CCMask) {
1655 IPMConversion Conversion = getIPMConversion(CCValid, CCMask);
1656 SDValue Result = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, Glue);
1658 if (Conversion.XORValue)
1659 Result = DAG.getNode(ISD::XOR, DL, MVT::i32, Result,
1660 DAG.getConstant(Conversion.XORValue, MVT::i32));
1662 if (Conversion.AddValue)
1663 Result = DAG.getNode(ISD::ADD, DL, MVT::i32, Result,
1664 DAG.getConstant(Conversion.AddValue, MVT::i32));
1666 // The SHR/AND sequence should get optimized to an RISBG.
1667 Result = DAG.getNode(ISD::SRL, DL, MVT::i32, Result,
1668 DAG.getConstant(Conversion.Bit, MVT::i32));
1669 if (Conversion.Bit != 31)
1670 Result = DAG.getNode(ISD::AND, DL, MVT::i32, Result,
1671 DAG.getConstant(1, MVT::i32));
1675 SDValue SystemZTargetLowering::lowerSETCC(SDValue Op,
1676 SelectionDAG &DAG) const {
1677 SDValue CmpOp0 = Op.getOperand(0);
1678 SDValue CmpOp1 = Op.getOperand(1);
1679 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1682 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC));
1683 SDValue Glue = emitCmp(DAG, DL, C);
1684 return emitSETCC(DAG, DL, Glue, C.CCValid, C.CCMask);
1687 SDValue SystemZTargetLowering::lowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
1688 SDValue Chain = Op.getOperand(0);
1689 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1690 SDValue CmpOp0 = Op.getOperand(2);
1691 SDValue CmpOp1 = Op.getOperand(3);
1692 SDValue Dest = Op.getOperand(4);
1695 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC));
1696 SDValue Glue = emitCmp(DAG, DL, C);
1697 return DAG.getNode(SystemZISD::BR_CCMASK, DL, Op.getValueType(),
1698 Chain, DAG.getConstant(C.CCValid, MVT::i32),
1699 DAG.getConstant(C.CCMask, MVT::i32), Dest, Glue);
1702 // Return true if Pos is CmpOp and Neg is the negative of CmpOp,
1703 // allowing Pos and Neg to be wider than CmpOp.
1704 static bool isAbsolute(SDValue CmpOp, SDValue Pos, SDValue Neg) {
1705 return (Neg.getOpcode() == ISD::SUB &&
1706 Neg.getOperand(0).getOpcode() == ISD::Constant &&
1707 cast<ConstantSDNode>(Neg.getOperand(0))->getZExtValue() == 0 &&
1708 Neg.getOperand(1) == Pos &&
1710 (Pos.getOpcode() == ISD::SIGN_EXTEND &&
1711 Pos.getOperand(0) == CmpOp)));
1714 // Return the absolute or negative absolute of Op; IsNegative decides which.
1715 static SDValue getAbsolute(SelectionDAG &DAG, SDLoc DL, SDValue Op,
1717 Op = DAG.getNode(SystemZISD::IABS, DL, Op.getValueType(), Op);
1719 Op = DAG.getNode(ISD::SUB, DL, Op.getValueType(),
1720 DAG.getConstant(0, Op.getValueType()), Op);
1724 SDValue SystemZTargetLowering::lowerSELECT_CC(SDValue Op,
1725 SelectionDAG &DAG) const {
1726 SDValue CmpOp0 = Op.getOperand(0);
1727 SDValue CmpOp1 = Op.getOperand(1);
1728 SDValue TrueOp = Op.getOperand(2);
1729 SDValue FalseOp = Op.getOperand(3);
1730 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1733 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC));
1735 // Check for absolute and negative-absolute selections, including those
1736 // where the comparison value is sign-extended (for LPGFR and LNGFR).
1737 // This check supplements the one in DAGCombiner.
1738 if (C.Opcode == SystemZISD::ICMP &&
1739 C.CCMask != SystemZ::CCMASK_CMP_EQ &&
1740 C.CCMask != SystemZ::CCMASK_CMP_NE &&
1741 C.Op1.getOpcode() == ISD::Constant &&
1742 cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
1743 if (isAbsolute(C.Op0, TrueOp, FalseOp))
1744 return getAbsolute(DAG, DL, TrueOp, C.CCMask & SystemZ::CCMASK_CMP_LT);
1745 if (isAbsolute(C.Op0, FalseOp, TrueOp))
1746 return getAbsolute(DAG, DL, FalseOp, C.CCMask & SystemZ::CCMASK_CMP_GT);
1749 SDValue Glue = emitCmp(DAG, DL, C);
1751 // Special case for handling -1/0 results. The shifts we use here
1752 // should get optimized with the IPM conversion sequence.
1753 auto *TrueC = dyn_cast<ConstantSDNode>(TrueOp);
1754 auto *FalseC = dyn_cast<ConstantSDNode>(FalseOp);
1755 if (TrueC && FalseC) {
1756 int64_t TrueVal = TrueC->getSExtValue();
1757 int64_t FalseVal = FalseC->getSExtValue();
1758 if ((TrueVal == -1 && FalseVal == 0) || (TrueVal == 0 && FalseVal == -1)) {
1759 // Invert the condition if we want -1 on false.
1761 C.CCMask ^= C.CCValid;
1762 SDValue Result = emitSETCC(DAG, DL, Glue, C.CCValid, C.CCMask);
1763 EVT VT = Op.getValueType();
1764 // Extend the result to VT. Upper bits are ignored.
1766 Result = DAG.getNode(ISD::ANY_EXTEND, DL, VT, Result);
1767 // Sign-extend from the low bit.
1768 SDValue ShAmt = DAG.getConstant(VT.getSizeInBits() - 1, MVT::i32);
1769 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, Result, ShAmt);
1770 return DAG.getNode(ISD::SRA, DL, VT, Shl, ShAmt);
1774 SmallVector<SDValue, 5> Ops;
1775 Ops.push_back(TrueOp);
1776 Ops.push_back(FalseOp);
1777 Ops.push_back(DAG.getConstant(C.CCValid, MVT::i32));
1778 Ops.push_back(DAG.getConstant(C.CCMask, MVT::i32));
1779 Ops.push_back(Glue);
1781 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1782 return DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VTs, &Ops[0], Ops.size());
1785 SDValue SystemZTargetLowering::lowerGlobalAddress(GlobalAddressSDNode *Node,
1786 SelectionDAG &DAG) const {
1788 const GlobalValue *GV = Node->getGlobal();
1789 int64_t Offset = Node->getOffset();
1790 EVT PtrVT = getPointerTy();
1791 Reloc::Model RM = TM.getRelocationModel();
1792 CodeModel::Model CM = TM.getCodeModel();
1795 if (Subtarget.isPC32DBLSymbol(GV, RM, CM)) {
1796 // Assign anchors at 1<<12 byte boundaries.
1797 uint64_t Anchor = Offset & ~uint64_t(0xfff);
1798 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor);
1799 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1801 // The offset can be folded into the address if it is aligned to a halfword.
1803 if (Offset != 0 && (Offset & 1) == 0) {
1804 SDValue Full = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor + Offset);
1805 Result = DAG.getNode(SystemZISD::PCREL_OFFSET, DL, PtrVT, Full, Result);
1809 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, SystemZII::MO_GOT);
1810 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1811 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
1812 MachinePointerInfo::getGOT(), false, false, false, 0);
1815 // If there was a non-zero offset that we didn't fold, create an explicit
1818 Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result,
1819 DAG.getConstant(Offset, PtrVT));
1824 SDValue SystemZTargetLowering::lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
1825 SelectionDAG &DAG) const {
1827 const GlobalValue *GV = Node->getGlobal();
1828 EVT PtrVT = getPointerTy();
1829 TLSModel::Model model = TM.getTLSModel(GV);
1831 if (model != TLSModel::LocalExec)
1832 llvm_unreachable("only local-exec TLS mode supported");
1834 // The high part of the thread pointer is in access register 0.
1835 SDValue TPHi = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
1836 DAG.getConstant(0, MVT::i32));
1837 TPHi = DAG.getNode(ISD::ANY_EXTEND, DL, PtrVT, TPHi);
1839 // The low part of the thread pointer is in access register 1.
1840 SDValue TPLo = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
1841 DAG.getConstant(1, MVT::i32));
1842 TPLo = DAG.getNode(ISD::ZERO_EXTEND, DL, PtrVT, TPLo);
1844 // Merge them into a single 64-bit address.
1845 SDValue TPHiShifted = DAG.getNode(ISD::SHL, DL, PtrVT, TPHi,
1846 DAG.getConstant(32, PtrVT));
1847 SDValue TP = DAG.getNode(ISD::OR, DL, PtrVT, TPHiShifted, TPLo);
1849 // Get the offset of GA from the thread pointer.
1850 SystemZConstantPoolValue *CPV =
1851 SystemZConstantPoolValue::Create(GV, SystemZCP::NTPOFF);
1853 // Force the offset into the constant pool and load it from there.
1854 SDValue CPAddr = DAG.getConstantPool(CPV, PtrVT, 8);
1855 SDValue Offset = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(),
1856 CPAddr, MachinePointerInfo::getConstantPool(),
1857 false, false, false, 0);
1859 // Add the base and offset together.
1860 return DAG.getNode(ISD::ADD, DL, PtrVT, TP, Offset);
1863 SDValue SystemZTargetLowering::lowerBlockAddress(BlockAddressSDNode *Node,
1864 SelectionDAG &DAG) const {
1866 const BlockAddress *BA = Node->getBlockAddress();
1867 int64_t Offset = Node->getOffset();
1868 EVT PtrVT = getPointerTy();
1870 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset);
1871 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1875 SDValue SystemZTargetLowering::lowerJumpTable(JumpTableSDNode *JT,
1876 SelectionDAG &DAG) const {
1878 EVT PtrVT = getPointerTy();
1879 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1881 // Use LARL to load the address of the table.
1882 return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1885 SDValue SystemZTargetLowering::lowerConstantPool(ConstantPoolSDNode *CP,
1886 SelectionDAG &DAG) const {
1888 EVT PtrVT = getPointerTy();
1891 if (CP->isMachineConstantPoolEntry())
1892 Result = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1893 CP->getAlignment());
1895 Result = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1896 CP->getAlignment(), CP->getOffset());
1898 // Use LARL to load the address of the constant pool entry.
1899 return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1902 SDValue SystemZTargetLowering::lowerBITCAST(SDValue Op,
1903 SelectionDAG &DAG) const {
1905 SDValue In = Op.getOperand(0);
1906 EVT InVT = In.getValueType();
1907 EVT ResVT = Op.getValueType();
1909 if (InVT == MVT::i32 && ResVT == MVT::f32) {
1911 if (Subtarget.hasHighWord()) {
1912 SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL,
1914 In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h32, DL,
1915 MVT::i64, SDValue(U64, 0), In);
1917 In64 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, In);
1918 In64 = DAG.getNode(ISD::SHL, DL, MVT::i64, In64,
1919 DAG.getConstant(32, MVT::i64));
1921 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::f64, In64);
1922 return DAG.getTargetExtractSubreg(SystemZ::subreg_h32,
1923 DL, MVT::f32, Out64);
1925 if (InVT == MVT::f32 && ResVT == MVT::i32) {
1926 SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::f64);
1927 SDValue In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h32, DL,
1928 MVT::f64, SDValue(U64, 0), In);
1929 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::i64, In64);
1930 if (Subtarget.hasHighWord())
1931 return DAG.getTargetExtractSubreg(SystemZ::subreg_h32, DL,
1933 SDValue Shift = DAG.getNode(ISD::SRL, DL, MVT::i64, Out64,
1934 DAG.getConstant(32, MVT::i64));
1935 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Shift);
1937 llvm_unreachable("Unexpected bitcast combination");
1940 SDValue SystemZTargetLowering::lowerVASTART(SDValue Op,
1941 SelectionDAG &DAG) const {
1942 MachineFunction &MF = DAG.getMachineFunction();
1943 SystemZMachineFunctionInfo *FuncInfo =
1944 MF.getInfo<SystemZMachineFunctionInfo>();
1945 EVT PtrVT = getPointerTy();
1947 SDValue Chain = Op.getOperand(0);
1948 SDValue Addr = Op.getOperand(1);
1949 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1952 // The initial values of each field.
1953 const unsigned NumFields = 4;
1954 SDValue Fields[NumFields] = {
1955 DAG.getConstant(FuncInfo->getVarArgsFirstGPR(), PtrVT),
1956 DAG.getConstant(FuncInfo->getVarArgsFirstFPR(), PtrVT),
1957 DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT),
1958 DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT)
1961 // Store each field into its respective slot.
1962 SDValue MemOps[NumFields];
1963 unsigned Offset = 0;
1964 for (unsigned I = 0; I < NumFields; ++I) {
1965 SDValue FieldAddr = Addr;
1967 FieldAddr = DAG.getNode(ISD::ADD, DL, PtrVT, FieldAddr,
1968 DAG.getIntPtrConstant(Offset));
1969 MemOps[I] = DAG.getStore(Chain, DL, Fields[I], FieldAddr,
1970 MachinePointerInfo(SV, Offset),
1974 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps, NumFields);
1977 SDValue SystemZTargetLowering::lowerVACOPY(SDValue Op,
1978 SelectionDAG &DAG) const {
1979 SDValue Chain = Op.getOperand(0);
1980 SDValue DstPtr = Op.getOperand(1);
1981 SDValue SrcPtr = Op.getOperand(2);
1982 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
1983 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
1986 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, DAG.getIntPtrConstant(32),
1987 /*Align*/8, /*isVolatile*/false, /*AlwaysInline*/false,
1988 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
1991 SDValue SystemZTargetLowering::
1992 lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
1993 SDValue Chain = Op.getOperand(0);
1994 SDValue Size = Op.getOperand(1);
1997 unsigned SPReg = getStackPointerRegisterToSaveRestore();
1999 // Get a reference to the stack pointer.
2000 SDValue OldSP = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i64);
2002 // Get the new stack pointer value.
2003 SDValue NewSP = DAG.getNode(ISD::SUB, DL, MVT::i64, OldSP, Size);
2005 // Copy the new stack pointer back.
2006 Chain = DAG.getCopyToReg(Chain, DL, SPReg, NewSP);
2008 // The allocated data lives above the 160 bytes allocated for the standard
2009 // frame, plus any outgoing stack arguments. We don't know how much that
2010 // amounts to yet, so emit a special ADJDYNALLOC placeholder.
2011 SDValue ArgAdjust = DAG.getNode(SystemZISD::ADJDYNALLOC, DL, MVT::i64);
2012 SDValue Result = DAG.getNode(ISD::ADD, DL, MVT::i64, NewSP, ArgAdjust);
2014 SDValue Ops[2] = { Result, Chain };
2015 return DAG.getMergeValues(Ops, 2, DL);
2018 SDValue SystemZTargetLowering::lowerSMUL_LOHI(SDValue Op,
2019 SelectionDAG &DAG) const {
2020 EVT VT = Op.getValueType();
2024 // Just do a normal 64-bit multiplication and extract the results.
2025 // We define this so that it can be used for constant division.
2026 lowerMUL_LOHI32(DAG, DL, ISD::SIGN_EXTEND, Op.getOperand(0),
2027 Op.getOperand(1), Ops[1], Ops[0]);
2029 // Do a full 128-bit multiplication based on UMUL_LOHI64:
2031 // (ll * rl) + ((lh * rl) << 64) + ((ll * rh) << 64)
2033 // but using the fact that the upper halves are either all zeros
2036 // (ll * rl) - ((lh & rl) << 64) - ((ll & rh) << 64)
2038 // and grouping the right terms together since they are quicker than the
2041 // (ll * rl) - (((lh & rl) + (ll & rh)) << 64)
2042 SDValue C63 = DAG.getConstant(63, MVT::i64);
2043 SDValue LL = Op.getOperand(0);
2044 SDValue RL = Op.getOperand(1);
2045 SDValue LH = DAG.getNode(ISD::SRA, DL, VT, LL, C63);
2046 SDValue RH = DAG.getNode(ISD::SRA, DL, VT, RL, C63);
2047 // UMUL_LOHI64 returns the low result in the odd register and the high
2048 // result in the even register. SMUL_LOHI is defined to return the
2049 // low half first, so the results are in reverse order.
2050 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
2051 LL, RL, Ops[1], Ops[0]);
2052 SDValue NegLLTimesRH = DAG.getNode(ISD::AND, DL, VT, LL, RH);
2053 SDValue NegLHTimesRL = DAG.getNode(ISD::AND, DL, VT, LH, RL);
2054 SDValue NegSum = DAG.getNode(ISD::ADD, DL, VT, NegLLTimesRH, NegLHTimesRL);
2055 Ops[1] = DAG.getNode(ISD::SUB, DL, VT, Ops[1], NegSum);
2057 return DAG.getMergeValues(Ops, 2, DL);
2060 SDValue SystemZTargetLowering::lowerUMUL_LOHI(SDValue Op,
2061 SelectionDAG &DAG) const {
2062 EVT VT = Op.getValueType();
2066 // Just do a normal 64-bit multiplication and extract the results.
2067 // We define this so that it can be used for constant division.
2068 lowerMUL_LOHI32(DAG, DL, ISD::ZERO_EXTEND, Op.getOperand(0),
2069 Op.getOperand(1), Ops[1], Ops[0]);
2071 // UMUL_LOHI64 returns the low result in the odd register and the high
2072 // result in the even register. UMUL_LOHI is defined to return the
2073 // low half first, so the results are in reverse order.
2074 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
2075 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
2076 return DAG.getMergeValues(Ops, 2, DL);
2079 SDValue SystemZTargetLowering::lowerSDIVREM(SDValue Op,
2080 SelectionDAG &DAG) const {
2081 SDValue Op0 = Op.getOperand(0);
2082 SDValue Op1 = Op.getOperand(1);
2083 EVT VT = Op.getValueType();
2087 // We use DSGF for 32-bit division.
2089 Op0 = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op0);
2090 Opcode = SystemZISD::SDIVREM32;
2091 } else if (DAG.ComputeNumSignBits(Op1) > 32) {
2092 Op1 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op1);
2093 Opcode = SystemZISD::SDIVREM32;
2095 Opcode = SystemZISD::SDIVREM64;
2097 // DSG(F) takes a 64-bit dividend, so the even register in the GR128
2098 // input is "don't care". The instruction returns the remainder in
2099 // the even register and the quotient in the odd register.
2101 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, Opcode,
2102 Op0, Op1, Ops[1], Ops[0]);
2103 return DAG.getMergeValues(Ops, 2, DL);
2106 SDValue SystemZTargetLowering::lowerUDIVREM(SDValue Op,
2107 SelectionDAG &DAG) const {
2108 EVT VT = Op.getValueType();
2111 // DL(G) uses a double-width dividend, so we need to clear the even
2112 // register in the GR128 input. The instruction returns the remainder
2113 // in the even register and the quotient in the odd register.
2116 lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_32, SystemZISD::UDIVREM32,
2117 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
2119 lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_64, SystemZISD::UDIVREM64,
2120 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
2121 return DAG.getMergeValues(Ops, 2, DL);
2124 SDValue SystemZTargetLowering::lowerOR(SDValue Op, SelectionDAG &DAG) const {
2125 assert(Op.getValueType() == MVT::i64 && "Should be 64-bit operation");
2127 // Get the known-zero masks for each operand.
2128 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1) };
2129 APInt KnownZero[2], KnownOne[2];
2130 DAG.ComputeMaskedBits(Ops[0], KnownZero[0], KnownOne[0]);
2131 DAG.ComputeMaskedBits(Ops[1], KnownZero[1], KnownOne[1]);
2133 // See if the upper 32 bits of one operand and the lower 32 bits of the
2134 // other are known zero. They are the low and high operands respectively.
2135 uint64_t Masks[] = { KnownZero[0].getZExtValue(),
2136 KnownZero[1].getZExtValue() };
2138 if ((Masks[0] >> 32) == 0xffffffff && uint32_t(Masks[1]) == 0xffffffff)
2140 else if ((Masks[1] >> 32) == 0xffffffff && uint32_t(Masks[0]) == 0xffffffff)
2145 SDValue LowOp = Ops[Low];
2146 SDValue HighOp = Ops[High];
2148 // If the high part is a constant, we're better off using IILH.
2149 if (HighOp.getOpcode() == ISD::Constant)
2152 // If the low part is a constant that is outside the range of LHI,
2153 // then we're better off using IILF.
2154 if (LowOp.getOpcode() == ISD::Constant) {
2155 int64_t Value = int32_t(cast<ConstantSDNode>(LowOp)->getZExtValue());
2156 if (!isInt<16>(Value))
2160 // Check whether the high part is an AND that doesn't change the
2161 // high 32 bits and just masks out low bits. We can skip it if so.
2162 if (HighOp.getOpcode() == ISD::AND &&
2163 HighOp.getOperand(1).getOpcode() == ISD::Constant) {
2164 SDValue HighOp0 = HighOp.getOperand(0);
2165 uint64_t Mask = cast<ConstantSDNode>(HighOp.getOperand(1))->getZExtValue();
2166 if (DAG.MaskedValueIsZero(HighOp0, APInt(64, ~(Mask | 0xffffffff))))
2170 // Take advantage of the fact that all GR32 operations only change the
2171 // low 32 bits by truncating Low to an i32 and inserting it directly
2172 // using a subreg. The interesting cases are those where the truncation
2175 SDValue Low32 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, LowOp);
2176 return DAG.getTargetInsertSubreg(SystemZ::subreg_l32, DL,
2177 MVT::i64, HighOp, Low32);
2180 // Op is an atomic load. Lower it into a normal volatile load.
2181 SDValue SystemZTargetLowering::lowerATOMIC_LOAD(SDValue Op,
2182 SelectionDAG &DAG) const {
2183 auto *Node = cast<AtomicSDNode>(Op.getNode());
2184 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), Op.getValueType(),
2185 Node->getChain(), Node->getBasePtr(),
2186 Node->getMemoryVT(), Node->getMemOperand());
2189 // Op is an atomic store. Lower it into a normal volatile store followed
2190 // by a serialization.
2191 SDValue SystemZTargetLowering::lowerATOMIC_STORE(SDValue Op,
2192 SelectionDAG &DAG) const {
2193 auto *Node = cast<AtomicSDNode>(Op.getNode());
2194 SDValue Chain = DAG.getTruncStore(Node->getChain(), SDLoc(Op), Node->getVal(),
2195 Node->getBasePtr(), Node->getMemoryVT(),
2196 Node->getMemOperand());
2197 return SDValue(DAG.getMachineNode(SystemZ::Serialize, SDLoc(Op), MVT::Other,
2201 // Op is an 8-, 16-bit or 32-bit ATOMIC_LOAD_* operation. Lower the first
2202 // two into the fullword ATOMIC_LOADW_* operation given by Opcode.
2203 SDValue SystemZTargetLowering::lowerATOMIC_LOAD_OP(SDValue Op,
2205 unsigned Opcode) const {
2206 auto *Node = cast<AtomicSDNode>(Op.getNode());
2208 // 32-bit operations need no code outside the main loop.
2209 EVT NarrowVT = Node->getMemoryVT();
2210 EVT WideVT = MVT::i32;
2211 if (NarrowVT == WideVT)
2214 int64_t BitSize = NarrowVT.getSizeInBits();
2215 SDValue ChainIn = Node->getChain();
2216 SDValue Addr = Node->getBasePtr();
2217 SDValue Src2 = Node->getVal();
2218 MachineMemOperand *MMO = Node->getMemOperand();
2220 EVT PtrVT = Addr.getValueType();
2222 // Convert atomic subtracts of constants into additions.
2223 if (Opcode == SystemZISD::ATOMIC_LOADW_SUB)
2224 if (auto *Const = dyn_cast<ConstantSDNode>(Src2)) {
2225 Opcode = SystemZISD::ATOMIC_LOADW_ADD;
2226 Src2 = DAG.getConstant(-Const->getSExtValue(), Src2.getValueType());
2229 // Get the address of the containing word.
2230 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
2231 DAG.getConstant(-4, PtrVT));
2233 // Get the number of bits that the word must be rotated left in order
2234 // to bring the field to the top bits of a GR32.
2235 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
2236 DAG.getConstant(3, PtrVT));
2237 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
2239 // Get the complementing shift amount, for rotating a field in the top
2240 // bits back to its proper position.
2241 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
2242 DAG.getConstant(0, WideVT), BitShift);
2244 // Extend the source operand to 32 bits and prepare it for the inner loop.
2245 // ATOMIC_SWAPW uses RISBG to rotate the field left, but all other
2246 // operations require the source to be shifted in advance. (This shift
2247 // can be folded if the source is constant.) For AND and NAND, the lower
2248 // bits must be set, while for other opcodes they should be left clear.
2249 if (Opcode != SystemZISD::ATOMIC_SWAPW)
2250 Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2,
2251 DAG.getConstant(32 - BitSize, WideVT));
2252 if (Opcode == SystemZISD::ATOMIC_LOADW_AND ||
2253 Opcode == SystemZISD::ATOMIC_LOADW_NAND)
2254 Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2,
2255 DAG.getConstant(uint32_t(-1) >> BitSize, WideVT));
2257 // Construct the ATOMIC_LOADW_* node.
2258 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
2259 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift,
2260 DAG.getConstant(BitSize, WideVT) };
2261 SDValue AtomicOp = DAG.getMemIntrinsicNode(Opcode, DL, VTList, Ops,
2262 array_lengthof(Ops),
2265 // Rotate the result of the final CS so that the field is in the lower
2266 // bits of a GR32, then truncate it.
2267 SDValue ResultShift = DAG.getNode(ISD::ADD, DL, WideVT, BitShift,
2268 DAG.getConstant(BitSize, WideVT));
2269 SDValue Result = DAG.getNode(ISD::ROTL, DL, WideVT, AtomicOp, ResultShift);
2271 SDValue RetOps[2] = { Result, AtomicOp.getValue(1) };
2272 return DAG.getMergeValues(RetOps, 2, DL);
2275 // Op is an ATOMIC_LOAD_SUB operation. Lower 8- and 16-bit operations
2276 // into ATOMIC_LOADW_SUBs and decide whether to convert 32- and 64-bit
2277 // operations into additions.
2278 SDValue SystemZTargetLowering::lowerATOMIC_LOAD_SUB(SDValue Op,
2279 SelectionDAG &DAG) const {
2280 auto *Node = cast<AtomicSDNode>(Op.getNode());
2281 EVT MemVT = Node->getMemoryVT();
2282 if (MemVT == MVT::i32 || MemVT == MVT::i64) {
2283 // A full-width operation.
2284 assert(Op.getValueType() == MemVT && "Mismatched VTs");
2285 SDValue Src2 = Node->getVal();
2289 if (auto *Op2 = dyn_cast<ConstantSDNode>(Src2)) {
2290 // Use an addition if the operand is constant and either LAA(G) is
2291 // available or the negative value is in the range of A(G)FHI.
2292 int64_t Value = (-Op2->getAPIntValue()).getSExtValue();
2293 if (isInt<32>(Value) || TM.getSubtargetImpl()->hasInterlockedAccess1())
2294 NegSrc2 = DAG.getConstant(Value, MemVT);
2295 } else if (TM.getSubtargetImpl()->hasInterlockedAccess1())
2296 // Use LAA(G) if available.
2297 NegSrc2 = DAG.getNode(ISD::SUB, DL, MemVT, DAG.getConstant(0, MemVT),
2300 if (NegSrc2.getNode())
2301 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, DL, MemVT,
2302 Node->getChain(), Node->getBasePtr(), NegSrc2,
2303 Node->getMemOperand(), Node->getOrdering(),
2304 Node->getSynchScope());
2306 // Use the node as-is.
2310 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_SUB);
2313 // Node is an 8- or 16-bit ATOMIC_CMP_SWAP operation. Lower the first two
2314 // into a fullword ATOMIC_CMP_SWAPW operation.
2315 SDValue SystemZTargetLowering::lowerATOMIC_CMP_SWAP(SDValue Op,
2316 SelectionDAG &DAG) const {
2317 auto *Node = cast<AtomicSDNode>(Op.getNode());
2319 // We have native support for 32-bit compare and swap.
2320 EVT NarrowVT = Node->getMemoryVT();
2321 EVT WideVT = MVT::i32;
2322 if (NarrowVT == WideVT)
2325 int64_t BitSize = NarrowVT.getSizeInBits();
2326 SDValue ChainIn = Node->getOperand(0);
2327 SDValue Addr = Node->getOperand(1);
2328 SDValue CmpVal = Node->getOperand(2);
2329 SDValue SwapVal = Node->getOperand(3);
2330 MachineMemOperand *MMO = Node->getMemOperand();
2332 EVT PtrVT = Addr.getValueType();
2334 // Get the address of the containing word.
2335 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
2336 DAG.getConstant(-4, PtrVT));
2338 // Get the number of bits that the word must be rotated left in order
2339 // to bring the field to the top bits of a GR32.
2340 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
2341 DAG.getConstant(3, PtrVT));
2342 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
2344 // Get the complementing shift amount, for rotating a field in the top
2345 // bits back to its proper position.
2346 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
2347 DAG.getConstant(0, WideVT), BitShift);
2349 // Construct the ATOMIC_CMP_SWAPW node.
2350 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
2351 SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift,
2352 NegBitShift, DAG.getConstant(BitSize, WideVT) };
2353 SDValue AtomicOp = DAG.getMemIntrinsicNode(SystemZISD::ATOMIC_CMP_SWAPW, DL,
2354 VTList, Ops, array_lengthof(Ops),
2359 SDValue SystemZTargetLowering::lowerSTACKSAVE(SDValue Op,
2360 SelectionDAG &DAG) const {
2361 MachineFunction &MF = DAG.getMachineFunction();
2362 MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
2363 return DAG.getCopyFromReg(Op.getOperand(0), SDLoc(Op),
2364 SystemZ::R15D, Op.getValueType());
2367 SDValue SystemZTargetLowering::lowerSTACKRESTORE(SDValue Op,
2368 SelectionDAG &DAG) const {
2369 MachineFunction &MF = DAG.getMachineFunction();
2370 MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
2371 return DAG.getCopyToReg(Op.getOperand(0), SDLoc(Op),
2372 SystemZ::R15D, Op.getOperand(1));
2375 SDValue SystemZTargetLowering::lowerPREFETCH(SDValue Op,
2376 SelectionDAG &DAG) const {
2377 bool IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
2379 // Just preserve the chain.
2380 return Op.getOperand(0);
2382 bool IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
2383 unsigned Code = IsWrite ? SystemZ::PFD_WRITE : SystemZ::PFD_READ;
2384 auto *Node = cast<MemIntrinsicSDNode>(Op.getNode());
2387 DAG.getConstant(Code, MVT::i32),
2390 return DAG.getMemIntrinsicNode(SystemZISD::PREFETCH, SDLoc(Op),
2391 Node->getVTList(), Ops, array_lengthof(Ops),
2392 Node->getMemoryVT(), Node->getMemOperand());
2395 SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
2396 SelectionDAG &DAG) const {
2397 switch (Op.getOpcode()) {
2399 return lowerBR_CC(Op, DAG);
2400 case ISD::SELECT_CC:
2401 return lowerSELECT_CC(Op, DAG);
2403 return lowerSETCC(Op, DAG);
2404 case ISD::GlobalAddress:
2405 return lowerGlobalAddress(cast<GlobalAddressSDNode>(Op), DAG);
2406 case ISD::GlobalTLSAddress:
2407 return lowerGlobalTLSAddress(cast<GlobalAddressSDNode>(Op), DAG);
2408 case ISD::BlockAddress:
2409 return lowerBlockAddress(cast<BlockAddressSDNode>(Op), DAG);
2410 case ISD::JumpTable:
2411 return lowerJumpTable(cast<JumpTableSDNode>(Op), DAG);
2412 case ISD::ConstantPool:
2413 return lowerConstantPool(cast<ConstantPoolSDNode>(Op), DAG);
2415 return lowerBITCAST(Op, DAG);
2417 return lowerVASTART(Op, DAG);
2419 return lowerVACOPY(Op, DAG);
2420 case ISD::DYNAMIC_STACKALLOC:
2421 return lowerDYNAMIC_STACKALLOC(Op, DAG);
2422 case ISD::SMUL_LOHI:
2423 return lowerSMUL_LOHI(Op, DAG);
2424 case ISD::UMUL_LOHI:
2425 return lowerUMUL_LOHI(Op, DAG);
2427 return lowerSDIVREM(Op, DAG);
2429 return lowerUDIVREM(Op, DAG);
2431 return lowerOR(Op, DAG);
2432 case ISD::ATOMIC_SWAP:
2433 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_SWAPW);
2434 case ISD::ATOMIC_STORE:
2435 return lowerATOMIC_STORE(Op, DAG);
2436 case ISD::ATOMIC_LOAD:
2437 return lowerATOMIC_LOAD(Op, DAG);
2438 case ISD::ATOMIC_LOAD_ADD:
2439 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_ADD);
2440 case ISD::ATOMIC_LOAD_SUB:
2441 return lowerATOMIC_LOAD_SUB(Op, DAG);
2442 case ISD::ATOMIC_LOAD_AND:
2443 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_AND);
2444 case ISD::ATOMIC_LOAD_OR:
2445 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_OR);
2446 case ISD::ATOMIC_LOAD_XOR:
2447 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_XOR);
2448 case ISD::ATOMIC_LOAD_NAND:
2449 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_NAND);
2450 case ISD::ATOMIC_LOAD_MIN:
2451 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_MIN);
2452 case ISD::ATOMIC_LOAD_MAX:
2453 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_MAX);
2454 case ISD::ATOMIC_LOAD_UMIN:
2455 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_UMIN);
2456 case ISD::ATOMIC_LOAD_UMAX:
2457 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_UMAX);
2458 case ISD::ATOMIC_CMP_SWAP:
2459 return lowerATOMIC_CMP_SWAP(Op, DAG);
2460 case ISD::STACKSAVE:
2461 return lowerSTACKSAVE(Op, DAG);
2462 case ISD::STACKRESTORE:
2463 return lowerSTACKRESTORE(Op, DAG);
2465 return lowerPREFETCH(Op, DAG);
2467 llvm_unreachable("Unexpected node to lower");
2471 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
2472 #define OPCODE(NAME) case SystemZISD::NAME: return "SystemZISD::" #NAME
2477 OPCODE(PCREL_WRAPPER);
2478 OPCODE(PCREL_OFFSET);
2484 OPCODE(SELECT_CCMASK);
2485 OPCODE(ADJDYNALLOC);
2486 OPCODE(EXTRACT_ACCESS);
2487 OPCODE(UMUL_LOHI64);
2503 OPCODE(SEARCH_STRING);
2506 OPCODE(ATOMIC_SWAPW);
2507 OPCODE(ATOMIC_LOADW_ADD);
2508 OPCODE(ATOMIC_LOADW_SUB);
2509 OPCODE(ATOMIC_LOADW_AND);
2510 OPCODE(ATOMIC_LOADW_OR);
2511 OPCODE(ATOMIC_LOADW_XOR);
2512 OPCODE(ATOMIC_LOADW_NAND);
2513 OPCODE(ATOMIC_LOADW_MIN);
2514 OPCODE(ATOMIC_LOADW_MAX);
2515 OPCODE(ATOMIC_LOADW_UMIN);
2516 OPCODE(ATOMIC_LOADW_UMAX);
2517 OPCODE(ATOMIC_CMP_SWAPW);
2524 SDValue SystemZTargetLowering::PerformDAGCombine(SDNode *N,
2525 DAGCombinerInfo &DCI) const {
2526 SelectionDAG &DAG = DCI.DAG;
2527 unsigned Opcode = N->getOpcode();
2528 if (Opcode == ISD::SIGN_EXTEND) {
2529 // Convert (sext (ashr (shl X, C1), C2)) to
2530 // (ashr (shl (anyext X), C1'), C2')), since wider shifts are as
2531 // cheap as narrower ones.
2532 SDValue N0 = N->getOperand(0);
2533 EVT VT = N->getValueType(0);
2534 if (N0.hasOneUse() && N0.getOpcode() == ISD::SRA) {
2535 auto *SraAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2536 SDValue Inner = N0.getOperand(0);
2537 if (SraAmt && Inner.hasOneUse() && Inner.getOpcode() == ISD::SHL) {
2538 if (auto *ShlAmt = dyn_cast<ConstantSDNode>(Inner.getOperand(1))) {
2539 unsigned Extra = (VT.getSizeInBits() -
2540 N0.getValueType().getSizeInBits());
2541 unsigned NewShlAmt = ShlAmt->getZExtValue() + Extra;
2542 unsigned NewSraAmt = SraAmt->getZExtValue() + Extra;
2543 EVT ShiftVT = N0.getOperand(1).getValueType();
2544 SDValue Ext = DAG.getNode(ISD::ANY_EXTEND, SDLoc(Inner), VT,
2545 Inner.getOperand(0));
2546 SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(Inner), VT, Ext,
2547 DAG.getConstant(NewShlAmt, ShiftVT));
2548 return DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl,
2549 DAG.getConstant(NewSraAmt, ShiftVT));
2557 //===----------------------------------------------------------------------===//
2559 //===----------------------------------------------------------------------===//
2561 // Create a new basic block after MBB.
2562 static MachineBasicBlock *emitBlockAfter(MachineBasicBlock *MBB) {
2563 MachineFunction &MF = *MBB->getParent();
2564 MachineBasicBlock *NewMBB = MF.CreateMachineBasicBlock(MBB->getBasicBlock());
2565 MF.insert(std::next(MachineFunction::iterator(MBB)), NewMBB);
2569 // Split MBB after MI and return the new block (the one that contains
2570 // instructions after MI).
2571 static MachineBasicBlock *splitBlockAfter(MachineInstr *MI,
2572 MachineBasicBlock *MBB) {
2573 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
2574 NewMBB->splice(NewMBB->begin(), MBB,
2575 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
2576 NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
2580 // Split MBB before MI and return the new block (the one that contains MI).
2581 static MachineBasicBlock *splitBlockBefore(MachineInstr *MI,
2582 MachineBasicBlock *MBB) {
2583 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
2584 NewMBB->splice(NewMBB->begin(), MBB, MI, MBB->end());
2585 NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
2589 // Force base value Base into a register before MI. Return the register.
2590 static unsigned forceReg(MachineInstr *MI, MachineOperand &Base,
2591 const SystemZInstrInfo *TII) {
2593 return Base.getReg();
2595 MachineBasicBlock *MBB = MI->getParent();
2596 MachineFunction &MF = *MBB->getParent();
2597 MachineRegisterInfo &MRI = MF.getRegInfo();
2599 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
2600 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LA), Reg)
2601 .addOperand(Base).addImm(0).addReg(0);
2605 // Implement EmitInstrWithCustomInserter for pseudo Select* instruction MI.
2607 SystemZTargetLowering::emitSelect(MachineInstr *MI,
2608 MachineBasicBlock *MBB) const {
2609 const SystemZInstrInfo *TII = TM.getInstrInfo();
2611 unsigned DestReg = MI->getOperand(0).getReg();
2612 unsigned TrueReg = MI->getOperand(1).getReg();
2613 unsigned FalseReg = MI->getOperand(2).getReg();
2614 unsigned CCValid = MI->getOperand(3).getImm();
2615 unsigned CCMask = MI->getOperand(4).getImm();
2616 DebugLoc DL = MI->getDebugLoc();
2618 MachineBasicBlock *StartMBB = MBB;
2619 MachineBasicBlock *JoinMBB = splitBlockBefore(MI, MBB);
2620 MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
2623 // BRC CCMask, JoinMBB
2624 // # fallthrough to FalseMBB
2626 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2627 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
2628 MBB->addSuccessor(JoinMBB);
2629 MBB->addSuccessor(FalseMBB);
2632 // # fallthrough to JoinMBB
2634 MBB->addSuccessor(JoinMBB);
2637 // %Result = phi [ %FalseReg, FalseMBB ], [ %TrueReg, StartMBB ]
2640 BuildMI(*MBB, MI, DL, TII->get(SystemZ::PHI), DestReg)
2641 .addReg(TrueReg).addMBB(StartMBB)
2642 .addReg(FalseReg).addMBB(FalseMBB);
2644 MI->eraseFromParent();
2648 // Implement EmitInstrWithCustomInserter for pseudo CondStore* instruction MI.
2649 // StoreOpcode is the store to use and Invert says whether the store should
2650 // happen when the condition is false rather than true. If a STORE ON
2651 // CONDITION is available, STOCOpcode is its opcode, otherwise it is 0.
2653 SystemZTargetLowering::emitCondStore(MachineInstr *MI,
2654 MachineBasicBlock *MBB,
2655 unsigned StoreOpcode, unsigned STOCOpcode,
2656 bool Invert) const {
2657 const SystemZInstrInfo *TII = TM.getInstrInfo();
2659 unsigned SrcReg = MI->getOperand(0).getReg();
2660 MachineOperand Base = MI->getOperand(1);
2661 int64_t Disp = MI->getOperand(2).getImm();
2662 unsigned IndexReg = MI->getOperand(3).getReg();
2663 unsigned CCValid = MI->getOperand(4).getImm();
2664 unsigned CCMask = MI->getOperand(5).getImm();
2665 DebugLoc DL = MI->getDebugLoc();
2667 StoreOpcode = TII->getOpcodeForOffset(StoreOpcode, Disp);
2669 // Use STOCOpcode if possible. We could use different store patterns in
2670 // order to avoid matching the index register, but the performance trade-offs
2671 // might be more complicated in that case.
2672 if (STOCOpcode && !IndexReg && TM.getSubtargetImpl()->hasLoadStoreOnCond()) {
2675 BuildMI(*MBB, MI, DL, TII->get(STOCOpcode))
2676 .addReg(SrcReg).addOperand(Base).addImm(Disp)
2677 .addImm(CCValid).addImm(CCMask);
2678 MI->eraseFromParent();
2682 // Get the condition needed to branch around the store.
2686 MachineBasicBlock *StartMBB = MBB;
2687 MachineBasicBlock *JoinMBB = splitBlockBefore(MI, MBB);
2688 MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
2691 // BRC CCMask, JoinMBB
2692 // # fallthrough to FalseMBB
2694 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2695 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
2696 MBB->addSuccessor(JoinMBB);
2697 MBB->addSuccessor(FalseMBB);
2700 // store %SrcReg, %Disp(%Index,%Base)
2701 // # fallthrough to JoinMBB
2703 BuildMI(MBB, DL, TII->get(StoreOpcode))
2704 .addReg(SrcReg).addOperand(Base).addImm(Disp).addReg(IndexReg);
2705 MBB->addSuccessor(JoinMBB);
2707 MI->eraseFromParent();
2711 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_LOAD{,W}_*
2712 // or ATOMIC_SWAP{,W} instruction MI. BinOpcode is the instruction that
2713 // performs the binary operation elided by "*", or 0 for ATOMIC_SWAP{,W}.
2714 // BitSize is the width of the field in bits, or 0 if this is a partword
2715 // ATOMIC_LOADW_* or ATOMIC_SWAPW instruction, in which case the bitsize
2716 // is one of the operands. Invert says whether the field should be
2717 // inverted after performing BinOpcode (e.g. for NAND).
2719 SystemZTargetLowering::emitAtomicLoadBinary(MachineInstr *MI,
2720 MachineBasicBlock *MBB,
2723 bool Invert) const {
2724 const SystemZInstrInfo *TII = TM.getInstrInfo();
2725 MachineFunction &MF = *MBB->getParent();
2726 MachineRegisterInfo &MRI = MF.getRegInfo();
2727 bool IsSubWord = (BitSize < 32);
2729 // Extract the operands. Base can be a register or a frame index.
2730 // Src2 can be a register or immediate.
2731 unsigned Dest = MI->getOperand(0).getReg();
2732 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
2733 int64_t Disp = MI->getOperand(2).getImm();
2734 MachineOperand Src2 = earlyUseOperand(MI->getOperand(3));
2735 unsigned BitShift = (IsSubWord ? MI->getOperand(4).getReg() : 0);
2736 unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0);
2737 DebugLoc DL = MI->getDebugLoc();
2739 BitSize = MI->getOperand(6).getImm();
2741 // Subword operations use 32-bit registers.
2742 const TargetRegisterClass *RC = (BitSize <= 32 ?
2743 &SystemZ::GR32BitRegClass :
2744 &SystemZ::GR64BitRegClass);
2745 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
2746 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
2748 // Get the right opcodes for the displacement.
2749 LOpcode = TII->getOpcodeForOffset(LOpcode, Disp);
2750 CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
2751 assert(LOpcode && CSOpcode && "Displacement out of range");
2753 // Create virtual registers for temporary results.
2754 unsigned OrigVal = MRI.createVirtualRegister(RC);
2755 unsigned OldVal = MRI.createVirtualRegister(RC);
2756 unsigned NewVal = (BinOpcode || IsSubWord ?
2757 MRI.createVirtualRegister(RC) : Src2.getReg());
2758 unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
2759 unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
2761 // Insert a basic block for the main loop.
2762 MachineBasicBlock *StartMBB = MBB;
2763 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
2764 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
2768 // %OrigVal = L Disp(%Base)
2769 // # fall through to LoopMMB
2771 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
2772 .addOperand(Base).addImm(Disp).addReg(0);
2773 MBB->addSuccessor(LoopMBB);
2776 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, LoopMBB ]
2777 // %RotatedOldVal = RLL %OldVal, 0(%BitShift)
2778 // %RotatedNewVal = OP %RotatedOldVal, %Src2
2779 // %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
2780 // %Dest = CS %OldVal, %NewVal, Disp(%Base)
2782 // # fall through to DoneMMB
2784 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
2785 .addReg(OrigVal).addMBB(StartMBB)
2786 .addReg(Dest).addMBB(LoopMBB);
2788 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
2789 .addReg(OldVal).addReg(BitShift).addImm(0);
2791 // Perform the operation normally and then invert every bit of the field.
2792 unsigned Tmp = MRI.createVirtualRegister(RC);
2793 BuildMI(MBB, DL, TII->get(BinOpcode), Tmp)
2794 .addReg(RotatedOldVal).addOperand(Src2);
2796 // XILF with the upper BitSize bits set.
2797 BuildMI(MBB, DL, TII->get(SystemZ::XILF), RotatedNewVal)
2798 .addReg(Tmp).addImm(uint32_t(~0 << (32 - BitSize)));
2799 else if (BitSize == 32)
2800 // XILF with every bit set.
2801 BuildMI(MBB, DL, TII->get(SystemZ::XILF), RotatedNewVal)
2802 .addReg(Tmp).addImm(~uint32_t(0));
2804 // Use LCGR and add -1 to the result, which is more compact than
2805 // an XILF, XILH pair.
2806 unsigned Tmp2 = MRI.createVirtualRegister(RC);
2807 BuildMI(MBB, DL, TII->get(SystemZ::LCGR), Tmp2).addReg(Tmp);
2808 BuildMI(MBB, DL, TII->get(SystemZ::AGHI), RotatedNewVal)
2809 .addReg(Tmp2).addImm(-1);
2811 } else if (BinOpcode)
2812 // A simply binary operation.
2813 BuildMI(MBB, DL, TII->get(BinOpcode), RotatedNewVal)
2814 .addReg(RotatedOldVal).addOperand(Src2);
2816 // Use RISBG to rotate Src2 into position and use it to replace the
2817 // field in RotatedOldVal.
2818 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedNewVal)
2819 .addReg(RotatedOldVal).addReg(Src2.getReg())
2820 .addImm(32).addImm(31 + BitSize).addImm(32 - BitSize);
2822 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
2823 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
2824 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
2825 .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
2826 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2827 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
2828 MBB->addSuccessor(LoopMBB);
2829 MBB->addSuccessor(DoneMBB);
2831 MI->eraseFromParent();
2835 // Implement EmitInstrWithCustomInserter for pseudo
2836 // ATOMIC_LOAD{,W}_{,U}{MIN,MAX} instruction MI. CompareOpcode is the
2837 // instruction that should be used to compare the current field with the
2838 // minimum or maximum value. KeepOldMask is the BRC condition-code mask
2839 // for when the current field should be kept. BitSize is the width of
2840 // the field in bits, or 0 if this is a partword ATOMIC_LOADW_* instruction.
2842 SystemZTargetLowering::emitAtomicLoadMinMax(MachineInstr *MI,
2843 MachineBasicBlock *MBB,
2844 unsigned CompareOpcode,
2845 unsigned KeepOldMask,
2846 unsigned BitSize) const {
2847 const SystemZInstrInfo *TII = TM.getInstrInfo();
2848 MachineFunction &MF = *MBB->getParent();
2849 MachineRegisterInfo &MRI = MF.getRegInfo();
2850 bool IsSubWord = (BitSize < 32);
2852 // Extract the operands. Base can be a register or a frame index.
2853 unsigned Dest = MI->getOperand(0).getReg();
2854 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
2855 int64_t Disp = MI->getOperand(2).getImm();
2856 unsigned Src2 = MI->getOperand(3).getReg();
2857 unsigned BitShift = (IsSubWord ? MI->getOperand(4).getReg() : 0);
2858 unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0);
2859 DebugLoc DL = MI->getDebugLoc();
2861 BitSize = MI->getOperand(6).getImm();
2863 // Subword operations use 32-bit registers.
2864 const TargetRegisterClass *RC = (BitSize <= 32 ?
2865 &SystemZ::GR32BitRegClass :
2866 &SystemZ::GR64BitRegClass);
2867 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
2868 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
2870 // Get the right opcodes for the displacement.
2871 LOpcode = TII->getOpcodeForOffset(LOpcode, Disp);
2872 CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
2873 assert(LOpcode && CSOpcode && "Displacement out of range");
2875 // Create virtual registers for temporary results.
2876 unsigned OrigVal = MRI.createVirtualRegister(RC);
2877 unsigned OldVal = MRI.createVirtualRegister(RC);
2878 unsigned NewVal = MRI.createVirtualRegister(RC);
2879 unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
2880 unsigned RotatedAltVal = (IsSubWord ? MRI.createVirtualRegister(RC) : Src2);
2881 unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
2883 // Insert 3 basic blocks for the loop.
2884 MachineBasicBlock *StartMBB = MBB;
2885 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
2886 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
2887 MachineBasicBlock *UseAltMBB = emitBlockAfter(LoopMBB);
2888 MachineBasicBlock *UpdateMBB = emitBlockAfter(UseAltMBB);
2892 // %OrigVal = L Disp(%Base)
2893 // # fall through to LoopMMB
2895 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
2896 .addOperand(Base).addImm(Disp).addReg(0);
2897 MBB->addSuccessor(LoopMBB);
2900 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, UpdateMBB ]
2901 // %RotatedOldVal = RLL %OldVal, 0(%BitShift)
2902 // CompareOpcode %RotatedOldVal, %Src2
2903 // BRC KeepOldMask, UpdateMBB
2905 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
2906 .addReg(OrigVal).addMBB(StartMBB)
2907 .addReg(Dest).addMBB(UpdateMBB);
2909 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
2910 .addReg(OldVal).addReg(BitShift).addImm(0);
2911 BuildMI(MBB, DL, TII->get(CompareOpcode))
2912 .addReg(RotatedOldVal).addReg(Src2);
2913 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2914 .addImm(SystemZ::CCMASK_ICMP).addImm(KeepOldMask).addMBB(UpdateMBB);
2915 MBB->addSuccessor(UpdateMBB);
2916 MBB->addSuccessor(UseAltMBB);
2919 // %RotatedAltVal = RISBG %RotatedOldVal, %Src2, 32, 31 + BitSize, 0
2920 // # fall through to UpdateMMB
2923 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedAltVal)
2924 .addReg(RotatedOldVal).addReg(Src2)
2925 .addImm(32).addImm(31 + BitSize).addImm(0);
2926 MBB->addSuccessor(UpdateMBB);
2929 // %RotatedNewVal = PHI [ %RotatedOldVal, LoopMBB ],
2930 // [ %RotatedAltVal, UseAltMBB ]
2931 // %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
2932 // %Dest = CS %OldVal, %NewVal, Disp(%Base)
2934 // # fall through to DoneMMB
2936 BuildMI(MBB, DL, TII->get(SystemZ::PHI), RotatedNewVal)
2937 .addReg(RotatedOldVal).addMBB(LoopMBB)
2938 .addReg(RotatedAltVal).addMBB(UseAltMBB);
2940 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
2941 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
2942 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
2943 .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
2944 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2945 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
2946 MBB->addSuccessor(LoopMBB);
2947 MBB->addSuccessor(DoneMBB);
2949 MI->eraseFromParent();
2953 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_CMP_SWAPW
2956 SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr *MI,
2957 MachineBasicBlock *MBB) const {
2958 const SystemZInstrInfo *TII = TM.getInstrInfo();
2959 MachineFunction &MF = *MBB->getParent();
2960 MachineRegisterInfo &MRI = MF.getRegInfo();
2962 // Extract the operands. Base can be a register or a frame index.
2963 unsigned Dest = MI->getOperand(0).getReg();
2964 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
2965 int64_t Disp = MI->getOperand(2).getImm();
2966 unsigned OrigCmpVal = MI->getOperand(3).getReg();
2967 unsigned OrigSwapVal = MI->getOperand(4).getReg();
2968 unsigned BitShift = MI->getOperand(5).getReg();
2969 unsigned NegBitShift = MI->getOperand(6).getReg();
2970 int64_t BitSize = MI->getOperand(7).getImm();
2971 DebugLoc DL = MI->getDebugLoc();
2973 const TargetRegisterClass *RC = &SystemZ::GR32BitRegClass;
2975 // Get the right opcodes for the displacement.
2976 unsigned LOpcode = TII->getOpcodeForOffset(SystemZ::L, Disp);
2977 unsigned CSOpcode = TII->getOpcodeForOffset(SystemZ::CS, Disp);
2978 assert(LOpcode && CSOpcode && "Displacement out of range");
2980 // Create virtual registers for temporary results.
2981 unsigned OrigOldVal = MRI.createVirtualRegister(RC);
2982 unsigned OldVal = MRI.createVirtualRegister(RC);
2983 unsigned CmpVal = MRI.createVirtualRegister(RC);
2984 unsigned SwapVal = MRI.createVirtualRegister(RC);
2985 unsigned StoreVal = MRI.createVirtualRegister(RC);
2986 unsigned RetryOldVal = MRI.createVirtualRegister(RC);
2987 unsigned RetryCmpVal = MRI.createVirtualRegister(RC);
2988 unsigned RetrySwapVal = MRI.createVirtualRegister(RC);
2990 // Insert 2 basic blocks for the loop.
2991 MachineBasicBlock *StartMBB = MBB;
2992 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
2993 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
2994 MachineBasicBlock *SetMBB = emitBlockAfter(LoopMBB);
2998 // %OrigOldVal = L Disp(%Base)
2999 // # fall through to LoopMMB
3001 BuildMI(MBB, DL, TII->get(LOpcode), OrigOldVal)
3002 .addOperand(Base).addImm(Disp).addReg(0);
3003 MBB->addSuccessor(LoopMBB);
3006 // %OldVal = phi [ %OrigOldVal, EntryBB ], [ %RetryOldVal, SetMBB ]
3007 // %CmpVal = phi [ %OrigCmpVal, EntryBB ], [ %RetryCmpVal, SetMBB ]
3008 // %SwapVal = phi [ %OrigSwapVal, EntryBB ], [ %RetrySwapVal, SetMBB ]
3009 // %Dest = RLL %OldVal, BitSize(%BitShift)
3010 // ^^ The low BitSize bits contain the field
3012 // %RetryCmpVal = RISBG32 %CmpVal, %Dest, 32, 63-BitSize, 0
3013 // ^^ Replace the upper 32-BitSize bits of the
3014 // comparison value with those that we loaded,
3015 // so that we can use a full word comparison.
3016 // CR %Dest, %RetryCmpVal
3018 // # Fall through to SetMBB
3020 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
3021 .addReg(OrigOldVal).addMBB(StartMBB)
3022 .addReg(RetryOldVal).addMBB(SetMBB);
3023 BuildMI(MBB, DL, TII->get(SystemZ::PHI), CmpVal)
3024 .addReg(OrigCmpVal).addMBB(StartMBB)
3025 .addReg(RetryCmpVal).addMBB(SetMBB);
3026 BuildMI(MBB, DL, TII->get(SystemZ::PHI), SwapVal)
3027 .addReg(OrigSwapVal).addMBB(StartMBB)
3028 .addReg(RetrySwapVal).addMBB(SetMBB);
3029 BuildMI(MBB, DL, TII->get(SystemZ::RLL), Dest)
3030 .addReg(OldVal).addReg(BitShift).addImm(BitSize);
3031 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetryCmpVal)
3032 .addReg(CmpVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
3033 BuildMI(MBB, DL, TII->get(SystemZ::CR))
3034 .addReg(Dest).addReg(RetryCmpVal);
3035 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
3036 .addImm(SystemZ::CCMASK_ICMP)
3037 .addImm(SystemZ::CCMASK_CMP_NE).addMBB(DoneMBB);
3038 MBB->addSuccessor(DoneMBB);
3039 MBB->addSuccessor(SetMBB);
3042 // %RetrySwapVal = RISBG32 %SwapVal, %Dest, 32, 63-BitSize, 0
3043 // ^^ Replace the upper 32-BitSize bits of the new
3044 // value with those that we loaded.
3045 // %StoreVal = RLL %RetrySwapVal, -BitSize(%NegBitShift)
3046 // ^^ Rotate the new field to its proper position.
3047 // %RetryOldVal = CS %Dest, %StoreVal, Disp(%Base)
3049 // # fall through to ExitMMB
3051 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetrySwapVal)
3052 .addReg(SwapVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
3053 BuildMI(MBB, DL, TII->get(SystemZ::RLL), StoreVal)
3054 .addReg(RetrySwapVal).addReg(NegBitShift).addImm(-BitSize);
3055 BuildMI(MBB, DL, TII->get(CSOpcode), RetryOldVal)
3056 .addReg(OldVal).addReg(StoreVal).addOperand(Base).addImm(Disp);
3057 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
3058 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
3059 MBB->addSuccessor(LoopMBB);
3060 MBB->addSuccessor(DoneMBB);
3062 MI->eraseFromParent();
3066 // Emit an extension from a GR32 or GR64 to a GR128. ClearEven is true
3067 // if the high register of the GR128 value must be cleared or false if
3068 // it's "don't care". SubReg is subreg_l32 when extending a GR32
3069 // and subreg_l64 when extending a GR64.
3071 SystemZTargetLowering::emitExt128(MachineInstr *MI,
3072 MachineBasicBlock *MBB,
3073 bool ClearEven, unsigned SubReg) const {
3074 const SystemZInstrInfo *TII = TM.getInstrInfo();
3075 MachineFunction &MF = *MBB->getParent();
3076 MachineRegisterInfo &MRI = MF.getRegInfo();
3077 DebugLoc DL = MI->getDebugLoc();
3079 unsigned Dest = MI->getOperand(0).getReg();
3080 unsigned Src = MI->getOperand(1).getReg();
3081 unsigned In128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
3083 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::IMPLICIT_DEF), In128);
3085 unsigned NewIn128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
3086 unsigned Zero64 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
3088 BuildMI(*MBB, MI, DL, TII->get(SystemZ::LLILL), Zero64)
3090 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), NewIn128)
3091 .addReg(In128).addReg(Zero64).addImm(SystemZ::subreg_h64);
3094 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dest)
3095 .addReg(In128).addReg(Src).addImm(SubReg);
3097 MI->eraseFromParent();
3102 SystemZTargetLowering::emitMemMemWrapper(MachineInstr *MI,
3103 MachineBasicBlock *MBB,
3104 unsigned Opcode) const {
3105 const SystemZInstrInfo *TII = TM.getInstrInfo();
3106 MachineFunction &MF = *MBB->getParent();
3107 MachineRegisterInfo &MRI = MF.getRegInfo();
3108 DebugLoc DL = MI->getDebugLoc();
3110 MachineOperand DestBase = earlyUseOperand(MI->getOperand(0));
3111 uint64_t DestDisp = MI->getOperand(1).getImm();
3112 MachineOperand SrcBase = earlyUseOperand(MI->getOperand(2));
3113 uint64_t SrcDisp = MI->getOperand(3).getImm();
3114 uint64_t Length = MI->getOperand(4).getImm();
3116 // When generating more than one CLC, all but the last will need to
3117 // branch to the end when a difference is found.
3118 MachineBasicBlock *EndMBB = (Length > 256 && Opcode == SystemZ::CLC ?
3119 splitBlockAfter(MI, MBB) : 0);
3121 // Check for the loop form, in which operand 5 is the trip count.
3122 if (MI->getNumExplicitOperands() > 5) {
3123 bool HaveSingleBase = DestBase.isIdenticalTo(SrcBase);
3125 uint64_t StartCountReg = MI->getOperand(5).getReg();
3126 uint64_t StartSrcReg = forceReg(MI, SrcBase, TII);
3127 uint64_t StartDestReg = (HaveSingleBase ? StartSrcReg :
3128 forceReg(MI, DestBase, TII));
3130 const TargetRegisterClass *RC = &SystemZ::ADDR64BitRegClass;
3131 uint64_t ThisSrcReg = MRI.createVirtualRegister(RC);
3132 uint64_t ThisDestReg = (HaveSingleBase ? ThisSrcReg :
3133 MRI.createVirtualRegister(RC));
3134 uint64_t NextSrcReg = MRI.createVirtualRegister(RC);
3135 uint64_t NextDestReg = (HaveSingleBase ? NextSrcReg :
3136 MRI.createVirtualRegister(RC));
3138 RC = &SystemZ::GR64BitRegClass;
3139 uint64_t ThisCountReg = MRI.createVirtualRegister(RC);
3140 uint64_t NextCountReg = MRI.createVirtualRegister(RC);
3142 MachineBasicBlock *StartMBB = MBB;
3143 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
3144 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
3145 MachineBasicBlock *NextMBB = (EndMBB ? emitBlockAfter(LoopMBB) : LoopMBB);
3148 // # fall through to LoopMMB
3149 MBB->addSuccessor(LoopMBB);
3152 // %ThisDestReg = phi [ %StartDestReg, StartMBB ],
3153 // [ %NextDestReg, NextMBB ]
3154 // %ThisSrcReg = phi [ %StartSrcReg, StartMBB ],
3155 // [ %NextSrcReg, NextMBB ]
3156 // %ThisCountReg = phi [ %StartCountReg, StartMBB ],
3157 // [ %NextCountReg, NextMBB ]
3158 // ( PFD 2, 768+DestDisp(%ThisDestReg) )
3159 // Opcode DestDisp(256,%ThisDestReg), SrcDisp(%ThisSrcReg)
3162 // The prefetch is used only for MVC. The JLH is used only for CLC.
3165 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisDestReg)
3166 .addReg(StartDestReg).addMBB(StartMBB)
3167 .addReg(NextDestReg).addMBB(NextMBB);
3168 if (!HaveSingleBase)
3169 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisSrcReg)
3170 .addReg(StartSrcReg).addMBB(StartMBB)
3171 .addReg(NextSrcReg).addMBB(NextMBB);
3172 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisCountReg)
3173 .addReg(StartCountReg).addMBB(StartMBB)
3174 .addReg(NextCountReg).addMBB(NextMBB);
3175 if (Opcode == SystemZ::MVC)
3176 BuildMI(MBB, DL, TII->get(SystemZ::PFD))
3177 .addImm(SystemZ::PFD_WRITE)
3178 .addReg(ThisDestReg).addImm(DestDisp + 768).addReg(0);
3179 BuildMI(MBB, DL, TII->get(Opcode))
3180 .addReg(ThisDestReg).addImm(DestDisp).addImm(256)
3181 .addReg(ThisSrcReg).addImm(SrcDisp);
3183 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
3184 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
3186 MBB->addSuccessor(EndMBB);
3187 MBB->addSuccessor(NextMBB);
3191 // %NextDestReg = LA 256(%ThisDestReg)
3192 // %NextSrcReg = LA 256(%ThisSrcReg)
3193 // %NextCountReg = AGHI %ThisCountReg, -1
3194 // CGHI %NextCountReg, 0
3196 // # fall through to DoneMMB
3198 // The AGHI, CGHI and JLH should be converted to BRCTG by later passes.
3201 BuildMI(MBB, DL, TII->get(SystemZ::LA), NextDestReg)
3202 .addReg(ThisDestReg).addImm(256).addReg(0);
3203 if (!HaveSingleBase)
3204 BuildMI(MBB, DL, TII->get(SystemZ::LA), NextSrcReg)
3205 .addReg(ThisSrcReg).addImm(256).addReg(0);
3206 BuildMI(MBB, DL, TII->get(SystemZ::AGHI), NextCountReg)
3207 .addReg(ThisCountReg).addImm(-1);
3208 BuildMI(MBB, DL, TII->get(SystemZ::CGHI))
3209 .addReg(NextCountReg).addImm(0);
3210 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
3211 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
3213 MBB->addSuccessor(LoopMBB);
3214 MBB->addSuccessor(DoneMBB);
3216 DestBase = MachineOperand::CreateReg(NextDestReg, false);
3217 SrcBase = MachineOperand::CreateReg(NextSrcReg, false);
3221 // Handle any remaining bytes with straight-line code.
3222 while (Length > 0) {
3223 uint64_t ThisLength = std::min(Length, uint64_t(256));
3224 // The previous iteration might have created out-of-range displacements.
3225 // Apply them using LAY if so.
3226 if (!isUInt<12>(DestDisp)) {
3227 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
3228 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LAY), Reg)
3229 .addOperand(DestBase).addImm(DestDisp).addReg(0);
3230 DestBase = MachineOperand::CreateReg(Reg, false);
3233 if (!isUInt<12>(SrcDisp)) {
3234 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
3235 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LAY), Reg)
3236 .addOperand(SrcBase).addImm(SrcDisp).addReg(0);
3237 SrcBase = MachineOperand::CreateReg(Reg, false);
3240 BuildMI(*MBB, MI, DL, TII->get(Opcode))
3241 .addOperand(DestBase).addImm(DestDisp).addImm(ThisLength)
3242 .addOperand(SrcBase).addImm(SrcDisp);
3243 DestDisp += ThisLength;
3244 SrcDisp += ThisLength;
3245 Length -= ThisLength;
3246 // If there's another CLC to go, branch to the end if a difference
3248 if (EndMBB && Length > 0) {
3249 MachineBasicBlock *NextMBB = splitBlockBefore(MI, MBB);
3250 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
3251 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
3253 MBB->addSuccessor(EndMBB);
3254 MBB->addSuccessor(NextMBB);
3259 MBB->addSuccessor(EndMBB);
3261 MBB->addLiveIn(SystemZ::CC);
3264 MI->eraseFromParent();
3268 // Decompose string pseudo-instruction MI into a loop that continually performs
3269 // Opcode until CC != 3.
3271 SystemZTargetLowering::emitStringWrapper(MachineInstr *MI,
3272 MachineBasicBlock *MBB,
3273 unsigned Opcode) const {
3274 const SystemZInstrInfo *TII = TM.getInstrInfo();
3275 MachineFunction &MF = *MBB->getParent();
3276 MachineRegisterInfo &MRI = MF.getRegInfo();
3277 DebugLoc DL = MI->getDebugLoc();
3279 uint64_t End1Reg = MI->getOperand(0).getReg();
3280 uint64_t Start1Reg = MI->getOperand(1).getReg();
3281 uint64_t Start2Reg = MI->getOperand(2).getReg();
3282 uint64_t CharReg = MI->getOperand(3).getReg();
3284 const TargetRegisterClass *RC = &SystemZ::GR64BitRegClass;
3285 uint64_t This1Reg = MRI.createVirtualRegister(RC);
3286 uint64_t This2Reg = MRI.createVirtualRegister(RC);
3287 uint64_t End2Reg = MRI.createVirtualRegister(RC);
3289 MachineBasicBlock *StartMBB = MBB;
3290 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
3291 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
3294 // # fall through to LoopMMB
3295 MBB->addSuccessor(LoopMBB);
3298 // %This1Reg = phi [ %Start1Reg, StartMBB ], [ %End1Reg, LoopMBB ]
3299 // %This2Reg = phi [ %Start2Reg, StartMBB ], [ %End2Reg, LoopMBB ]
3301 // %End1Reg, %End2Reg = CLST %This1Reg, %This2Reg -- uses R0L
3303 // # fall through to DoneMMB
3305 // The load of R0L can be hoisted by post-RA LICM.
3308 BuildMI(MBB, DL, TII->get(SystemZ::PHI), This1Reg)
3309 .addReg(Start1Reg).addMBB(StartMBB)
3310 .addReg(End1Reg).addMBB(LoopMBB);
3311 BuildMI(MBB, DL, TII->get(SystemZ::PHI), This2Reg)
3312 .addReg(Start2Reg).addMBB(StartMBB)
3313 .addReg(End2Reg).addMBB(LoopMBB);
3314 BuildMI(MBB, DL, TII->get(TargetOpcode::COPY), SystemZ::R0L).addReg(CharReg);
3315 BuildMI(MBB, DL, TII->get(Opcode))
3316 .addReg(End1Reg, RegState::Define).addReg(End2Reg, RegState::Define)
3317 .addReg(This1Reg).addReg(This2Reg);
3318 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
3319 .addImm(SystemZ::CCMASK_ANY).addImm(SystemZ::CCMASK_3).addMBB(LoopMBB);
3320 MBB->addSuccessor(LoopMBB);
3321 MBB->addSuccessor(DoneMBB);
3323 DoneMBB->addLiveIn(SystemZ::CC);
3325 MI->eraseFromParent();
3329 MachineBasicBlock *SystemZTargetLowering::
3330 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const {
3331 switch (MI->getOpcode()) {
3332 case SystemZ::Select32Mux:
3333 case SystemZ::Select32:
3334 case SystemZ::SelectF32:
3335 case SystemZ::Select64:
3336 case SystemZ::SelectF64:
3337 case SystemZ::SelectF128:
3338 return emitSelect(MI, MBB);
3340 case SystemZ::CondStore8Mux:
3341 return emitCondStore(MI, MBB, SystemZ::STCMux, 0, false);
3342 case SystemZ::CondStore8MuxInv:
3343 return emitCondStore(MI, MBB, SystemZ::STCMux, 0, true);
3344 case SystemZ::CondStore16Mux:
3345 return emitCondStore(MI, MBB, SystemZ::STHMux, 0, false);
3346 case SystemZ::CondStore16MuxInv:
3347 return emitCondStore(MI, MBB, SystemZ::STHMux, 0, true);
3348 case SystemZ::CondStore8:
3349 return emitCondStore(MI, MBB, SystemZ::STC, 0, false);
3350 case SystemZ::CondStore8Inv:
3351 return emitCondStore(MI, MBB, SystemZ::STC, 0, true);
3352 case SystemZ::CondStore16:
3353 return emitCondStore(MI, MBB, SystemZ::STH, 0, false);
3354 case SystemZ::CondStore16Inv:
3355 return emitCondStore(MI, MBB, SystemZ::STH, 0, true);
3356 case SystemZ::CondStore32:
3357 return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, false);
3358 case SystemZ::CondStore32Inv:
3359 return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, true);
3360 case SystemZ::CondStore64:
3361 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, false);
3362 case SystemZ::CondStore64Inv:
3363 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, true);
3364 case SystemZ::CondStoreF32:
3365 return emitCondStore(MI, MBB, SystemZ::STE, 0, false);
3366 case SystemZ::CondStoreF32Inv:
3367 return emitCondStore(MI, MBB, SystemZ::STE, 0, true);
3368 case SystemZ::CondStoreF64:
3369 return emitCondStore(MI, MBB, SystemZ::STD, 0, false);
3370 case SystemZ::CondStoreF64Inv:
3371 return emitCondStore(MI, MBB, SystemZ::STD, 0, true);
3373 case SystemZ::AEXT128_64:
3374 return emitExt128(MI, MBB, false, SystemZ::subreg_l64);
3375 case SystemZ::ZEXT128_32:
3376 return emitExt128(MI, MBB, true, SystemZ::subreg_l32);
3377 case SystemZ::ZEXT128_64:
3378 return emitExt128(MI, MBB, true, SystemZ::subreg_l64);
3380 case SystemZ::ATOMIC_SWAPW:
3381 return emitAtomicLoadBinary(MI, MBB, 0, 0);
3382 case SystemZ::ATOMIC_SWAP_32:
3383 return emitAtomicLoadBinary(MI, MBB, 0, 32);
3384 case SystemZ::ATOMIC_SWAP_64:
3385 return emitAtomicLoadBinary(MI, MBB, 0, 64);
3387 case SystemZ::ATOMIC_LOADW_AR:
3388 return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 0);
3389 case SystemZ::ATOMIC_LOADW_AFI:
3390 return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 0);
3391 case SystemZ::ATOMIC_LOAD_AR:
3392 return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 32);
3393 case SystemZ::ATOMIC_LOAD_AHI:
3394 return emitAtomicLoadBinary(MI, MBB, SystemZ::AHI, 32);
3395 case SystemZ::ATOMIC_LOAD_AFI:
3396 return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 32);
3397 case SystemZ::ATOMIC_LOAD_AGR:
3398 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGR, 64);
3399 case SystemZ::ATOMIC_LOAD_AGHI:
3400 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGHI, 64);
3401 case SystemZ::ATOMIC_LOAD_AGFI:
3402 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGFI, 64);
3404 case SystemZ::ATOMIC_LOADW_SR:
3405 return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 0);
3406 case SystemZ::ATOMIC_LOAD_SR:
3407 return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 32);
3408 case SystemZ::ATOMIC_LOAD_SGR:
3409 return emitAtomicLoadBinary(MI, MBB, SystemZ::SGR, 64);
3411 case SystemZ::ATOMIC_LOADW_NR:
3412 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0);
3413 case SystemZ::ATOMIC_LOADW_NILH:
3414 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 0);
3415 case SystemZ::ATOMIC_LOAD_NR:
3416 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32);
3417 case SystemZ::ATOMIC_LOAD_NILL:
3418 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 32);
3419 case SystemZ::ATOMIC_LOAD_NILH:
3420 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 32);
3421 case SystemZ::ATOMIC_LOAD_NILF:
3422 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 32);
3423 case SystemZ::ATOMIC_LOAD_NGR:
3424 return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64);
3425 case SystemZ::ATOMIC_LOAD_NILL64:
3426 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL64, 64);
3427 case SystemZ::ATOMIC_LOAD_NILH64:
3428 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH64, 64);
3429 case SystemZ::ATOMIC_LOAD_NIHL64:
3430 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL64, 64);
3431 case SystemZ::ATOMIC_LOAD_NIHH64:
3432 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH64, 64);
3433 case SystemZ::ATOMIC_LOAD_NILF64:
3434 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF64, 64);
3435 case SystemZ::ATOMIC_LOAD_NIHF64:
3436 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF64, 64);
3438 case SystemZ::ATOMIC_LOADW_OR:
3439 return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 0);
3440 case SystemZ::ATOMIC_LOADW_OILH:
3441 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 0);
3442 case SystemZ::ATOMIC_LOAD_OR:
3443 return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 32);
3444 case SystemZ::ATOMIC_LOAD_OILL:
3445 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL, 32);
3446 case SystemZ::ATOMIC_LOAD_OILH:
3447 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 32);
3448 case SystemZ::ATOMIC_LOAD_OILF:
3449 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF, 32);
3450 case SystemZ::ATOMIC_LOAD_OGR:
3451 return emitAtomicLoadBinary(MI, MBB, SystemZ::OGR, 64);
3452 case SystemZ::ATOMIC_LOAD_OILL64:
3453 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL64, 64);
3454 case SystemZ::ATOMIC_LOAD_OILH64:
3455 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH64, 64);
3456 case SystemZ::ATOMIC_LOAD_OIHL64:
3457 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHL64, 64);
3458 case SystemZ::ATOMIC_LOAD_OIHH64:
3459 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHH64, 64);
3460 case SystemZ::ATOMIC_LOAD_OILF64:
3461 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF64, 64);
3462 case SystemZ::ATOMIC_LOAD_OIHF64:
3463 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHF64, 64);
3465 case SystemZ::ATOMIC_LOADW_XR:
3466 return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 0);
3467 case SystemZ::ATOMIC_LOADW_XILF:
3468 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 0);
3469 case SystemZ::ATOMIC_LOAD_XR:
3470 return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 32);
3471 case SystemZ::ATOMIC_LOAD_XILF:
3472 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 32);
3473 case SystemZ::ATOMIC_LOAD_XGR:
3474 return emitAtomicLoadBinary(MI, MBB, SystemZ::XGR, 64);
3475 case SystemZ::ATOMIC_LOAD_XILF64:
3476 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF64, 64);
3477 case SystemZ::ATOMIC_LOAD_XIHF64:
3478 return emitAtomicLoadBinary(MI, MBB, SystemZ::XIHF64, 64);
3480 case SystemZ::ATOMIC_LOADW_NRi:
3481 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0, true);
3482 case SystemZ::ATOMIC_LOADW_NILHi:
3483 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 0, true);
3484 case SystemZ::ATOMIC_LOAD_NRi:
3485 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32, true);
3486 case SystemZ::ATOMIC_LOAD_NILLi:
3487 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 32, true);
3488 case SystemZ::ATOMIC_LOAD_NILHi:
3489 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 32, true);
3490 case SystemZ::ATOMIC_LOAD_NILFi:
3491 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 32, true);
3492 case SystemZ::ATOMIC_LOAD_NGRi:
3493 return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64, true);
3494 case SystemZ::ATOMIC_LOAD_NILL64i:
3495 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL64, 64, true);
3496 case SystemZ::ATOMIC_LOAD_NILH64i:
3497 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH64, 64, true);
3498 case SystemZ::ATOMIC_LOAD_NIHL64i:
3499 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL64, 64, true);
3500 case SystemZ::ATOMIC_LOAD_NIHH64i:
3501 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH64, 64, true);
3502 case SystemZ::ATOMIC_LOAD_NILF64i:
3503 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF64, 64, true);
3504 case SystemZ::ATOMIC_LOAD_NIHF64i:
3505 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF64, 64, true);
3507 case SystemZ::ATOMIC_LOADW_MIN:
3508 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
3509 SystemZ::CCMASK_CMP_LE, 0);
3510 case SystemZ::ATOMIC_LOAD_MIN_32:
3511 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
3512 SystemZ::CCMASK_CMP_LE, 32);
3513 case SystemZ::ATOMIC_LOAD_MIN_64:
3514 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
3515 SystemZ::CCMASK_CMP_LE, 64);
3517 case SystemZ::ATOMIC_LOADW_MAX:
3518 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
3519 SystemZ::CCMASK_CMP_GE, 0);
3520 case SystemZ::ATOMIC_LOAD_MAX_32:
3521 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
3522 SystemZ::CCMASK_CMP_GE, 32);
3523 case SystemZ::ATOMIC_LOAD_MAX_64:
3524 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
3525 SystemZ::CCMASK_CMP_GE, 64);
3527 case SystemZ::ATOMIC_LOADW_UMIN:
3528 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
3529 SystemZ::CCMASK_CMP_LE, 0);
3530 case SystemZ::ATOMIC_LOAD_UMIN_32:
3531 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
3532 SystemZ::CCMASK_CMP_LE, 32);
3533 case SystemZ::ATOMIC_LOAD_UMIN_64:
3534 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
3535 SystemZ::CCMASK_CMP_LE, 64);
3537 case SystemZ::ATOMIC_LOADW_UMAX:
3538 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
3539 SystemZ::CCMASK_CMP_GE, 0);
3540 case SystemZ::ATOMIC_LOAD_UMAX_32:
3541 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
3542 SystemZ::CCMASK_CMP_GE, 32);
3543 case SystemZ::ATOMIC_LOAD_UMAX_64:
3544 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
3545 SystemZ::CCMASK_CMP_GE, 64);
3547 case SystemZ::ATOMIC_CMP_SWAPW:
3548 return emitAtomicCmpSwapW(MI, MBB);
3549 case SystemZ::MVCSequence:
3550 case SystemZ::MVCLoop:
3551 return emitMemMemWrapper(MI, MBB, SystemZ::MVC);
3552 case SystemZ::NCSequence:
3553 case SystemZ::NCLoop:
3554 return emitMemMemWrapper(MI, MBB, SystemZ::NC);
3555 case SystemZ::OCSequence:
3556 case SystemZ::OCLoop:
3557 return emitMemMemWrapper(MI, MBB, SystemZ::OC);
3558 case SystemZ::XCSequence:
3559 case SystemZ::XCLoop:
3560 return emitMemMemWrapper(MI, MBB, SystemZ::XC);
3561 case SystemZ::CLCSequence:
3562 case SystemZ::CLCLoop:
3563 return emitMemMemWrapper(MI, MBB, SystemZ::CLC);
3564 case SystemZ::CLSTLoop:
3565 return emitStringWrapper(MI, MBB, SystemZ::CLST);
3566 case SystemZ::MVSTLoop:
3567 return emitStringWrapper(MI, MBB, SystemZ::MVST);
3568 case SystemZ::SRSTLoop:
3569 return emitStringWrapper(MI, MBB, SystemZ::SRST);
3571 llvm_unreachable("Unexpected instr type to insert");