1 //===-- SystemZISelLowering.cpp - SystemZ DAG Lowering Implementation -----==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SystemZTargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "systemz-lower"
16 #include "SystemZISelLowering.h"
18 #include "SystemZTargetMachine.h"
19 #include "SystemZSubtarget.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/PseudoSourceValue.h"
32 #include "llvm/CodeGen/SelectionDAGISel.h"
33 #include "llvm/CodeGen/ValueTypes.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Target/TargetOptions.h"
36 #include "llvm/ADT/VectorExtras.h"
39 SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
40 TargetLowering(tm), Subtarget(*tm.getSubtargetImpl()), TM(tm) {
42 RegInfo = TM.getRegisterInfo();
44 // Set up the register classes.
45 addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass);
46 addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass);
47 addRegisterClass(MVT::v2i32,SystemZ::GR64PRegisterClass);
48 addRegisterClass(MVT::v2i64,SystemZ::GR128RegisterClass);
51 addRegisterClass(MVT::f32, SystemZ::FP32RegisterClass);
52 addRegisterClass(MVT::f64, SystemZ::FP64RegisterClass);
54 addLegalFPImmediate(APFloat(+0.0)); // lzer
55 addLegalFPImmediate(APFloat(+0.0f)); // lzdr
56 addLegalFPImmediate(APFloat(-0.0)); // lzer + lner
57 addLegalFPImmediate(APFloat(-0.0f)); // lzdr + lndr
60 // Compute derived properties from the register classes
61 computeRegisterProperties();
63 // Set shifts properties
64 setShiftAmountFlavor(Extend);
65 setShiftAmountType(MVT::i64);
67 // Provide all sorts of operation actions
68 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
69 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
70 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
72 setLoadExtAction(ISD::SEXTLOAD, MVT::f32, Expand);
73 setLoadExtAction(ISD::ZEXTLOAD, MVT::f32, Expand);
74 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
76 setLoadExtAction(ISD::SEXTLOAD, MVT::f64, Expand);
77 setLoadExtAction(ISD::ZEXTLOAD, MVT::f64, Expand);
78 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
80 setStackPointerRegisterToSaveRestore(SystemZ::R15D);
81 setSchedulingPreference(SchedulingForLatency);
82 setBooleanContents(ZeroOrOneBooleanContent);
84 setOperationAction(ISD::RET, MVT::Other, Custom);
86 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
87 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
88 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
89 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
90 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
91 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
92 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
93 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
94 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
95 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
96 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
98 setOperationAction(ISD::SDIV, MVT::i32, Expand);
99 setOperationAction(ISD::UDIV, MVT::i32, Expand);
100 setOperationAction(ISD::SDIV, MVT::i64, Expand);
101 setOperationAction(ISD::UDIV, MVT::i64, Expand);
102 setOperationAction(ISD::SREM, MVT::i32, Expand);
103 setOperationAction(ISD::UREM, MVT::i32, Expand);
104 setOperationAction(ISD::SREM, MVT::i64, Expand);
105 setOperationAction(ISD::UREM, MVT::i64, Expand);
107 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
109 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
110 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
111 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
112 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
113 setOperationAction(ISD::CTLZ, MVT::i32, Promote);
114 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
116 // FIXME: Can we lower these 2 efficiently?
117 setOperationAction(ISD::SETCC, MVT::i32, Expand);
118 setOperationAction(ISD::SETCC, MVT::i64, Expand);
119 setOperationAction(ISD::SETCC, MVT::f32, Expand);
120 setOperationAction(ISD::SETCC, MVT::f64, Expand);
121 setOperationAction(ISD::SELECT, MVT::i32, Expand);
122 setOperationAction(ISD::SELECT, MVT::i64, Expand);
123 setOperationAction(ISD::SELECT, MVT::f32, Expand);
124 setOperationAction(ISD::SELECT, MVT::f64, Expand);
125 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
126 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
127 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
128 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
130 // Funny enough: we don't have 64-bit signed versions of these stuff, but have
132 setOperationAction(ISD::MULHS, MVT::i64, Expand);
133 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
135 // Lower some FP stuff
136 setOperationAction(ISD::FSIN, MVT::f32, Expand);
137 setOperationAction(ISD::FSIN, MVT::f64, Expand);
138 setOperationAction(ISD::FCOS, MVT::f32, Expand);
139 setOperationAction(ISD::FCOS, MVT::f64, Expand);
140 setOperationAction(ISD::FREM, MVT::f32, Expand);
141 setOperationAction(ISD::FREM, MVT::f64, Expand);
143 // We have only 64-bit bitconverts
144 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
145 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
147 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
148 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
149 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
150 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
152 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
155 SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
156 switch (Op.getOpcode()) {
157 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
158 case ISD::RET: return LowerRET(Op, DAG);
159 case ISD::CALL: return LowerCALL(Op, DAG);
160 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
161 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
162 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
163 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
164 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
166 llvm_unreachable("Should not custom lower this!");
171 //===----------------------------------------------------------------------===//
172 // Calling Convention Implementation
173 //===----------------------------------------------------------------------===//
175 #include "SystemZGenCallingConv.inc"
177 SDValue SystemZTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
179 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
182 llvm_unreachable("Unsupported calling convention");
184 case CallingConv::Fast:
185 return LowerCCCArguments(Op, DAG);
189 SDValue SystemZTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
190 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
191 unsigned CallingConv = TheCall->getCallingConv();
192 switch (CallingConv) {
194 llvm_unreachable("Unsupported calling convention");
195 case CallingConv::Fast:
197 return LowerCCCCallTo(Op, DAG, CallingConv);
201 /// LowerCCCArguments - transform physical registers into virtual registers and
202 /// generate load operations for arguments places on the stack.
203 // FIXME: struct return stuff
205 SDValue SystemZTargetLowering::LowerCCCArguments(SDValue Op,
207 MachineFunction &MF = DAG.getMachineFunction();
208 MachineFrameInfo *MFI = MF.getFrameInfo();
209 MachineRegisterInfo &RegInfo = MF.getRegInfo();
210 SDValue Root = Op.getOperand(0);
211 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
212 unsigned CC = MF.getFunction()->getCallingConv();
213 DebugLoc dl = Op.getDebugLoc();
215 // Assign locations to all of the incoming arguments.
216 SmallVector<CCValAssign, 16> ArgLocs;
217 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, DAG.getContext());
218 CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_SystemZ);
221 llvm_report_error("Varargs not supported yet");
223 SmallVector<SDValue, 16> ArgValues;
224 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
226 CCValAssign &VA = ArgLocs[i];
227 MVT LocVT = VA.getLocVT();
229 // Arguments passed in registers
230 TargetRegisterClass *RC;
231 switch (LocVT.getSimpleVT()) {
234 cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
235 << LocVT.getSimpleVT()
240 RC = SystemZ::GR64RegisterClass;
243 RC = SystemZ::FP32RegisterClass;
246 RC = SystemZ::FP64RegisterClass;
250 unsigned VReg = RegInfo.createVirtualRegister(RC);
251 RegInfo.addLiveIn(VA.getLocReg(), VReg);
252 ArgValue = DAG.getCopyFromReg(Root, dl, VReg, LocVT);
255 assert(VA.isMemLoc());
257 // Create the nodes corresponding to a load from this parameter slot.
258 // Create the frame index object for this incoming parameter...
259 int FI = MFI->CreateFixedObject(LocVT.getSizeInBits()/8,
260 VA.getLocMemOffset());
262 // Create the SelectionDAG nodes corresponding to a load
263 // from this parameter
264 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
265 ArgValue = DAG.getLoad(LocVT, dl, Root, FIN,
266 PseudoSourceValue::getFixedStack(FI), 0);
269 // If this is an 8/16/32-bit value, it is really passed promoted to 64
270 // bits. Insert an assert[sz]ext to capture this, then truncate to the
272 if (VA.getLocInfo() == CCValAssign::SExt)
273 ArgValue = DAG.getNode(ISD::AssertSext, dl, LocVT, ArgValue,
274 DAG.getValueType(VA.getValVT()));
275 else if (VA.getLocInfo() == CCValAssign::ZExt)
276 ArgValue = DAG.getNode(ISD::AssertZext, dl, LocVT, ArgValue,
277 DAG.getValueType(VA.getValVT()));
279 if (VA.getLocInfo() != CCValAssign::Full)
280 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
282 ArgValues.push_back(ArgValue);
285 ArgValues.push_back(Root);
287 // Return the new list of results.
288 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
289 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
292 /// LowerCCCCallTo - functions arguments are copied from virtual regs to
293 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
295 SDValue SystemZTargetLowering::LowerCCCCallTo(SDValue Op, SelectionDAG &DAG,
297 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
298 SDValue Chain = TheCall->getChain();
299 SDValue Callee = TheCall->getCallee();
300 bool isVarArg = TheCall->isVarArg();
301 DebugLoc dl = Op.getDebugLoc();
302 MachineFunction &MF = DAG.getMachineFunction();
304 // Offset to first argument stack slot.
305 const unsigned FirstArgOffset = 160;
307 // Analyze operands of the call, assigning locations to each operand.
308 SmallVector<CCValAssign, 16> ArgLocs;
309 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, DAG.getContext());
311 CCInfo.AnalyzeCallOperands(TheCall, CC_SystemZ);
313 // Get a count of how many bytes are to be pushed on the stack.
314 unsigned NumBytes = CCInfo.getNextStackOffset();
316 Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
317 getPointerTy(), true));
319 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
320 SmallVector<SDValue, 12> MemOpChains;
323 // Walk the register/memloc assignments, inserting copies/loads.
324 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
325 CCValAssign &VA = ArgLocs[i];
327 // Arguments start after the 5 first operands of ISD::CALL
328 SDValue Arg = TheCall->getArg(i);
330 // Promote the value if needed.
331 switch (VA.getLocInfo()) {
332 default: assert(0 && "Unknown loc info!");
333 case CCValAssign::Full: break;
334 case CCValAssign::SExt:
335 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
337 case CCValAssign::ZExt:
338 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
340 case CCValAssign::AExt:
341 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
345 // Arguments that can be passed on register must be kept at RegsToPass
348 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
350 assert(VA.isMemLoc());
352 if (StackPtr.getNode() == 0)
354 DAG.getCopyFromReg(Chain, dl,
355 (RegInfo->hasFP(MF) ?
356 SystemZ::R11D : SystemZ::R15D),
359 unsigned Offset = FirstArgOffset + VA.getLocMemOffset();
360 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
362 DAG.getIntPtrConstant(Offset));
364 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
365 PseudoSourceValue::getStack(), Offset));
369 // Transform all store nodes into one single node because all store nodes are
370 // independent of each other.
371 if (!MemOpChains.empty())
372 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
373 &MemOpChains[0], MemOpChains.size());
375 // Build a sequence of copy-to-reg nodes chained together with token chain and
376 // flag operands which copy the outgoing args into registers. The InFlag in
377 // necessary since all emited instructions must be stuck together.
379 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
380 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
381 RegsToPass[i].second, InFlag);
382 InFlag = Chain.getValue(1);
385 // If the callee is a GlobalAddress node (quite common, every direct call is)
386 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
387 // Likewise ExternalSymbol -> TargetExternalSymbol.
388 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
389 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
390 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
391 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy());
393 // Returns a chain & a flag for retval copy to use.
394 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
395 SmallVector<SDValue, 8> Ops;
396 Ops.push_back(Chain);
397 Ops.push_back(Callee);
399 // Add argument registers to the end of the list so that they are
400 // known live into the call.
401 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
402 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
403 RegsToPass[i].second.getValueType()));
405 if (InFlag.getNode())
406 Ops.push_back(InFlag);
408 Chain = DAG.getNode(SystemZISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
409 InFlag = Chain.getValue(1);
411 // Create the CALLSEQ_END node.
412 Chain = DAG.getCALLSEQ_END(Chain,
413 DAG.getConstant(NumBytes, getPointerTy(), true),
414 DAG.getConstant(0, getPointerTy(), true),
416 InFlag = Chain.getValue(1);
418 // Handle result values, copying them out of physregs into vregs that we
420 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
424 /// LowerCallResult - Lower the result values of an ISD::CALL into the
425 /// appropriate copies out of appropriate physical registers. This assumes that
426 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
427 /// being lowered. Returns a SDNode with the same number of values as the
430 SystemZTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
432 unsigned CallingConv,
434 bool isVarArg = TheCall->isVarArg();
435 DebugLoc dl = TheCall->getDebugLoc();
437 // Assign locations to each value returned by this call.
438 SmallVector<CCValAssign, 16> RVLocs;
439 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs,
442 CCInfo.AnalyzeCallResult(TheCall, RetCC_SystemZ);
443 SmallVector<SDValue, 8> ResultVals;
445 // Copy all of the result registers out of their specified physreg.
446 for (unsigned i = 0; i != RVLocs.size(); ++i) {
447 CCValAssign &VA = RVLocs[i];
449 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
450 VA.getLocVT(), InFlag).getValue(1);
451 SDValue RetValue = Chain.getValue(0);
452 InFlag = Chain.getValue(2);
454 // If this is an 8/16/32-bit value, it is really passed promoted to 64
455 // bits. Insert an assert[sz]ext to capture this, then truncate to the
457 if (VA.getLocInfo() == CCValAssign::SExt)
458 RetValue = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), RetValue,
459 DAG.getValueType(VA.getValVT()));
460 else if (VA.getLocInfo() == CCValAssign::ZExt)
461 RetValue = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), RetValue,
462 DAG.getValueType(VA.getValVT()));
464 if (VA.getLocInfo() != CCValAssign::Full)
465 RetValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), RetValue);
467 ResultVals.push_back(RetValue);
470 ResultVals.push_back(Chain);
472 // Merge everything together with a MERGE_VALUES node.
473 return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
474 &ResultVals[0], ResultVals.size()).getNode();
478 SDValue SystemZTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
479 // CCValAssign - represent the assignment of the return value to a location
480 SmallVector<CCValAssign, 16> RVLocs;
481 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
482 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
483 DebugLoc dl = Op.getDebugLoc();
485 // CCState - Info about the registers and stack slot.
486 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs, DAG.getContext());
488 // Analize return values of ISD::RET
489 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_SystemZ);
491 // If this is the first return lowered for this function, add the regs to the
492 // liveout set for the function.
493 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
494 for (unsigned i = 0; i != RVLocs.size(); ++i)
495 if (RVLocs[i].isRegLoc())
496 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
499 // The chain is always operand #0
500 SDValue Chain = Op.getOperand(0);
503 // Copy the result values into the output registers.
504 for (unsigned i = 0; i != RVLocs.size(); ++i) {
505 CCValAssign &VA = RVLocs[i];
506 SDValue ResValue = Op.getOperand(i*2+1);
507 assert(VA.isRegLoc() && "Can only return in registers!");
509 // If this is an 8/16/32-bit value, it is really should be passed promoted
511 if (VA.getLocInfo() == CCValAssign::SExt)
512 ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue);
513 else if (VA.getLocInfo() == CCValAssign::ZExt)
514 ResValue = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ResValue);
515 else if (VA.getLocInfo() == CCValAssign::AExt)
516 ResValue = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ResValue);
518 // ISD::RET => ret chain, (regnum1,val1), ...
519 // So i*2+1 index only the regnums
520 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ResValue, Flag);
522 // Guarantee that all emitted copies are stuck together,
523 // avoiding something bad.
524 Flag = Chain.getValue(1);
528 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
531 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain);
534 SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS,
535 ISD::CondCode CC, SDValue &SystemZCC,
537 // FIXME: Emit a test if RHS is zero
539 bool isUnsigned = false;
540 SystemZCC::CondCodes TCC;
543 llvm_unreachable("Invalid integer condition!");
549 TCC = SystemZCC::NLH;
565 if (LHS.getValueType().isFloatingPoint()) {
569 isUnsigned = true; // FALLTHROUGH
575 if (LHS.getValueType().isFloatingPoint()) {
579 isUnsigned = true; // FALLTHROUGH
585 if (LHS.getValueType().isFloatingPoint()) {
586 TCC = SystemZCC::NLE;
589 isUnsigned = true; // FALLTHROUGH
595 if (LHS.getValueType().isFloatingPoint()) {
596 TCC = SystemZCC::NHE;
599 isUnsigned = true; // FALLTHROUGH
606 SystemZCC = DAG.getConstant(TCC, MVT::i32);
608 DebugLoc dl = LHS.getDebugLoc();
609 return DAG.getNode((isUnsigned ? SystemZISD::UCMP : SystemZISD::CMP),
610 dl, MVT::Flag, LHS, RHS);
614 SDValue SystemZTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
615 SDValue Chain = Op.getOperand(0);
616 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
617 SDValue LHS = Op.getOperand(2);
618 SDValue RHS = Op.getOperand(3);
619 SDValue Dest = Op.getOperand(4);
620 DebugLoc dl = Op.getDebugLoc();
623 SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG);
624 return DAG.getNode(SystemZISD::BRCOND, dl, Op.getValueType(),
625 Chain, Dest, SystemZCC, Flag);
628 SDValue SystemZTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
629 SDValue LHS = Op.getOperand(0);
630 SDValue RHS = Op.getOperand(1);
631 SDValue TrueV = Op.getOperand(2);
632 SDValue FalseV = Op.getOperand(3);
633 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
634 DebugLoc dl = Op.getDebugLoc();
637 SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG);
639 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
640 SmallVector<SDValue, 4> Ops;
641 Ops.push_back(TrueV);
642 Ops.push_back(FalseV);
643 Ops.push_back(SystemZCC);
646 return DAG.getNode(SystemZISD::SELECT, dl, VTs, &Ops[0], Ops.size());
649 SDValue SystemZTargetLowering::LowerGlobalAddress(SDValue Op,
651 DebugLoc dl = Op.getDebugLoc();
652 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
653 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
655 bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_;
656 bool ExtraLoadRequired =
657 Subtarget.GVRequiresExtraLoad(GV, getTargetMachine(), false);
660 if (!IsPic && !ExtraLoadRequired) {
661 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
664 unsigned char OpFlags = 0;
665 if (ExtraLoadRequired)
666 OpFlags = SystemZII::MO_GOTENT;
668 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
671 Result = DAG.getNode(SystemZISD::PCRelativeWrapper, dl,
672 getPointerTy(), Result);
674 if (ExtraLoadRequired)
675 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
676 PseudoSourceValue::getGOT(), 0);
678 // If there was a non-zero offset that we didn't fold, create an explicit
681 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
682 DAG.getConstant(Offset, getPointerTy()));
688 SDValue SystemZTargetLowering::LowerJumpTable(SDValue Op,
690 DebugLoc dl = Op.getDebugLoc();
691 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
692 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
694 return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result);
699 // FIXME: This is just dirty hack. We need to lower cpool properly
700 SDValue SystemZTargetLowering::LowerConstantPool(SDValue Op,
702 DebugLoc dl = Op.getDebugLoc();
703 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
705 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
709 return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result);
712 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
714 case SystemZISD::RET_FLAG: return "SystemZISD::RET_FLAG";
715 case SystemZISD::CALL: return "SystemZISD::CALL";
716 case SystemZISD::BRCOND: return "SystemZISD::BRCOND";
717 case SystemZISD::CMP: return "SystemZISD::CMP";
718 case SystemZISD::UCMP: return "SystemZISD::UCMP";
719 case SystemZISD::SELECT: return "SystemZISD::SELECT";
720 case SystemZISD::PCRelativeWrapper: return "SystemZISD::PCRelativeWrapper";
721 default: return NULL;
725 //===----------------------------------------------------------------------===//
726 // Other Lowering Code
727 //===----------------------------------------------------------------------===//
730 SystemZTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
731 MachineBasicBlock *BB) const {
732 const SystemZInstrInfo &TII = *TM.getInstrInfo();
733 DebugLoc dl = MI->getDebugLoc();
734 assert((MI->getOpcode() == SystemZ::Select32 ||
735 MI->getOpcode() == SystemZ::SelectF32 ||
736 MI->getOpcode() == SystemZ::Select64 ||
737 MI->getOpcode() == SystemZ::SelectF64) &&
738 "Unexpected instr type to insert");
740 // To "insert" a SELECT instruction, we actually have to insert the diamond
741 // control-flow pattern. The incoming instruction knows the destination vreg
742 // to set, the condition code register to branch on, the true/false values to
743 // select between, and a branch opcode to use.
744 const BasicBlock *LLVM_BB = BB->getBasicBlock();
745 MachineFunction::iterator I = BB;
753 // fallthrough --> copy0MBB
754 MachineBasicBlock *thisMBB = BB;
755 MachineFunction *F = BB->getParent();
756 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
757 MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
758 SystemZCC::CondCodes CC = (SystemZCC::CondCodes)MI->getOperand(3).getImm();
759 BuildMI(BB, dl, TII.getBrCond(CC)).addMBB(copy1MBB);
760 F->insert(I, copy0MBB);
761 F->insert(I, copy1MBB);
762 // Update machine-CFG edges by transferring all successors of the current
763 // block to the new block which will contain the Phi node for the select.
764 copy1MBB->transferSuccessors(BB);
765 // Next, add the true and fallthrough blocks as its successors.
766 BB->addSuccessor(copy0MBB);
767 BB->addSuccessor(copy1MBB);
771 // # fallthrough to copy1MBB
774 // Update machine-CFG edges
775 BB->addSuccessor(copy1MBB);
778 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
781 BuildMI(BB, dl, TII.get(SystemZ::PHI),
782 MI->getOperand(0).getReg())
783 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
784 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
786 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.