1 //===-- SystemZISelLowering.cpp - SystemZ DAG Lowering Implementation -----==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SystemZTargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "systemz-lower"
16 #include "SystemZISelLowering.h"
18 #include "SystemZTargetMachine.h"
19 #include "SystemZSubtarget.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/PseudoSourceValue.h"
32 #include "llvm/CodeGen/SelectionDAGISel.h"
33 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
34 #include "llvm/CodeGen/ValueTypes.h"
35 #include "llvm/Target/TargetOptions.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/ADT/VectorExtras.h"
42 SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
43 TargetLowering(tm, new TargetLoweringObjectFileELF()),
44 Subtarget(*tm.getSubtargetImpl()), TM(tm) {
46 RegInfo = TM.getRegisterInfo();
48 // Set up the register classes.
49 addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass);
50 addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass);
51 addRegisterClass(MVT::v2i32,SystemZ::GR64PRegisterClass);
52 addRegisterClass(MVT::v2i64,SystemZ::GR128RegisterClass);
55 addRegisterClass(MVT::f32, SystemZ::FP32RegisterClass);
56 addRegisterClass(MVT::f64, SystemZ::FP64RegisterClass);
59 // Compute derived properties from the register classes
60 computeRegisterProperties();
62 // Set shifts properties
63 setShiftAmountType(MVT::i64);
65 // Provide all sorts of operation actions
66 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
67 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
68 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
70 setLoadExtAction(ISD::SEXTLOAD, MVT::f32, Expand);
71 setLoadExtAction(ISD::ZEXTLOAD, MVT::f32, Expand);
72 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
74 setLoadExtAction(ISD::SEXTLOAD, MVT::f64, Expand);
75 setLoadExtAction(ISD::ZEXTLOAD, MVT::f64, Expand);
76 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
78 setStackPointerRegisterToSaveRestore(SystemZ::R15D);
80 // TODO: It may be better to default to latency-oriented scheduling, however
81 // LLVM's current latency-oriented scheduler can't handle physreg definitions
82 // such as SystemZ has with PSW, so set this to the register-pressure
83 // scheduler, because it can.
84 setSchedulingPreference(SchedulingForRegPressure);
86 setBooleanContents(ZeroOrOneBooleanContent);
88 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
89 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
90 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
91 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
92 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
93 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
94 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
95 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
96 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
97 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
98 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
100 setOperationAction(ISD::SDIV, MVT::i32, Expand);
101 setOperationAction(ISD::UDIV, MVT::i32, Expand);
102 setOperationAction(ISD::SDIV, MVT::i64, Expand);
103 setOperationAction(ISD::UDIV, MVT::i64, Expand);
104 setOperationAction(ISD::SREM, MVT::i32, Expand);
105 setOperationAction(ISD::UREM, MVT::i32, Expand);
106 setOperationAction(ISD::SREM, MVT::i64, Expand);
107 setOperationAction(ISD::UREM, MVT::i64, Expand);
109 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
111 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
112 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
113 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
114 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
115 setOperationAction(ISD::CTLZ, MVT::i32, Promote);
116 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
118 // FIXME: Can we lower these 2 efficiently?
119 setOperationAction(ISD::SETCC, MVT::i32, Expand);
120 setOperationAction(ISD::SETCC, MVT::i64, Expand);
121 setOperationAction(ISD::SETCC, MVT::f32, Expand);
122 setOperationAction(ISD::SETCC, MVT::f64, Expand);
123 setOperationAction(ISD::SELECT, MVT::i32, Expand);
124 setOperationAction(ISD::SELECT, MVT::i64, Expand);
125 setOperationAction(ISD::SELECT, MVT::f32, Expand);
126 setOperationAction(ISD::SELECT, MVT::f64, Expand);
127 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
128 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
129 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
130 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
132 setOperationAction(ISD::MULHS, MVT::i64, Expand);
133 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
135 // FIXME: Can we support these natively?
136 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
137 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
138 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
139 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
141 // Lower some FP stuff
142 setOperationAction(ISD::FSIN, MVT::f32, Expand);
143 setOperationAction(ISD::FSIN, MVT::f64, Expand);
144 setOperationAction(ISD::FCOS, MVT::f32, Expand);
145 setOperationAction(ISD::FCOS, MVT::f64, Expand);
146 setOperationAction(ISD::FREM, MVT::f32, Expand);
147 setOperationAction(ISD::FREM, MVT::f64, Expand);
149 // We have only 64-bit bitconverts
150 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
151 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
153 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
154 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
155 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
156 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
158 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
161 SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
162 SelectionDAG &DAG) const {
163 switch (Op.getOpcode()) {
164 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
165 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
166 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
167 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
168 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
170 llvm_unreachable("Should not custom lower this!");
175 bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
176 if (UseSoftFloat || (VT != MVT::f32 && VT != MVT::f64))
183 return Imm.isZero() || Imm.isNegZero();
186 //===----------------------------------------------------------------------===//
187 // SystemZ Inline Assembly Support
188 //===----------------------------------------------------------------------===//
190 /// getConstraintType - Given a constraint letter, return the type of
191 /// constraint it is for this target.
192 TargetLowering::ConstraintType
193 SystemZTargetLowering::getConstraintType(const std::string &Constraint) const {
194 if (Constraint.size() == 1) {
195 switch (Constraint[0]) {
197 return C_RegisterClass;
202 return TargetLowering::getConstraintType(Constraint);
205 std::pair<unsigned, const TargetRegisterClass*>
206 SystemZTargetLowering::
207 getRegForInlineAsmConstraint(const std::string &Constraint,
209 if (Constraint.size() == 1) {
210 // GCC Constraint Letters
211 switch (Constraint[0]) {
213 case 'r': // GENERAL_REGS
215 return std::make_pair(0U, SystemZ::GR32RegisterClass);
216 else if (VT == MVT::i128)
217 return std::make_pair(0U, SystemZ::GR128RegisterClass);
219 return std::make_pair(0U, SystemZ::GR64RegisterClass);
223 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
226 //===----------------------------------------------------------------------===//
227 // Calling Convention Implementation
228 //===----------------------------------------------------------------------===//
230 #include "SystemZGenCallingConv.inc"
233 SystemZTargetLowering::LowerFormalArguments(SDValue Chain,
234 CallingConv::ID CallConv,
236 const SmallVectorImpl<ISD::InputArg>
240 SmallVectorImpl<SDValue> &InVals)
245 llvm_unreachable("Unsupported calling convention");
247 case CallingConv::Fast:
248 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
253 SystemZTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
254 CallingConv::ID CallConv, bool isVarArg,
256 const SmallVectorImpl<ISD::OutputArg> &Outs,
257 const SmallVectorImpl<ISD::InputArg> &Ins,
258 DebugLoc dl, SelectionDAG &DAG,
259 SmallVectorImpl<SDValue> &InVals) const {
260 // SystemZ target does not yet support tail call optimization.
265 llvm_unreachable("Unsupported calling convention");
266 case CallingConv::Fast:
268 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
269 Outs, Ins, dl, DAG, InVals);
273 /// LowerCCCArguments - transform physical registers into virtual registers and
274 /// generate load operations for arguments places on the stack.
275 // FIXME: struct return stuff
278 SystemZTargetLowering::LowerCCCArguments(SDValue Chain,
279 CallingConv::ID CallConv,
281 const SmallVectorImpl<ISD::InputArg>
285 SmallVectorImpl<SDValue> &InVals)
288 MachineFunction &MF = DAG.getMachineFunction();
289 MachineFrameInfo *MFI = MF.getFrameInfo();
290 MachineRegisterInfo &RegInfo = MF.getRegInfo();
292 // Assign locations to all of the incoming arguments.
293 SmallVector<CCValAssign, 16> ArgLocs;
294 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
295 ArgLocs, *DAG.getContext());
296 CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ);
299 report_fatal_error("Varargs not supported yet");
301 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
303 CCValAssign &VA = ArgLocs[i];
304 EVT LocVT = VA.getLocVT();
306 // Arguments passed in registers
307 TargetRegisterClass *RC;
308 switch (LocVT.getSimpleVT().SimpleTy) {
311 errs() << "LowerFormalArguments Unhandled argument type: "
312 << LocVT.getSimpleVT().SimpleTy
317 RC = SystemZ::GR64RegisterClass;
320 RC = SystemZ::FP32RegisterClass;
323 RC = SystemZ::FP64RegisterClass;
327 unsigned VReg = RegInfo.createVirtualRegister(RC);
328 RegInfo.addLiveIn(VA.getLocReg(), VReg);
329 ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, LocVT);
332 assert(VA.isMemLoc());
334 // Create the nodes corresponding to a load from this parameter slot.
335 // Create the frame index object for this incoming parameter...
336 int FI = MFI->CreateFixedObject(LocVT.getSizeInBits()/8,
337 VA.getLocMemOffset(), true, false);
339 // Create the SelectionDAG nodes corresponding to a load
340 // from this parameter
341 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
342 ArgValue = DAG.getLoad(LocVT, dl, Chain, FIN,
343 PseudoSourceValue::getFixedStack(FI), 0,
347 // If this is an 8/16/32-bit value, it is really passed promoted to 64
348 // bits. Insert an assert[sz]ext to capture this, then truncate to the
350 if (VA.getLocInfo() == CCValAssign::SExt)
351 ArgValue = DAG.getNode(ISD::AssertSext, dl, LocVT, ArgValue,
352 DAG.getValueType(VA.getValVT()));
353 else if (VA.getLocInfo() == CCValAssign::ZExt)
354 ArgValue = DAG.getNode(ISD::AssertZext, dl, LocVT, ArgValue,
355 DAG.getValueType(VA.getValVT()));
357 if (VA.getLocInfo() != CCValAssign::Full)
358 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
360 InVals.push_back(ArgValue);
366 /// LowerCCCCallTo - functions arguments are copied from virtual regs to
367 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
370 SystemZTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
371 CallingConv::ID CallConv, bool isVarArg,
373 const SmallVectorImpl<ISD::OutputArg>
375 const SmallVectorImpl<ISD::InputArg> &Ins,
376 DebugLoc dl, SelectionDAG &DAG,
377 SmallVectorImpl<SDValue> &InVals) const {
379 MachineFunction &MF = DAG.getMachineFunction();
381 // Offset to first argument stack slot.
382 const unsigned FirstArgOffset = 160;
384 // Analyze operands of the call, assigning locations to each operand.
385 SmallVector<CCValAssign, 16> ArgLocs;
386 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
387 ArgLocs, *DAG.getContext());
389 CCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
391 // Get a count of how many bytes are to be pushed on the stack.
392 unsigned NumBytes = CCInfo.getNextStackOffset();
394 Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
395 getPointerTy(), true));
397 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
398 SmallVector<SDValue, 12> MemOpChains;
401 // Walk the register/memloc assignments, inserting copies/loads.
402 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
403 CCValAssign &VA = ArgLocs[i];
405 SDValue Arg = Outs[i].Val;
407 // Promote the value if needed.
408 switch (VA.getLocInfo()) {
409 default: assert(0 && "Unknown loc info!");
410 case CCValAssign::Full: break;
411 case CCValAssign::SExt:
412 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
414 case CCValAssign::ZExt:
415 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
417 case CCValAssign::AExt:
418 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
422 // Arguments that can be passed on register must be kept at RegsToPass
425 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
427 assert(VA.isMemLoc());
429 if (StackPtr.getNode() == 0)
431 DAG.getCopyFromReg(Chain, dl,
432 (RegInfo->hasFP(MF) ?
433 SystemZ::R11D : SystemZ::R15D),
436 unsigned Offset = FirstArgOffset + VA.getLocMemOffset();
437 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
439 DAG.getIntPtrConstant(Offset));
441 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
442 PseudoSourceValue::getStack(), Offset,
447 // Transform all store nodes into one single node because all store nodes are
448 // independent of each other.
449 if (!MemOpChains.empty())
450 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
451 &MemOpChains[0], MemOpChains.size());
453 // Build a sequence of copy-to-reg nodes chained together with token chain and
454 // flag operands which copy the outgoing args into registers. The InFlag in
455 // necessary since all emited instructions must be stuck together.
457 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
458 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
459 RegsToPass[i].second, InFlag);
460 InFlag = Chain.getValue(1);
463 // If the callee is a GlobalAddress node (quite common, every direct call is)
464 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
465 // Likewise ExternalSymbol -> TargetExternalSymbol.
466 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
467 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
468 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
469 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy());
471 // Returns a chain & a flag for retval copy to use.
472 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
473 SmallVector<SDValue, 8> Ops;
474 Ops.push_back(Chain);
475 Ops.push_back(Callee);
477 // Add argument registers to the end of the list so that they are
478 // known live into the call.
479 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
480 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
481 RegsToPass[i].second.getValueType()));
483 if (InFlag.getNode())
484 Ops.push_back(InFlag);
486 Chain = DAG.getNode(SystemZISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
487 InFlag = Chain.getValue(1);
489 // Create the CALLSEQ_END node.
490 Chain = DAG.getCALLSEQ_END(Chain,
491 DAG.getConstant(NumBytes, getPointerTy(), true),
492 DAG.getConstant(0, getPointerTy(), true),
494 InFlag = Chain.getValue(1);
496 // Handle result values, copying them out of physregs into vregs that we
498 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
502 /// LowerCallResult - Lower the result values of a call into the
503 /// appropriate copies out of appropriate physical registers.
506 SystemZTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
507 CallingConv::ID CallConv, bool isVarArg,
508 const SmallVectorImpl<ISD::InputArg>
510 DebugLoc dl, SelectionDAG &DAG,
511 SmallVectorImpl<SDValue> &InVals) const {
513 // Assign locations to each value returned by this call.
514 SmallVector<CCValAssign, 16> RVLocs;
515 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
518 CCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ);
520 // Copy all of the result registers out of their specified physreg.
521 for (unsigned i = 0; i != RVLocs.size(); ++i) {
522 CCValAssign &VA = RVLocs[i];
524 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
525 VA.getLocVT(), InFlag).getValue(1);
526 SDValue RetValue = Chain.getValue(0);
527 InFlag = Chain.getValue(2);
529 // If this is an 8/16/32-bit value, it is really passed promoted to 64
530 // bits. Insert an assert[sz]ext to capture this, then truncate to the
532 if (VA.getLocInfo() == CCValAssign::SExt)
533 RetValue = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), RetValue,
534 DAG.getValueType(VA.getValVT()));
535 else if (VA.getLocInfo() == CCValAssign::ZExt)
536 RetValue = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), RetValue,
537 DAG.getValueType(VA.getValVT()));
539 if (VA.getLocInfo() != CCValAssign::Full)
540 RetValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), RetValue);
542 InVals.push_back(RetValue);
550 SystemZTargetLowering::LowerReturn(SDValue Chain,
551 CallingConv::ID CallConv, bool isVarArg,
552 const SmallVectorImpl<ISD::OutputArg> &Outs,
553 DebugLoc dl, SelectionDAG &DAG) const {
555 // CCValAssign - represent the assignment of the return value to a location
556 SmallVector<CCValAssign, 16> RVLocs;
558 // CCState - Info about the registers and stack slot.
559 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
560 RVLocs, *DAG.getContext());
562 // Analize return values.
563 CCInfo.AnalyzeReturn(Outs, RetCC_SystemZ);
565 // If this is the first return lowered for this function, add the regs to the
566 // liveout set for the function.
567 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
568 for (unsigned i = 0; i != RVLocs.size(); ++i)
569 if (RVLocs[i].isRegLoc())
570 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
575 // Copy the result values into the output registers.
576 for (unsigned i = 0; i != RVLocs.size(); ++i) {
577 CCValAssign &VA = RVLocs[i];
578 SDValue ResValue = Outs[i].Val;
579 assert(VA.isRegLoc() && "Can only return in registers!");
581 // If this is an 8/16/32-bit value, it is really should be passed promoted
583 if (VA.getLocInfo() == CCValAssign::SExt)
584 ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue);
585 else if (VA.getLocInfo() == CCValAssign::ZExt)
586 ResValue = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ResValue);
587 else if (VA.getLocInfo() == CCValAssign::AExt)
588 ResValue = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ResValue);
590 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ResValue, Flag);
592 // Guarantee that all emitted copies are stuck together,
593 // avoiding something bad.
594 Flag = Chain.getValue(1);
598 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
601 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain);
604 SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS,
605 ISD::CondCode CC, SDValue &SystemZCC,
606 SelectionDAG &DAG) const {
607 // FIXME: Emit a test if RHS is zero
609 bool isUnsigned = false;
610 SystemZCC::CondCodes TCC;
613 llvm_unreachable("Invalid integer condition!");
619 TCC = SystemZCC::NLH;
635 if (LHS.getValueType().isFloatingPoint()) {
639 isUnsigned = true; // FALLTHROUGH
645 if (LHS.getValueType().isFloatingPoint()) {
649 isUnsigned = true; // FALLTHROUGH
655 if (LHS.getValueType().isFloatingPoint()) {
656 TCC = SystemZCC::NLE;
659 isUnsigned = true; // FALLTHROUGH
665 if (LHS.getValueType().isFloatingPoint()) {
666 TCC = SystemZCC::NHE;
669 isUnsigned = true; // FALLTHROUGH
676 SystemZCC = DAG.getConstant(TCC, MVT::i32);
678 DebugLoc dl = LHS.getDebugLoc();
679 return DAG.getNode((isUnsigned ? SystemZISD::UCMP : SystemZISD::CMP),
680 dl, MVT::i64, LHS, RHS);
684 SDValue SystemZTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
685 SDValue Chain = Op.getOperand(0);
686 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
687 SDValue LHS = Op.getOperand(2);
688 SDValue RHS = Op.getOperand(3);
689 SDValue Dest = Op.getOperand(4);
690 DebugLoc dl = Op.getDebugLoc();
693 SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG);
694 return DAG.getNode(SystemZISD::BRCOND, dl, Op.getValueType(),
695 Chain, Dest, SystemZCC, Flag);
698 SDValue SystemZTargetLowering::LowerSELECT_CC(SDValue Op,
699 SelectionDAG &DAG) const {
700 SDValue LHS = Op.getOperand(0);
701 SDValue RHS = Op.getOperand(1);
702 SDValue TrueV = Op.getOperand(2);
703 SDValue FalseV = Op.getOperand(3);
704 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
705 DebugLoc dl = Op.getDebugLoc();
708 SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG);
710 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
711 SmallVector<SDValue, 4> Ops;
712 Ops.push_back(TrueV);
713 Ops.push_back(FalseV);
714 Ops.push_back(SystemZCC);
717 return DAG.getNode(SystemZISD::SELECT, dl, VTs, &Ops[0], Ops.size());
720 SDValue SystemZTargetLowering::LowerGlobalAddress(SDValue Op,
721 SelectionDAG &DAG) const {
722 DebugLoc dl = Op.getDebugLoc();
723 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
724 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
726 bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_;
727 bool ExtraLoadRequired =
728 Subtarget.GVRequiresExtraLoad(GV, getTargetMachine(), false);
731 if (!IsPic && !ExtraLoadRequired) {
732 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
735 unsigned char OpFlags = 0;
736 if (ExtraLoadRequired)
737 OpFlags = SystemZII::MO_GOTENT;
739 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
742 Result = DAG.getNode(SystemZISD::PCRelativeWrapper, dl,
743 getPointerTy(), Result);
745 if (ExtraLoadRequired)
746 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
747 PseudoSourceValue::getGOT(), 0, false, false, 0);
749 // If there was a non-zero offset that we didn't fold, create an explicit
752 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
753 DAG.getConstant(Offset, getPointerTy()));
759 SDValue SystemZTargetLowering::LowerJumpTable(SDValue Op,
760 SelectionDAG &DAG) const {
761 DebugLoc dl = Op.getDebugLoc();
762 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
763 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
765 return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result);
770 // FIXME: This is just dirty hack. We need to lower cpool properly
771 SDValue SystemZTargetLowering::LowerConstantPool(SDValue Op,
772 SelectionDAG &DAG) const {
773 DebugLoc dl = Op.getDebugLoc();
774 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
776 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
780 return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result);
783 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
785 case SystemZISD::RET_FLAG: return "SystemZISD::RET_FLAG";
786 case SystemZISD::CALL: return "SystemZISD::CALL";
787 case SystemZISD::BRCOND: return "SystemZISD::BRCOND";
788 case SystemZISD::CMP: return "SystemZISD::CMP";
789 case SystemZISD::UCMP: return "SystemZISD::UCMP";
790 case SystemZISD::SELECT: return "SystemZISD::SELECT";
791 case SystemZISD::PCRelativeWrapper: return "SystemZISD::PCRelativeWrapper";
792 default: return NULL;
796 //===----------------------------------------------------------------------===//
797 // Other Lowering Code
798 //===----------------------------------------------------------------------===//
801 SystemZTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
802 MachineBasicBlock *BB,
803 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
804 const SystemZInstrInfo &TII = *TM.getInstrInfo();
805 DebugLoc dl = MI->getDebugLoc();
806 assert((MI->getOpcode() == SystemZ::Select32 ||
807 MI->getOpcode() == SystemZ::SelectF32 ||
808 MI->getOpcode() == SystemZ::Select64 ||
809 MI->getOpcode() == SystemZ::SelectF64) &&
810 "Unexpected instr type to insert");
812 // To "insert" a SELECT instruction, we actually have to insert the diamond
813 // control-flow pattern. The incoming instruction knows the destination vreg
814 // to set, the condition code register to branch on, the true/false values to
815 // select between, and a branch opcode to use.
816 const BasicBlock *LLVM_BB = BB->getBasicBlock();
817 MachineFunction::iterator I = BB;
825 // fallthrough --> copy0MBB
826 MachineBasicBlock *thisMBB = BB;
827 MachineFunction *F = BB->getParent();
828 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
829 MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
830 SystemZCC::CondCodes CC = (SystemZCC::CondCodes)MI->getOperand(3).getImm();
831 BuildMI(BB, dl, TII.getBrCond(CC)).addMBB(copy1MBB);
832 F->insert(I, copy0MBB);
833 F->insert(I, copy1MBB);
834 // Inform sdisel of the edge changes.
835 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
836 SE = BB->succ_end(); SI != SE; ++SI)
837 EM->insert(std::make_pair(*SI, copy1MBB));
838 // Update machine-CFG edges by transferring all successors of the current
839 // block to the new block which will contain the Phi node for the select.
840 copy1MBB->transferSuccessors(BB);
841 // Next, add the true and fallthrough blocks as its successors.
842 BB->addSuccessor(copy0MBB);
843 BB->addSuccessor(copy1MBB);
847 // # fallthrough to copy1MBB
850 // Update machine-CFG edges
851 BB->addSuccessor(copy1MBB);
854 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
857 BuildMI(BB, dl, TII.get(SystemZ::PHI),
858 MI->getOperand(0).getReg())
859 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
860 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
862 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.