1 //===-- SystemZISelLowering.cpp - SystemZ DAG lowering implementation -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SystemZTargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "systemz-lower"
16 #include "SystemZISelLowering.h"
17 #include "SystemZCallingConv.h"
18 #include "SystemZConstantPoolValue.h"
19 #include "SystemZMachineFunctionInfo.h"
20 #include "SystemZTargetMachine.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 // Classify VT as either 32 or 64 bit.
29 static bool is32Bit(EVT VT) {
30 switch (VT.getSimpleVT().SimpleTy) {
36 llvm_unreachable("Unsupported type");
40 // Return a version of MachineOperand that can be safely used before the
42 static MachineOperand earlyUseOperand(MachineOperand Op) {
48 SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm)
49 : TargetLowering(tm, new TargetLoweringObjectFileELF()),
50 Subtarget(*tm.getSubtargetImpl()), TM(tm) {
51 MVT PtrVT = getPointerTy();
53 // Set up the register classes.
54 addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass);
55 addRegisterClass(MVT::i64, &SystemZ::GR64BitRegClass);
56 addRegisterClass(MVT::f32, &SystemZ::FP32BitRegClass);
57 addRegisterClass(MVT::f64, &SystemZ::FP64BitRegClass);
58 addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass);
60 // Compute derived properties from the register classes
61 computeRegisterProperties();
63 // Set up special registers.
64 setExceptionPointerRegister(SystemZ::R6D);
65 setExceptionSelectorRegister(SystemZ::R7D);
66 setStackPointerRegisterToSaveRestore(SystemZ::R15D);
68 // TODO: It may be better to default to latency-oriented scheduling, however
69 // LLVM's current latency-oriented scheduler can't handle physreg definitions
70 // such as SystemZ has with CC, so set this to the register-pressure
71 // scheduler, because it can.
72 setSchedulingPreference(Sched::RegPressure);
74 setBooleanContents(ZeroOrOneBooleanContent);
75 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
77 // Instructions are strings of 2-byte aligned 2-byte values.
78 setMinFunctionAlignment(2);
80 // Handle operations that are handled in a similar way for all types.
81 for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
82 I <= MVT::LAST_FP_VALUETYPE;
84 MVT VT = MVT::SimpleValueType(I);
85 if (isTypeLegal(VT)) {
86 // Expand SETCC(X, Y, COND) into SELECT_CC(X, Y, 1, 0, COND).
87 setOperationAction(ISD::SETCC, VT, Expand);
89 // Expand SELECT(C, A, B) into SELECT_CC(X, 0, A, B, NE).
90 setOperationAction(ISD::SELECT, VT, Expand);
92 // Lower SELECT_CC and BR_CC into separate comparisons and branches.
93 setOperationAction(ISD::SELECT_CC, VT, Custom);
94 setOperationAction(ISD::BR_CC, VT, Custom);
98 // Expand jump table branches as address arithmetic followed by an
100 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
102 // Expand BRCOND into a BR_CC (see above).
103 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
105 // Handle integer types.
106 for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
107 I <= MVT::LAST_INTEGER_VALUETYPE;
109 MVT VT = MVT::SimpleValueType(I);
110 if (isTypeLegal(VT)) {
111 // Expand individual DIV and REMs into DIVREMs.
112 setOperationAction(ISD::SDIV, VT, Expand);
113 setOperationAction(ISD::UDIV, VT, Expand);
114 setOperationAction(ISD::SREM, VT, Expand);
115 setOperationAction(ISD::UREM, VT, Expand);
116 setOperationAction(ISD::SDIVREM, VT, Custom);
117 setOperationAction(ISD::UDIVREM, VT, Custom);
119 // Expand ATOMIC_LOAD and ATOMIC_STORE using ATOMIC_CMP_SWAP.
120 // FIXME: probably much too conservative.
121 setOperationAction(ISD::ATOMIC_LOAD, VT, Expand);
122 setOperationAction(ISD::ATOMIC_STORE, VT, Expand);
124 // No special instructions for these.
125 setOperationAction(ISD::CTPOP, VT, Expand);
126 setOperationAction(ISD::CTTZ, VT, Expand);
127 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
128 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
129 setOperationAction(ISD::ROTR, VT, Expand);
131 // Use *MUL_LOHI where possible and a wider multiplication otherwise.
132 setOperationAction(ISD::MULHS, VT, Expand);
133 setOperationAction(ISD::MULHU, VT, Expand);
135 // We have instructions for signed but not unsigned FP conversion.
136 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
140 // Type legalization will convert 8- and 16-bit atomic operations into
141 // forms that operate on i32s (but still keeping the original memory VT).
142 // Lower them into full i32 operations.
143 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Custom);
144 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Custom);
145 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
146 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Custom);
147 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Custom);
148 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Custom);
149 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Custom);
150 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Custom);
151 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Custom);
152 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Custom);
153 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Custom);
154 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
156 // We have instructions for signed but not unsigned FP conversion.
157 // Handle unsigned 32-bit types as signed 64-bit types.
158 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote);
159 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
161 // We have native support for a 64-bit CTLZ, via FLOGR.
162 setOperationAction(ISD::CTLZ, MVT::i32, Promote);
163 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
165 // Give LowerOperation the chance to replace 64-bit ORs with subregs.
166 setOperationAction(ISD::OR, MVT::i64, Custom);
168 // The architecture has 32-bit SMUL_LOHI and UMUL_LOHI (MR and MLR),
169 // but they aren't really worth using. There is no 64-bit SMUL_LOHI,
170 // but there is a 64-bit UMUL_LOHI: MLGR.
171 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
172 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
173 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
174 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Custom);
176 // FIXME: Can we support these natively?
177 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
178 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
179 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
181 // We have native instructions for i8, i16 and i32 extensions, but not i1.
182 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
183 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
184 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
185 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
187 // Handle the various types of symbolic address.
188 setOperationAction(ISD::ConstantPool, PtrVT, Custom);
189 setOperationAction(ISD::GlobalAddress, PtrVT, Custom);
190 setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom);
191 setOperationAction(ISD::BlockAddress, PtrVT, Custom);
192 setOperationAction(ISD::JumpTable, PtrVT, Custom);
194 // We need to handle dynamic allocations specially because of the
195 // 160-byte area at the bottom of the stack.
196 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
198 // Use custom expanders so that we can force the function to use
200 setOperationAction(ISD::STACKSAVE, MVT::Other, Custom);
201 setOperationAction(ISD::STACKRESTORE, MVT::Other, Custom);
203 // Handle floating-point types.
204 for (unsigned I = MVT::FIRST_FP_VALUETYPE;
205 I <= MVT::LAST_FP_VALUETYPE;
207 MVT VT = MVT::SimpleValueType(I);
208 if (isTypeLegal(VT)) {
209 // We can use FI for FRINT.
210 setOperationAction(ISD::FRINT, VT, Legal);
212 // No special instructions for these.
213 setOperationAction(ISD::FSIN, VT, Expand);
214 setOperationAction(ISD::FCOS, VT, Expand);
215 setOperationAction(ISD::FREM, VT, Expand);
219 // We have fused multiply-addition for f32 and f64 but not f128.
220 setOperationAction(ISD::FMA, MVT::f32, Legal);
221 setOperationAction(ISD::FMA, MVT::f64, Legal);
222 setOperationAction(ISD::FMA, MVT::f128, Expand);
224 // Needed so that we don't try to implement f128 constant loads using
225 // a load-and-extend of a f80 constant (in cases where the constant
226 // would fit in an f80).
227 setLoadExtAction(ISD::EXTLOAD, MVT::f80, Expand);
229 // Floating-point truncation and stores need to be done separately.
230 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
231 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
232 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
234 // We have 64-bit FPR<->GPR moves, but need special handling for
236 setOperationAction(ISD::BITCAST, MVT::i32, Custom);
237 setOperationAction(ISD::BITCAST, MVT::f32, Custom);
239 // VASTART and VACOPY need to deal with the SystemZ-specific varargs
240 // structure, but VAEND is a no-op.
241 setOperationAction(ISD::VASTART, MVT::Other, Custom);
242 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
243 setOperationAction(ISD::VAEND, MVT::Other, Expand);
245 // We want to use MVC in preference to even a single load/store pair.
246 MaxStoresPerMemcpy = 0;
247 MaxStoresPerMemcpyOptSize = 0;
249 // The main memset sequence is a byte store followed by an MVC.
250 // Two STC or MV..I stores win over that, but the kind of fused stores
251 // generated by target-independent code don't when the byte value is
252 // variable. E.g. "STC <reg>;MHI <reg>,257;STH <reg>" is not better
253 // than "STC;MVC". Handle the choice in target-specific code instead.
254 MaxStoresPerMemset = 0;
255 MaxStoresPerMemsetOptSize = 0;
259 SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
260 VT = VT.getScalarType();
265 switch (VT.getSimpleVT().SimpleTy) {
278 bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
279 // We can load zero using LZ?R and negative zero using LZ?R;LC?BR.
280 return Imm.isZero() || Imm.isNegZero();
283 bool SystemZTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
285 // Unaligned accesses should never be slower than the expanded version.
286 // We check specifically for aligned accesses in the few cases where
287 // they are required.
293 bool SystemZTargetLowering::isLegalAddressingMode(const AddrMode &AM,
295 // Punt on globals for now, although they can be used in limited
296 // RELATIVE LONG cases.
300 // Require a 20-bit signed offset.
301 if (!isInt<20>(AM.BaseOffs))
304 // Indexing is OK but no scale factor can be applied.
305 return AM.Scale == 0 || AM.Scale == 1;
308 //===----------------------------------------------------------------------===//
309 // Inline asm support
310 //===----------------------------------------------------------------------===//
312 TargetLowering::ConstraintType
313 SystemZTargetLowering::getConstraintType(const std::string &Constraint) const {
314 if (Constraint.size() == 1) {
315 switch (Constraint[0]) {
316 case 'a': // Address register
317 case 'd': // Data register (equivalent to 'r')
318 case 'f': // Floating-point register
319 case 'r': // General-purpose register
320 return C_RegisterClass;
322 case 'Q': // Memory with base and unsigned 12-bit displacement
323 case 'R': // Likewise, plus an index
324 case 'S': // Memory with base and signed 20-bit displacement
325 case 'T': // Likewise, plus an index
326 case 'm': // Equivalent to 'T'.
329 case 'I': // Unsigned 8-bit constant
330 case 'J': // Unsigned 12-bit constant
331 case 'K': // Signed 16-bit constant
332 case 'L': // Signed 20-bit displacement (on all targets we support)
333 case 'M': // 0x7fffffff
340 return TargetLowering::getConstraintType(Constraint);
343 TargetLowering::ConstraintWeight SystemZTargetLowering::
344 getSingleConstraintMatchWeight(AsmOperandInfo &info,
345 const char *constraint) const {
346 ConstraintWeight weight = CW_Invalid;
347 Value *CallOperandVal = info.CallOperandVal;
348 // If we don't have a value, we can't do a match,
349 // but allow it at the lowest weight.
350 if (CallOperandVal == NULL)
352 Type *type = CallOperandVal->getType();
353 // Look at the constraint type.
354 switch (*constraint) {
356 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
359 case 'a': // Address register
360 case 'd': // Data register (equivalent to 'r')
361 case 'r': // General-purpose register
362 if (CallOperandVal->getType()->isIntegerTy())
363 weight = CW_Register;
366 case 'f': // Floating-point register
367 if (type->isFloatingPointTy())
368 weight = CW_Register;
371 case 'I': // Unsigned 8-bit constant
372 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
373 if (isUInt<8>(C->getZExtValue()))
374 weight = CW_Constant;
377 case 'J': // Unsigned 12-bit constant
378 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
379 if (isUInt<12>(C->getZExtValue()))
380 weight = CW_Constant;
383 case 'K': // Signed 16-bit constant
384 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
385 if (isInt<16>(C->getSExtValue()))
386 weight = CW_Constant;
389 case 'L': // Signed 20-bit displacement (on all targets we support)
390 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
391 if (isInt<20>(C->getSExtValue()))
392 weight = CW_Constant;
395 case 'M': // 0x7fffffff
396 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
397 if (C->getZExtValue() == 0x7fffffff)
398 weight = CW_Constant;
404 // Parse a "{tNNN}" register constraint for which the register type "t"
405 // has already been verified. MC is the class associated with "t" and
406 // Map maps 0-based register numbers to LLVM register numbers.
407 static std::pair<unsigned, const TargetRegisterClass *>
408 parseRegisterNumber(const std::string &Constraint,
409 const TargetRegisterClass *RC, const unsigned *Map) {
410 assert(*(Constraint.end()-1) == '}' && "Missing '}'");
411 if (isdigit(Constraint[2])) {
412 std::string Suffix(Constraint.data() + 2, Constraint.size() - 2);
413 unsigned Index = atoi(Suffix.c_str());
414 if (Index < 16 && Map[Index])
415 return std::make_pair(Map[Index], RC);
417 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
420 std::pair<unsigned, const TargetRegisterClass *> SystemZTargetLowering::
421 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const {
422 if (Constraint.size() == 1) {
423 // GCC Constraint Letters
424 switch (Constraint[0]) {
426 case 'd': // Data register (equivalent to 'r')
427 case 'r': // General-purpose register
429 return std::make_pair(0U, &SystemZ::GR64BitRegClass);
430 else if (VT == MVT::i128)
431 return std::make_pair(0U, &SystemZ::GR128BitRegClass);
432 return std::make_pair(0U, &SystemZ::GR32BitRegClass);
434 case 'a': // Address register
436 return std::make_pair(0U, &SystemZ::ADDR64BitRegClass);
437 else if (VT == MVT::i128)
438 return std::make_pair(0U, &SystemZ::ADDR128BitRegClass);
439 return std::make_pair(0U, &SystemZ::ADDR32BitRegClass);
441 case 'f': // Floating-point register
443 return std::make_pair(0U, &SystemZ::FP64BitRegClass);
444 else if (VT == MVT::f128)
445 return std::make_pair(0U, &SystemZ::FP128BitRegClass);
446 return std::make_pair(0U, &SystemZ::FP32BitRegClass);
449 if (Constraint[0] == '{') {
450 // We need to override the default register parsing for GPRs and FPRs
451 // because the interpretation depends on VT. The internal names of
452 // the registers are also different from the external names
453 // (F0D and F0S instead of F0, etc.).
454 if (Constraint[1] == 'r') {
456 return parseRegisterNumber(Constraint, &SystemZ::GR32BitRegClass,
457 SystemZMC::GR32Regs);
459 return parseRegisterNumber(Constraint, &SystemZ::GR128BitRegClass,
460 SystemZMC::GR128Regs);
461 return parseRegisterNumber(Constraint, &SystemZ::GR64BitRegClass,
462 SystemZMC::GR64Regs);
464 if (Constraint[1] == 'f') {
466 return parseRegisterNumber(Constraint, &SystemZ::FP32BitRegClass,
467 SystemZMC::FP32Regs);
469 return parseRegisterNumber(Constraint, &SystemZ::FP128BitRegClass,
470 SystemZMC::FP128Regs);
471 return parseRegisterNumber(Constraint, &SystemZ::FP64BitRegClass,
472 SystemZMC::FP64Regs);
475 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
478 void SystemZTargetLowering::
479 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
480 std::vector<SDValue> &Ops,
481 SelectionDAG &DAG) const {
482 // Only support length 1 constraints for now.
483 if (Constraint.length() == 1) {
484 switch (Constraint[0]) {
485 case 'I': // Unsigned 8-bit constant
486 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
487 if (isUInt<8>(C->getZExtValue()))
488 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
492 case 'J': // Unsigned 12-bit constant
493 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
494 if (isUInt<12>(C->getZExtValue()))
495 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
499 case 'K': // Signed 16-bit constant
500 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
501 if (isInt<16>(C->getSExtValue()))
502 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
506 case 'L': // Signed 20-bit displacement (on all targets we support)
507 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
508 if (isInt<20>(C->getSExtValue()))
509 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
513 case 'M': // 0x7fffffff
514 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
515 if (C->getZExtValue() == 0x7fffffff)
516 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
521 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
524 //===----------------------------------------------------------------------===//
525 // Calling conventions
526 //===----------------------------------------------------------------------===//
528 #include "SystemZGenCallingConv.inc"
530 // Value is a value that has been passed to us in the location described by VA
531 // (and so has type VA.getLocVT()). Convert Value to VA.getValVT(), chaining
532 // any loads onto Chain.
533 static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDLoc DL,
534 CCValAssign &VA, SDValue Chain,
536 // If the argument has been promoted from a smaller type, insert an
537 // assertion to capture this.
538 if (VA.getLocInfo() == CCValAssign::SExt)
539 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value,
540 DAG.getValueType(VA.getValVT()));
541 else if (VA.getLocInfo() == CCValAssign::ZExt)
542 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value,
543 DAG.getValueType(VA.getValVT()));
546 Value = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Value);
547 else if (VA.getLocInfo() == CCValAssign::Indirect)
548 Value = DAG.getLoad(VA.getValVT(), DL, Chain, Value,
549 MachinePointerInfo(), false, false, false, 0);
551 assert(VA.getLocInfo() == CCValAssign::Full && "Unsupported getLocInfo");
555 // Value is a value of type VA.getValVT() that we need to copy into
556 // the location described by VA. Return a copy of Value converted to
557 // VA.getValVT(). The caller is responsible for handling indirect values.
558 static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDLoc DL,
559 CCValAssign &VA, SDValue Value) {
560 switch (VA.getLocInfo()) {
561 case CCValAssign::SExt:
562 return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value);
563 case CCValAssign::ZExt:
564 return DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Value);
565 case CCValAssign::AExt:
566 return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value);
567 case CCValAssign::Full:
570 llvm_unreachable("Unhandled getLocInfo()");
574 SDValue SystemZTargetLowering::
575 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
576 const SmallVectorImpl<ISD::InputArg> &Ins,
577 SDLoc DL, SelectionDAG &DAG,
578 SmallVectorImpl<SDValue> &InVals) const {
579 MachineFunction &MF = DAG.getMachineFunction();
580 MachineFrameInfo *MFI = MF.getFrameInfo();
581 MachineRegisterInfo &MRI = MF.getRegInfo();
582 SystemZMachineFunctionInfo *FuncInfo =
583 MF.getInfo<SystemZMachineFunctionInfo>();
584 const SystemZFrameLowering *TFL =
585 static_cast<const SystemZFrameLowering *>(TM.getFrameLowering());
587 // Assign locations to all of the incoming arguments.
588 SmallVector<CCValAssign, 16> ArgLocs;
589 CCState CCInfo(CallConv, IsVarArg, MF, TM, ArgLocs, *DAG.getContext());
590 CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ);
592 unsigned NumFixedGPRs = 0;
593 unsigned NumFixedFPRs = 0;
594 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
596 CCValAssign &VA = ArgLocs[I];
597 EVT LocVT = VA.getLocVT();
599 // Arguments passed in registers
600 const TargetRegisterClass *RC;
601 switch (LocVT.getSimpleVT().SimpleTy) {
603 // Integers smaller than i64 should be promoted to i64.
604 llvm_unreachable("Unexpected argument type");
607 RC = &SystemZ::GR32BitRegClass;
611 RC = &SystemZ::GR64BitRegClass;
615 RC = &SystemZ::FP32BitRegClass;
619 RC = &SystemZ::FP64BitRegClass;
623 unsigned VReg = MRI.createVirtualRegister(RC);
624 MRI.addLiveIn(VA.getLocReg(), VReg);
625 ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
627 assert(VA.isMemLoc() && "Argument not register or memory");
629 // Create the frame index object for this incoming parameter.
630 int FI = MFI->CreateFixedObject(LocVT.getSizeInBits() / 8,
631 VA.getLocMemOffset(), true);
633 // Create the SelectionDAG nodes corresponding to a load
634 // from this parameter. Unpromoted ints and floats are
635 // passed as right-justified 8-byte values.
636 EVT PtrVT = getPointerTy();
637 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
638 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
639 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4));
640 ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN,
641 MachinePointerInfo::getFixedStack(FI),
642 false, false, false, 0);
645 // Convert the value of the argument register into the value that's
647 InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, ArgValue));
651 // Save the number of non-varargs registers for later use by va_start, etc.
652 FuncInfo->setVarArgsFirstGPR(NumFixedGPRs);
653 FuncInfo->setVarArgsFirstFPR(NumFixedFPRs);
655 // Likewise the address (in the form of a frame index) of where the
656 // first stack vararg would be. The 1-byte size here is arbitrary.
657 int64_t StackSize = CCInfo.getNextStackOffset();
658 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize, true));
660 // ...and a similar frame index for the caller-allocated save area
661 // that will be used to store the incoming registers.
662 int64_t RegSaveOffset = TFL->getOffsetOfLocalArea();
663 unsigned RegSaveIndex = MFI->CreateFixedObject(1, RegSaveOffset, true);
664 FuncInfo->setRegSaveFrameIndex(RegSaveIndex);
666 // Store the FPR varargs in the reserved frame slots. (We store the
667 // GPRs as part of the prologue.)
668 if (NumFixedFPRs < SystemZ::NumArgFPRs) {
669 SDValue MemOps[SystemZ::NumArgFPRs];
670 for (unsigned I = NumFixedFPRs; I < SystemZ::NumArgFPRs; ++I) {
671 unsigned Offset = TFL->getRegSpillOffset(SystemZ::ArgFPRs[I]);
672 int FI = MFI->CreateFixedObject(8, RegSaveOffset + Offset, true);
673 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
674 unsigned VReg = MF.addLiveIn(SystemZ::ArgFPRs[I],
675 &SystemZ::FP64BitRegClass);
676 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f64);
677 MemOps[I] = DAG.getStore(ArgValue.getValue(1), DL, ArgValue, FIN,
678 MachinePointerInfo::getFixedStack(FI),
682 // Join the stores, which are independent of one another.
683 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
684 &MemOps[NumFixedFPRs],
685 SystemZ::NumArgFPRs - NumFixedFPRs);
693 SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
694 SmallVectorImpl<SDValue> &InVals) const {
695 SelectionDAG &DAG = CLI.DAG;
697 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
698 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
699 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
700 SDValue Chain = CLI.Chain;
701 SDValue Callee = CLI.Callee;
702 bool &isTailCall = CLI.IsTailCall;
703 CallingConv::ID CallConv = CLI.CallConv;
704 bool IsVarArg = CLI.IsVarArg;
705 MachineFunction &MF = DAG.getMachineFunction();
706 EVT PtrVT = getPointerTy();
708 // SystemZ target does not yet support tail call optimization.
711 // Analyze the operands of the call, assigning locations to each operand.
712 SmallVector<CCValAssign, 16> ArgLocs;
713 CCState ArgCCInfo(CallConv, IsVarArg, MF, TM, ArgLocs, *DAG.getContext());
714 ArgCCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
716 // Get a count of how many bytes are to be pushed on the stack.
717 unsigned NumBytes = ArgCCInfo.getNextStackOffset();
719 // Mark the start of the call.
720 Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes, PtrVT, true),
723 // Copy argument values to their designated locations.
724 SmallVector<std::pair<unsigned, SDValue>, 9> RegsToPass;
725 SmallVector<SDValue, 8> MemOpChains;
727 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
728 CCValAssign &VA = ArgLocs[I];
729 SDValue ArgValue = OutVals[I];
731 if (VA.getLocInfo() == CCValAssign::Indirect) {
732 // Store the argument in a stack slot and pass its address.
733 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
734 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
735 MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, SpillSlot,
736 MachinePointerInfo::getFixedStack(FI),
738 ArgValue = SpillSlot;
740 ArgValue = convertValVTToLocVT(DAG, DL, VA, ArgValue);
743 // Queue up the argument copies and emit them at the end.
744 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));
746 assert(VA.isMemLoc() && "Argument not register or memory");
748 // Work out the address of the stack slot. Unpromoted ints and
749 // floats are passed as right-justified 8-byte values.
750 if (!StackPtr.getNode())
751 StackPtr = DAG.getCopyFromReg(Chain, DL, SystemZ::R15D, PtrVT);
752 unsigned Offset = SystemZMC::CallFrameSize + VA.getLocMemOffset();
753 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
755 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
756 DAG.getIntPtrConstant(Offset));
759 MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, Address,
760 MachinePointerInfo(),
765 // Join the stores, which are independent of one another.
766 if (!MemOpChains.empty())
767 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
768 &MemOpChains[0], MemOpChains.size());
770 // Build a sequence of copy-to-reg nodes, chained and glued together.
772 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {
773 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
774 RegsToPass[I].second, Glue);
775 Glue = Chain.getValue(1);
778 // Accept direct calls by converting symbolic call addresses to the
779 // associated Target* opcodes.
780 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
781 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT);
782 Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
783 } else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
784 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT);
785 Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
788 // The first call operand is the chain and the second is the target address.
789 SmallVector<SDValue, 8> Ops;
790 Ops.push_back(Chain);
791 Ops.push_back(Callee);
793 // Add argument registers to the end of the list so that they are
794 // known live into the call.
795 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I)
796 Ops.push_back(DAG.getRegister(RegsToPass[I].first,
797 RegsToPass[I].second.getValueType()));
799 // Glue the call to the argument copies, if any.
804 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
805 Chain = DAG.getNode(SystemZISD::CALL, DL, NodeTys, &Ops[0], Ops.size());
806 Glue = Chain.getValue(1);
808 // Mark the end of the call, which is glued to the call itself.
809 Chain = DAG.getCALLSEQ_END(Chain,
810 DAG.getConstant(NumBytes, PtrVT, true),
811 DAG.getConstant(0, PtrVT, true),
813 Glue = Chain.getValue(1);
815 // Assign locations to each value returned by this call.
816 SmallVector<CCValAssign, 16> RetLocs;
817 CCState RetCCInfo(CallConv, IsVarArg, MF, TM, RetLocs, *DAG.getContext());
818 RetCCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ);
820 // Copy all of the result registers out of their specified physreg.
821 for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
822 CCValAssign &VA = RetLocs[I];
824 // Copy the value out, gluing the copy to the end of the call sequence.
825 SDValue RetValue = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(),
826 VA.getLocVT(), Glue);
827 Chain = RetValue.getValue(1);
828 Glue = RetValue.getValue(2);
830 // Convert the value of the return register into the value that's
832 InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, RetValue));
839 SystemZTargetLowering::LowerReturn(SDValue Chain,
840 CallingConv::ID CallConv, bool IsVarArg,
841 const SmallVectorImpl<ISD::OutputArg> &Outs,
842 const SmallVectorImpl<SDValue> &OutVals,
843 SDLoc DL, SelectionDAG &DAG) const {
844 MachineFunction &MF = DAG.getMachineFunction();
846 // Assign locations to each returned value.
847 SmallVector<CCValAssign, 16> RetLocs;
848 CCState RetCCInfo(CallConv, IsVarArg, MF, TM, RetLocs, *DAG.getContext());
849 RetCCInfo.AnalyzeReturn(Outs, RetCC_SystemZ);
851 // Quick exit for void returns
853 return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, Chain);
855 // Copy the result values into the output registers.
857 SmallVector<SDValue, 4> RetOps;
858 RetOps.push_back(Chain);
859 for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
860 CCValAssign &VA = RetLocs[I];
861 SDValue RetValue = OutVals[I];
863 // Make the return register live on exit.
864 assert(VA.isRegLoc() && "Can only return in registers!");
866 // Promote the value as required.
867 RetValue = convertValVTToLocVT(DAG, DL, VA, RetValue);
869 // Chain and glue the copies together.
870 unsigned Reg = VA.getLocReg();
871 Chain = DAG.getCopyToReg(Chain, DL, Reg, RetValue, Glue);
872 Glue = Chain.getValue(1);
873 RetOps.push_back(DAG.getRegister(Reg, VA.getLocVT()));
876 // Update chain and glue.
879 RetOps.push_back(Glue);
881 return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other,
882 RetOps.data(), RetOps.size());
885 // CC is a comparison that will be implemented using an integer or
886 // floating-point comparison. Return the condition code mask for
887 // a branch on true. In the integer case, CCMASK_CMP_UO is set for
888 // unsigned comparisons and clear for signed ones. In the floating-point
889 // case, CCMASK_CMP_UO has its normal mask meaning (unordered).
890 static unsigned CCMaskForCondCode(ISD::CondCode CC) {
892 case ISD::SET##X: return SystemZ::CCMASK_CMP_##X; \
893 case ISD::SETO##X: return SystemZ::CCMASK_CMP_##X; \
894 case ISD::SETU##X: return SystemZ::CCMASK_CMP_UO | SystemZ::CCMASK_CMP_##X
898 llvm_unreachable("Invalid integer condition!");
907 case ISD::SETO: return SystemZ::CCMASK_CMP_O;
908 case ISD::SETUO: return SystemZ::CCMASK_CMP_UO;
913 // If a comparison described by IsUnsigned, CCMask, CmpOp0 and CmpOp1
914 // is suitable for CLI(Y), CHHSI or CLHHSI, adjust the operands as necessary.
915 static void adjustSubwordCmp(SelectionDAG &DAG, bool &IsUnsigned,
916 SDValue &CmpOp0, SDValue &CmpOp1,
918 // For us to make any changes, it must a comparison between a single-use
919 // load and a constant.
920 if (!CmpOp0.hasOneUse() ||
921 CmpOp0.getOpcode() != ISD::LOAD ||
922 CmpOp1.getOpcode() != ISD::Constant)
925 // We must have an 8- or 16-bit load.
926 LoadSDNode *Load = cast<LoadSDNode>(CmpOp0);
927 unsigned NumBits = Load->getMemoryVT().getStoreSizeInBits();
928 if (NumBits != 8 && NumBits != 16)
931 // The load must be an extending one and the constant must be within the
932 // range of the unextended value.
933 ConstantSDNode *Constant = cast<ConstantSDNode>(CmpOp1);
934 uint64_t Value = Constant->getZExtValue();
935 uint64_t Mask = (1 << NumBits) - 1;
936 if (Load->getExtensionType() == ISD::SEXTLOAD) {
937 int64_t SignedValue = Constant->getSExtValue();
938 if (uint64_t(SignedValue) + (1ULL << (NumBits - 1)) > Mask)
940 // Unsigned comparison between two sign-extended values is equivalent
941 // to unsigned comparison between two zero-extended values.
944 else if (CCMask == SystemZ::CCMASK_CMP_EQ ||
945 CCMask == SystemZ::CCMASK_CMP_NE)
946 // Any choice of IsUnsigned is OK for equality comparisons.
947 // We could use either CHHSI or CLHHSI for 16-bit comparisons,
948 // but since we use CLHHSI for zero extensions, it seems better
949 // to be consistent and do the same here.
950 Value &= Mask, IsUnsigned = true;
951 else if (NumBits == 8) {
952 // Try to treat the comparison as unsigned, so that we can use CLI.
953 // Adjust CCMask and Value as necessary.
954 if (Value == 0 && CCMask == SystemZ::CCMASK_CMP_LT)
955 // Test whether the high bit of the byte is set.
956 Value = 127, CCMask = SystemZ::CCMASK_CMP_GT, IsUnsigned = true;
957 else if (SignedValue == -1 && CCMask == SystemZ::CCMASK_CMP_GT)
958 // Test whether the high bit of the byte is clear.
959 Value = 128, CCMask = SystemZ::CCMASK_CMP_LT, IsUnsigned = true;
961 // No instruction exists for this combination.
964 } else if (Load->getExtensionType() == ISD::ZEXTLOAD) {
967 // Signed comparison between two zero-extended values is equivalent
968 // to unsigned comparison.
973 // Make sure that the first operand is an i32 of the right extension type.
974 ISD::LoadExtType ExtType = IsUnsigned ? ISD::ZEXTLOAD : ISD::SEXTLOAD;
975 if (CmpOp0.getValueType() != MVT::i32 ||
976 Load->getExtensionType() != ExtType)
977 CmpOp0 = DAG.getExtLoad(ExtType, SDLoc(Load), MVT::i32,
978 Load->getChain(), Load->getBasePtr(),
979 Load->getPointerInfo(), Load->getMemoryVT(),
980 Load->isVolatile(), Load->isNonTemporal(),
981 Load->getAlignment());
983 // Make sure that the second operand is an i32 with the right value.
984 if (CmpOp1.getValueType() != MVT::i32 ||
985 Value != Constant->getZExtValue())
986 CmpOp1 = DAG.getConstant(Value, MVT::i32);
989 // Return true if a comparison described by CCMask, CmpOp0 and CmpOp1
990 // is an equality comparison that is better implemented using unsigned
991 // rather than signed comparison instructions.
992 static bool preferUnsignedComparison(SelectionDAG &DAG, SDValue CmpOp0,
993 SDValue CmpOp1, unsigned CCMask) {
994 // The test must be for equality or inequality.
995 if (CCMask != SystemZ::CCMASK_CMP_EQ && CCMask != SystemZ::CCMASK_CMP_NE)
998 if (CmpOp1.getOpcode() == ISD::Constant) {
999 uint64_t Value = cast<ConstantSDNode>(CmpOp1)->getSExtValue();
1001 // If we're comparing with memory, prefer unsigned comparisons for
1002 // values that are in the unsigned 16-bit range but not the signed
1003 // 16-bit range. We want to use CLFHSI and CLGHSI.
1004 if (CmpOp0.hasOneUse() &&
1005 ISD::isNormalLoad(CmpOp0.getNode()) &&
1006 (Value >= 32768 && Value < 65536))
1009 // Use unsigned comparisons for values that are in the CLGFI range
1010 // but not in the CGFI range.
1011 if (CmpOp0.getValueType() == MVT::i64 && (Value >> 31) == 1)
1017 // Prefer CL for zero-extended loads.
1018 if (CmpOp1.getOpcode() == ISD::ZERO_EXTEND ||
1019 ISD::isZEXTLoad(CmpOp1.getNode()))
1022 // ...and for "in-register" zero extensions.
1023 if (CmpOp1.getOpcode() == ISD::AND && CmpOp1.getValueType() == MVT::i64) {
1024 SDValue Mask = CmpOp1.getOperand(1);
1025 if (Mask.getOpcode() == ISD::Constant &&
1026 cast<ConstantSDNode>(Mask)->getZExtValue() == 0xffffffff)
1033 // Return a target node that compares CmpOp0 with CmpOp1 and stores a
1034 // 2-bit result in CC. Set CCValid to the CCMASK_* of all possible
1035 // 2-bit results and CCMask to the subset of those results that are
1036 // associated with Cond.
1037 static SDValue emitCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1,
1038 ISD::CondCode Cond, unsigned &CCValid,
1040 bool IsUnsigned = false;
1041 CCMask = CCMaskForCondCode(Cond);
1042 if (CmpOp0.getValueType().isFloatingPoint())
1043 CCValid = SystemZ::CCMASK_FCMP;
1045 IsUnsigned = CCMask & SystemZ::CCMASK_CMP_UO;
1046 CCValid = SystemZ::CCMASK_ICMP;
1048 adjustSubwordCmp(DAG, IsUnsigned, CmpOp0, CmpOp1, CCMask);
1049 if (preferUnsignedComparison(DAG, CmpOp0, CmpOp1, CCMask))
1054 return DAG.getNode((IsUnsigned ? SystemZISD::UCMP : SystemZISD::CMP),
1055 DL, MVT::Glue, CmpOp0, CmpOp1);
1058 // Lower a binary operation that produces two VT results, one in each
1059 // half of a GR128 pair. Op0 and Op1 are the VT operands to the operation,
1060 // Extend extends Op0 to a GR128, and Opcode performs the GR128 operation
1061 // on the extended Op0 and (unextended) Op1. Store the even register result
1062 // in Even and the odd register result in Odd.
1063 static void lowerGR128Binary(SelectionDAG &DAG, SDLoc DL, EVT VT,
1064 unsigned Extend, unsigned Opcode,
1065 SDValue Op0, SDValue Op1,
1066 SDValue &Even, SDValue &Odd) {
1067 SDNode *In128 = DAG.getMachineNode(Extend, DL, MVT::Untyped, Op0);
1068 SDValue Result = DAG.getNode(Opcode, DL, MVT::Untyped,
1069 SDValue(In128, 0), Op1);
1070 bool Is32Bit = is32Bit(VT);
1071 SDValue SubReg0 = DAG.getTargetConstant(SystemZ::even128(Is32Bit), VT);
1072 SDValue SubReg1 = DAG.getTargetConstant(SystemZ::odd128(Is32Bit), VT);
1073 SDNode *Reg0 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL,
1074 VT, Result, SubReg0);
1075 SDNode *Reg1 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL,
1076 VT, Result, SubReg1);
1077 Even = SDValue(Reg0, 0);
1078 Odd = SDValue(Reg1, 0);
1081 SDValue SystemZTargetLowering::lowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
1082 SDValue Chain = Op.getOperand(0);
1083 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1084 SDValue CmpOp0 = Op.getOperand(2);
1085 SDValue CmpOp1 = Op.getOperand(3);
1086 SDValue Dest = Op.getOperand(4);
1089 unsigned CCValid, CCMask;
1090 SDValue Flags = emitCmp(DAG, CmpOp0, CmpOp1, CC, CCValid, CCMask);
1091 return DAG.getNode(SystemZISD::BR_CCMASK, DL, Op.getValueType(),
1092 Chain, DAG.getConstant(CCValid, MVT::i32),
1093 DAG.getConstant(CCMask, MVT::i32), Dest, Flags);
1096 SDValue SystemZTargetLowering::lowerSELECT_CC(SDValue Op,
1097 SelectionDAG &DAG) const {
1098 SDValue CmpOp0 = Op.getOperand(0);
1099 SDValue CmpOp1 = Op.getOperand(1);
1100 SDValue TrueOp = Op.getOperand(2);
1101 SDValue FalseOp = Op.getOperand(3);
1102 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1105 unsigned CCValid, CCMask;
1106 SDValue Flags = emitCmp(DAG, CmpOp0, CmpOp1, CC, CCValid, CCMask);
1108 SmallVector<SDValue, 5> Ops;
1109 Ops.push_back(TrueOp);
1110 Ops.push_back(FalseOp);
1111 Ops.push_back(DAG.getConstant(CCValid, MVT::i32));
1112 Ops.push_back(DAG.getConstant(CCMask, MVT::i32));
1113 Ops.push_back(Flags);
1115 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1116 return DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VTs, &Ops[0], Ops.size());
1119 SDValue SystemZTargetLowering::lowerGlobalAddress(GlobalAddressSDNode *Node,
1120 SelectionDAG &DAG) const {
1122 const GlobalValue *GV = Node->getGlobal();
1123 int64_t Offset = Node->getOffset();
1124 EVT PtrVT = getPointerTy();
1125 Reloc::Model RM = TM.getRelocationModel();
1126 CodeModel::Model CM = TM.getCodeModel();
1129 if (Subtarget.isPC32DBLSymbol(GV, RM, CM)) {
1130 // Make sure that the offset is aligned to a halfword. If it isn't,
1131 // create an "anchor" at the previous 12-bit boundary.
1132 // FIXME check whether there is a better way of handling this.
1134 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
1135 Offset & ~uint64_t(0xfff));
1138 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Offset);
1141 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1143 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, SystemZII::MO_GOT);
1144 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1145 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
1146 MachinePointerInfo::getGOT(), false, false, false, 0);
1149 // If there was a non-zero offset that we didn't fold, create an explicit
1152 Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result,
1153 DAG.getConstant(Offset, PtrVT));
1158 SDValue SystemZTargetLowering::lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
1159 SelectionDAG &DAG) const {
1161 const GlobalValue *GV = Node->getGlobal();
1162 EVT PtrVT = getPointerTy();
1163 TLSModel::Model model = TM.getTLSModel(GV);
1165 if (model != TLSModel::LocalExec)
1166 llvm_unreachable("only local-exec TLS mode supported");
1168 // The high part of the thread pointer is in access register 0.
1169 SDValue TPHi = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
1170 DAG.getConstant(0, MVT::i32));
1171 TPHi = DAG.getNode(ISD::ANY_EXTEND, DL, PtrVT, TPHi);
1173 // The low part of the thread pointer is in access register 1.
1174 SDValue TPLo = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
1175 DAG.getConstant(1, MVT::i32));
1176 TPLo = DAG.getNode(ISD::ZERO_EXTEND, DL, PtrVT, TPLo);
1178 // Merge them into a single 64-bit address.
1179 SDValue TPHiShifted = DAG.getNode(ISD::SHL, DL, PtrVT, TPHi,
1180 DAG.getConstant(32, PtrVT));
1181 SDValue TP = DAG.getNode(ISD::OR, DL, PtrVT, TPHiShifted, TPLo);
1183 // Get the offset of GA from the thread pointer.
1184 SystemZConstantPoolValue *CPV =
1185 SystemZConstantPoolValue::Create(GV, SystemZCP::NTPOFF);
1187 // Force the offset into the constant pool and load it from there.
1188 SDValue CPAddr = DAG.getConstantPool(CPV, PtrVT, 8);
1189 SDValue Offset = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(),
1190 CPAddr, MachinePointerInfo::getConstantPool(),
1191 false, false, false, 0);
1193 // Add the base and offset together.
1194 return DAG.getNode(ISD::ADD, DL, PtrVT, TP, Offset);
1197 SDValue SystemZTargetLowering::lowerBlockAddress(BlockAddressSDNode *Node,
1198 SelectionDAG &DAG) const {
1200 const BlockAddress *BA = Node->getBlockAddress();
1201 int64_t Offset = Node->getOffset();
1202 EVT PtrVT = getPointerTy();
1204 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset);
1205 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1209 SDValue SystemZTargetLowering::lowerJumpTable(JumpTableSDNode *JT,
1210 SelectionDAG &DAG) const {
1212 EVT PtrVT = getPointerTy();
1213 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1215 // Use LARL to load the address of the table.
1216 return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1219 SDValue SystemZTargetLowering::lowerConstantPool(ConstantPoolSDNode *CP,
1220 SelectionDAG &DAG) const {
1222 EVT PtrVT = getPointerTy();
1225 if (CP->isMachineConstantPoolEntry())
1226 Result = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1227 CP->getAlignment());
1229 Result = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1230 CP->getAlignment(), CP->getOffset());
1232 // Use LARL to load the address of the constant pool entry.
1233 return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1236 SDValue SystemZTargetLowering::lowerBITCAST(SDValue Op,
1237 SelectionDAG &DAG) const {
1239 SDValue In = Op.getOperand(0);
1240 EVT InVT = In.getValueType();
1241 EVT ResVT = Op.getValueType();
1243 SDValue SubReg32 = DAG.getTargetConstant(SystemZ::subreg_32bit, MVT::i64);
1244 SDValue Shift32 = DAG.getConstant(32, MVT::i64);
1245 if (InVT == MVT::i32 && ResVT == MVT::f32) {
1246 SDValue In64 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, In);
1247 SDValue Shift = DAG.getNode(ISD::SHL, DL, MVT::i64, In64, Shift32);
1248 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::f64, Shift);
1249 SDNode *Out = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL,
1250 MVT::f32, Out64, SubReg32);
1251 return SDValue(Out, 0);
1253 if (InVT == MVT::f32 && ResVT == MVT::i32) {
1254 SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::f64);
1255 SDNode *In64 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL,
1256 MVT::f64, SDValue(U64, 0), In, SubReg32);
1257 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::i64, SDValue(In64, 0));
1258 SDValue Shift = DAG.getNode(ISD::SRL, DL, MVT::i64, Out64, Shift32);
1259 SDValue Out = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Shift);
1262 llvm_unreachable("Unexpected bitcast combination");
1265 SDValue SystemZTargetLowering::lowerVASTART(SDValue Op,
1266 SelectionDAG &DAG) const {
1267 MachineFunction &MF = DAG.getMachineFunction();
1268 SystemZMachineFunctionInfo *FuncInfo =
1269 MF.getInfo<SystemZMachineFunctionInfo>();
1270 EVT PtrVT = getPointerTy();
1272 SDValue Chain = Op.getOperand(0);
1273 SDValue Addr = Op.getOperand(1);
1274 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1277 // The initial values of each field.
1278 const unsigned NumFields = 4;
1279 SDValue Fields[NumFields] = {
1280 DAG.getConstant(FuncInfo->getVarArgsFirstGPR(), PtrVT),
1281 DAG.getConstant(FuncInfo->getVarArgsFirstFPR(), PtrVT),
1282 DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT),
1283 DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT)
1286 // Store each field into its respective slot.
1287 SDValue MemOps[NumFields];
1288 unsigned Offset = 0;
1289 for (unsigned I = 0; I < NumFields; ++I) {
1290 SDValue FieldAddr = Addr;
1292 FieldAddr = DAG.getNode(ISD::ADD, DL, PtrVT, FieldAddr,
1293 DAG.getIntPtrConstant(Offset));
1294 MemOps[I] = DAG.getStore(Chain, DL, Fields[I], FieldAddr,
1295 MachinePointerInfo(SV, Offset),
1299 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps, NumFields);
1302 SDValue SystemZTargetLowering::lowerVACOPY(SDValue Op,
1303 SelectionDAG &DAG) const {
1304 SDValue Chain = Op.getOperand(0);
1305 SDValue DstPtr = Op.getOperand(1);
1306 SDValue SrcPtr = Op.getOperand(2);
1307 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
1308 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
1311 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, DAG.getIntPtrConstant(32),
1312 /*Align*/8, /*isVolatile*/false, /*AlwaysInline*/false,
1313 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
1316 SDValue SystemZTargetLowering::
1317 lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
1318 SDValue Chain = Op.getOperand(0);
1319 SDValue Size = Op.getOperand(1);
1322 unsigned SPReg = getStackPointerRegisterToSaveRestore();
1324 // Get a reference to the stack pointer.
1325 SDValue OldSP = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i64);
1327 // Get the new stack pointer value.
1328 SDValue NewSP = DAG.getNode(ISD::SUB, DL, MVT::i64, OldSP, Size);
1330 // Copy the new stack pointer back.
1331 Chain = DAG.getCopyToReg(Chain, DL, SPReg, NewSP);
1333 // The allocated data lives above the 160 bytes allocated for the standard
1334 // frame, plus any outgoing stack arguments. We don't know how much that
1335 // amounts to yet, so emit a special ADJDYNALLOC placeholder.
1336 SDValue ArgAdjust = DAG.getNode(SystemZISD::ADJDYNALLOC, DL, MVT::i64);
1337 SDValue Result = DAG.getNode(ISD::ADD, DL, MVT::i64, NewSP, ArgAdjust);
1339 SDValue Ops[2] = { Result, Chain };
1340 return DAG.getMergeValues(Ops, 2, DL);
1343 SDValue SystemZTargetLowering::lowerUMUL_LOHI(SDValue Op,
1344 SelectionDAG &DAG) const {
1345 EVT VT = Op.getValueType();
1347 assert(!is32Bit(VT) && "Only support 64-bit UMUL_LOHI");
1349 // UMUL_LOHI64 returns the low result in the odd register and the high
1350 // result in the even register. UMUL_LOHI is defined to return the
1351 // low half first, so the results are in reverse order.
1353 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
1354 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
1355 return DAG.getMergeValues(Ops, 2, DL);
1358 SDValue SystemZTargetLowering::lowerSDIVREM(SDValue Op,
1359 SelectionDAG &DAG) const {
1360 SDValue Op0 = Op.getOperand(0);
1361 SDValue Op1 = Op.getOperand(1);
1362 EVT VT = Op.getValueType();
1366 // We use DSGF for 32-bit division.
1368 Op0 = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op0);
1369 Opcode = SystemZISD::SDIVREM32;
1370 } else if (DAG.ComputeNumSignBits(Op1) > 32) {
1371 Op1 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op1);
1372 Opcode = SystemZISD::SDIVREM32;
1374 Opcode = SystemZISD::SDIVREM64;
1376 // DSG(F) takes a 64-bit dividend, so the even register in the GR128
1377 // input is "don't care". The instruction returns the remainder in
1378 // the even register and the quotient in the odd register.
1380 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, Opcode,
1381 Op0, Op1, Ops[1], Ops[0]);
1382 return DAG.getMergeValues(Ops, 2, DL);
1385 SDValue SystemZTargetLowering::lowerUDIVREM(SDValue Op,
1386 SelectionDAG &DAG) const {
1387 EVT VT = Op.getValueType();
1390 // DL(G) uses a double-width dividend, so we need to clear the even
1391 // register in the GR128 input. The instruction returns the remainder
1392 // in the even register and the quotient in the odd register.
1395 lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_32, SystemZISD::UDIVREM32,
1396 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
1398 lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_64, SystemZISD::UDIVREM64,
1399 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
1400 return DAG.getMergeValues(Ops, 2, DL);
1403 SDValue SystemZTargetLowering::lowerOR(SDValue Op, SelectionDAG &DAG) const {
1404 assert(Op.getValueType() == MVT::i64 && "Should be 64-bit operation");
1406 // Get the known-zero masks for each operand.
1407 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1) };
1408 APInt KnownZero[2], KnownOne[2];
1409 DAG.ComputeMaskedBits(Ops[0], KnownZero[0], KnownOne[0]);
1410 DAG.ComputeMaskedBits(Ops[1], KnownZero[1], KnownOne[1]);
1412 // See if the upper 32 bits of one operand and the lower 32 bits of the
1413 // other are known zero. They are the low and high operands respectively.
1414 uint64_t Masks[] = { KnownZero[0].getZExtValue(),
1415 KnownZero[1].getZExtValue() };
1417 if ((Masks[0] >> 32) == 0xffffffff && uint32_t(Masks[1]) == 0xffffffff)
1419 else if ((Masks[1] >> 32) == 0xffffffff && uint32_t(Masks[0]) == 0xffffffff)
1424 SDValue LowOp = Ops[Low];
1425 SDValue HighOp = Ops[High];
1427 // If the high part is a constant, we're better off using IILH.
1428 if (HighOp.getOpcode() == ISD::Constant)
1431 // If the low part is a constant that is outside the range of LHI,
1432 // then we're better off using IILF.
1433 if (LowOp.getOpcode() == ISD::Constant) {
1434 int64_t Value = int32_t(cast<ConstantSDNode>(LowOp)->getZExtValue());
1435 if (!isInt<16>(Value))
1439 // Check whether the high part is an AND that doesn't change the
1440 // high 32 bits and just masks out low bits. We can skip it if so.
1441 if (HighOp.getOpcode() == ISD::AND &&
1442 HighOp.getOperand(1).getOpcode() == ISD::Constant) {
1443 ConstantSDNode *MaskNode = cast<ConstantSDNode>(HighOp.getOperand(1));
1444 uint64_t Mask = MaskNode->getZExtValue() | Masks[High];
1445 if ((Mask >> 32) == 0xffffffff)
1446 HighOp = HighOp.getOperand(0);
1449 // Take advantage of the fact that all GR32 operations only change the
1450 // low 32 bits by truncating Low to an i32 and inserting it directly
1451 // using a subreg. The interesting cases are those where the truncation
1454 SDValue Low32 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, LowOp);
1455 SDValue SubReg32 = DAG.getTargetConstant(SystemZ::subreg_32bit, MVT::i64);
1456 SDNode *Result = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL,
1457 MVT::i64, HighOp, Low32, SubReg32);
1458 return SDValue(Result, 0);
1461 // Op is an 8-, 16-bit or 32-bit ATOMIC_LOAD_* operation. Lower the first
1462 // two into the fullword ATOMIC_LOADW_* operation given by Opcode.
1463 SDValue SystemZTargetLowering::lowerATOMIC_LOAD(SDValue Op,
1465 unsigned Opcode) const {
1466 AtomicSDNode *Node = cast<AtomicSDNode>(Op.getNode());
1468 // 32-bit operations need no code outside the main loop.
1469 EVT NarrowVT = Node->getMemoryVT();
1470 EVT WideVT = MVT::i32;
1471 if (NarrowVT == WideVT)
1474 int64_t BitSize = NarrowVT.getSizeInBits();
1475 SDValue ChainIn = Node->getChain();
1476 SDValue Addr = Node->getBasePtr();
1477 SDValue Src2 = Node->getVal();
1478 MachineMemOperand *MMO = Node->getMemOperand();
1480 EVT PtrVT = Addr.getValueType();
1482 // Convert atomic subtracts of constants into additions.
1483 if (Opcode == SystemZISD::ATOMIC_LOADW_SUB)
1484 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Src2)) {
1485 Opcode = SystemZISD::ATOMIC_LOADW_ADD;
1486 Src2 = DAG.getConstant(-Const->getSExtValue(), Src2.getValueType());
1489 // Get the address of the containing word.
1490 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
1491 DAG.getConstant(-4, PtrVT));
1493 // Get the number of bits that the word must be rotated left in order
1494 // to bring the field to the top bits of a GR32.
1495 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
1496 DAG.getConstant(3, PtrVT));
1497 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
1499 // Get the complementing shift amount, for rotating a field in the top
1500 // bits back to its proper position.
1501 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
1502 DAG.getConstant(0, WideVT), BitShift);
1504 // Extend the source operand to 32 bits and prepare it for the inner loop.
1505 // ATOMIC_SWAPW uses RISBG to rotate the field left, but all other
1506 // operations require the source to be shifted in advance. (This shift
1507 // can be folded if the source is constant.) For AND and NAND, the lower
1508 // bits must be set, while for other opcodes they should be left clear.
1509 if (Opcode != SystemZISD::ATOMIC_SWAPW)
1510 Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2,
1511 DAG.getConstant(32 - BitSize, WideVT));
1512 if (Opcode == SystemZISD::ATOMIC_LOADW_AND ||
1513 Opcode == SystemZISD::ATOMIC_LOADW_NAND)
1514 Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2,
1515 DAG.getConstant(uint32_t(-1) >> BitSize, WideVT));
1517 // Construct the ATOMIC_LOADW_* node.
1518 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
1519 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift,
1520 DAG.getConstant(BitSize, WideVT) };
1521 SDValue AtomicOp = DAG.getMemIntrinsicNode(Opcode, DL, VTList, Ops,
1522 array_lengthof(Ops),
1525 // Rotate the result of the final CS so that the field is in the lower
1526 // bits of a GR32, then truncate it.
1527 SDValue ResultShift = DAG.getNode(ISD::ADD, DL, WideVT, BitShift,
1528 DAG.getConstant(BitSize, WideVT));
1529 SDValue Result = DAG.getNode(ISD::ROTL, DL, WideVT, AtomicOp, ResultShift);
1531 SDValue RetOps[2] = { Result, AtomicOp.getValue(1) };
1532 return DAG.getMergeValues(RetOps, 2, DL);
1535 // Node is an 8- or 16-bit ATOMIC_CMP_SWAP operation. Lower the first two
1536 // into a fullword ATOMIC_CMP_SWAPW operation.
1537 SDValue SystemZTargetLowering::lowerATOMIC_CMP_SWAP(SDValue Op,
1538 SelectionDAG &DAG) const {
1539 AtomicSDNode *Node = cast<AtomicSDNode>(Op.getNode());
1541 // We have native support for 32-bit compare and swap.
1542 EVT NarrowVT = Node->getMemoryVT();
1543 EVT WideVT = MVT::i32;
1544 if (NarrowVT == WideVT)
1547 int64_t BitSize = NarrowVT.getSizeInBits();
1548 SDValue ChainIn = Node->getOperand(0);
1549 SDValue Addr = Node->getOperand(1);
1550 SDValue CmpVal = Node->getOperand(2);
1551 SDValue SwapVal = Node->getOperand(3);
1552 MachineMemOperand *MMO = Node->getMemOperand();
1554 EVT PtrVT = Addr.getValueType();
1556 // Get the address of the containing word.
1557 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
1558 DAG.getConstant(-4, PtrVT));
1560 // Get the number of bits that the word must be rotated left in order
1561 // to bring the field to the top bits of a GR32.
1562 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
1563 DAG.getConstant(3, PtrVT));
1564 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
1566 // Get the complementing shift amount, for rotating a field in the top
1567 // bits back to its proper position.
1568 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
1569 DAG.getConstant(0, WideVT), BitShift);
1571 // Construct the ATOMIC_CMP_SWAPW node.
1572 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
1573 SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift,
1574 NegBitShift, DAG.getConstant(BitSize, WideVT) };
1575 SDValue AtomicOp = DAG.getMemIntrinsicNode(SystemZISD::ATOMIC_CMP_SWAPW, DL,
1576 VTList, Ops, array_lengthof(Ops),
1581 SDValue SystemZTargetLowering::lowerSTACKSAVE(SDValue Op,
1582 SelectionDAG &DAG) const {
1583 MachineFunction &MF = DAG.getMachineFunction();
1584 MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
1585 return DAG.getCopyFromReg(Op.getOperand(0), SDLoc(Op),
1586 SystemZ::R15D, Op.getValueType());
1589 SDValue SystemZTargetLowering::lowerSTACKRESTORE(SDValue Op,
1590 SelectionDAG &DAG) const {
1591 MachineFunction &MF = DAG.getMachineFunction();
1592 MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
1593 return DAG.getCopyToReg(Op.getOperand(0), SDLoc(Op),
1594 SystemZ::R15D, Op.getOperand(1));
1597 SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
1598 SelectionDAG &DAG) const {
1599 switch (Op.getOpcode()) {
1601 return lowerBR_CC(Op, DAG);
1602 case ISD::SELECT_CC:
1603 return lowerSELECT_CC(Op, DAG);
1604 case ISD::GlobalAddress:
1605 return lowerGlobalAddress(cast<GlobalAddressSDNode>(Op), DAG);
1606 case ISD::GlobalTLSAddress:
1607 return lowerGlobalTLSAddress(cast<GlobalAddressSDNode>(Op), DAG);
1608 case ISD::BlockAddress:
1609 return lowerBlockAddress(cast<BlockAddressSDNode>(Op), DAG);
1610 case ISD::JumpTable:
1611 return lowerJumpTable(cast<JumpTableSDNode>(Op), DAG);
1612 case ISD::ConstantPool:
1613 return lowerConstantPool(cast<ConstantPoolSDNode>(Op), DAG);
1615 return lowerBITCAST(Op, DAG);
1617 return lowerVASTART(Op, DAG);
1619 return lowerVACOPY(Op, DAG);
1620 case ISD::DYNAMIC_STACKALLOC:
1621 return lowerDYNAMIC_STACKALLOC(Op, DAG);
1622 case ISD::UMUL_LOHI:
1623 return lowerUMUL_LOHI(Op, DAG);
1625 return lowerSDIVREM(Op, DAG);
1627 return lowerUDIVREM(Op, DAG);
1629 return lowerOR(Op, DAG);
1630 case ISD::ATOMIC_SWAP:
1631 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_SWAPW);
1632 case ISD::ATOMIC_LOAD_ADD:
1633 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_ADD);
1634 case ISD::ATOMIC_LOAD_SUB:
1635 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_SUB);
1636 case ISD::ATOMIC_LOAD_AND:
1637 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_AND);
1638 case ISD::ATOMIC_LOAD_OR:
1639 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_OR);
1640 case ISD::ATOMIC_LOAD_XOR:
1641 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_XOR);
1642 case ISD::ATOMIC_LOAD_NAND:
1643 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_NAND);
1644 case ISD::ATOMIC_LOAD_MIN:
1645 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_MIN);
1646 case ISD::ATOMIC_LOAD_MAX:
1647 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_MAX);
1648 case ISD::ATOMIC_LOAD_UMIN:
1649 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_UMIN);
1650 case ISD::ATOMIC_LOAD_UMAX:
1651 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_UMAX);
1652 case ISD::ATOMIC_CMP_SWAP:
1653 return lowerATOMIC_CMP_SWAP(Op, DAG);
1654 case ISD::STACKSAVE:
1655 return lowerSTACKSAVE(Op, DAG);
1656 case ISD::STACKRESTORE:
1657 return lowerSTACKRESTORE(Op, DAG);
1659 llvm_unreachable("Unexpected node to lower");
1663 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
1664 #define OPCODE(NAME) case SystemZISD::NAME: return "SystemZISD::" #NAME
1668 OPCODE(PCREL_WRAPPER);
1672 OPCODE(SELECT_CCMASK);
1673 OPCODE(ADJDYNALLOC);
1674 OPCODE(EXTRACT_ACCESS);
1675 OPCODE(UMUL_LOHI64);
1680 OPCODE(ATOMIC_SWAPW);
1681 OPCODE(ATOMIC_LOADW_ADD);
1682 OPCODE(ATOMIC_LOADW_SUB);
1683 OPCODE(ATOMIC_LOADW_AND);
1684 OPCODE(ATOMIC_LOADW_OR);
1685 OPCODE(ATOMIC_LOADW_XOR);
1686 OPCODE(ATOMIC_LOADW_NAND);
1687 OPCODE(ATOMIC_LOADW_MIN);
1688 OPCODE(ATOMIC_LOADW_MAX);
1689 OPCODE(ATOMIC_LOADW_UMIN);
1690 OPCODE(ATOMIC_LOADW_UMAX);
1691 OPCODE(ATOMIC_CMP_SWAPW);
1697 //===----------------------------------------------------------------------===//
1699 //===----------------------------------------------------------------------===//
1701 // Create a new basic block after MBB.
1702 static MachineBasicBlock *emitBlockAfter(MachineBasicBlock *MBB) {
1703 MachineFunction &MF = *MBB->getParent();
1704 MachineBasicBlock *NewMBB = MF.CreateMachineBasicBlock(MBB->getBasicBlock());
1705 MF.insert(llvm::next(MachineFunction::iterator(MBB)), NewMBB);
1709 // Split MBB after MI and return the new block (the one that contains
1710 // instructions after MI).
1711 static MachineBasicBlock *splitBlockAfter(MachineInstr *MI,
1712 MachineBasicBlock *MBB) {
1713 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
1714 NewMBB->splice(NewMBB->begin(), MBB,
1715 llvm::next(MachineBasicBlock::iterator(MI)),
1717 NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
1721 // Implement EmitInstrWithCustomInserter for pseudo Select* instruction MI.
1723 SystemZTargetLowering::emitSelect(MachineInstr *MI,
1724 MachineBasicBlock *MBB) const {
1725 const SystemZInstrInfo *TII = TM.getInstrInfo();
1727 unsigned DestReg = MI->getOperand(0).getReg();
1728 unsigned TrueReg = MI->getOperand(1).getReg();
1729 unsigned FalseReg = MI->getOperand(2).getReg();
1730 unsigned CCValid = MI->getOperand(3).getImm();
1731 unsigned CCMask = MI->getOperand(4).getImm();
1732 DebugLoc DL = MI->getDebugLoc();
1734 MachineBasicBlock *StartMBB = MBB;
1735 MachineBasicBlock *JoinMBB = splitBlockAfter(MI, MBB);
1736 MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
1739 // BRC CCMask, JoinMBB
1740 // # fallthrough to FalseMBB
1742 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
1743 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
1744 MBB->addSuccessor(JoinMBB);
1745 MBB->addSuccessor(FalseMBB);
1748 // # fallthrough to JoinMBB
1750 MBB->addSuccessor(JoinMBB);
1753 // %Result = phi [ %FalseReg, FalseMBB ], [ %TrueReg, StartMBB ]
1756 BuildMI(*MBB, MBB->begin(), DL, TII->get(SystemZ::PHI), DestReg)
1757 .addReg(TrueReg).addMBB(StartMBB)
1758 .addReg(FalseReg).addMBB(FalseMBB);
1760 MI->eraseFromParent();
1764 // Implement EmitInstrWithCustomInserter for pseudo CondStore* instruction MI.
1765 // StoreOpcode is the store to use and Invert says whether the store should
1766 // happen when the condition is false rather than true. If a STORE ON
1767 // CONDITION is available, STOCOpcode is its opcode, otherwise it is 0.
1769 SystemZTargetLowering::emitCondStore(MachineInstr *MI,
1770 MachineBasicBlock *MBB,
1771 unsigned StoreOpcode, unsigned STOCOpcode,
1772 bool Invert) const {
1773 const SystemZInstrInfo *TII = TM.getInstrInfo();
1775 unsigned SrcReg = MI->getOperand(0).getReg();
1776 MachineOperand Base = MI->getOperand(1);
1777 int64_t Disp = MI->getOperand(2).getImm();
1778 unsigned IndexReg = MI->getOperand(3).getReg();
1779 unsigned CCValid = MI->getOperand(4).getImm();
1780 unsigned CCMask = MI->getOperand(5).getImm();
1781 DebugLoc DL = MI->getDebugLoc();
1783 StoreOpcode = TII->getOpcodeForOffset(StoreOpcode, Disp);
1785 // Use STOCOpcode if possible. We could use different store patterns in
1786 // order to avoid matching the index register, but the performance trade-offs
1787 // might be more complicated in that case.
1788 if (STOCOpcode && !IndexReg && TM.getSubtargetImpl()->hasLoadStoreOnCond()) {
1791 BuildMI(*MBB, MI, DL, TII->get(STOCOpcode))
1792 .addReg(SrcReg).addOperand(Base).addImm(Disp).addImm(CCMask);
1793 MI->eraseFromParent();
1797 // Get the condition needed to branch around the store.
1801 MachineBasicBlock *StartMBB = MBB;
1802 MachineBasicBlock *JoinMBB = splitBlockAfter(MI, MBB);
1803 MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
1806 // BRC CCMask, JoinMBB
1807 // # fallthrough to FalseMBB
1809 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
1810 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
1811 MBB->addSuccessor(JoinMBB);
1812 MBB->addSuccessor(FalseMBB);
1815 // store %SrcReg, %Disp(%Index,%Base)
1816 // # fallthrough to JoinMBB
1818 BuildMI(MBB, DL, TII->get(StoreOpcode))
1819 .addReg(SrcReg).addOperand(Base).addImm(Disp).addReg(IndexReg);
1820 MBB->addSuccessor(JoinMBB);
1822 MI->eraseFromParent();
1826 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_LOAD{,W}_*
1827 // or ATOMIC_SWAP{,W} instruction MI. BinOpcode is the instruction that
1828 // performs the binary operation elided by "*", or 0 for ATOMIC_SWAP{,W}.
1829 // BitSize is the width of the field in bits, or 0 if this is a partword
1830 // ATOMIC_LOADW_* or ATOMIC_SWAPW instruction, in which case the bitsize
1831 // is one of the operands. Invert says whether the field should be
1832 // inverted after performing BinOpcode (e.g. for NAND).
1834 SystemZTargetLowering::emitAtomicLoadBinary(MachineInstr *MI,
1835 MachineBasicBlock *MBB,
1838 bool Invert) const {
1839 const SystemZInstrInfo *TII = TM.getInstrInfo();
1840 MachineFunction &MF = *MBB->getParent();
1841 MachineRegisterInfo &MRI = MF.getRegInfo();
1842 bool IsSubWord = (BitSize < 32);
1844 // Extract the operands. Base can be a register or a frame index.
1845 // Src2 can be a register or immediate.
1846 unsigned Dest = MI->getOperand(0).getReg();
1847 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
1848 int64_t Disp = MI->getOperand(2).getImm();
1849 MachineOperand Src2 = earlyUseOperand(MI->getOperand(3));
1850 unsigned BitShift = (IsSubWord ? MI->getOperand(4).getReg() : 0);
1851 unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0);
1852 DebugLoc DL = MI->getDebugLoc();
1854 BitSize = MI->getOperand(6).getImm();
1856 // Subword operations use 32-bit registers.
1857 const TargetRegisterClass *RC = (BitSize <= 32 ?
1858 &SystemZ::GR32BitRegClass :
1859 &SystemZ::GR64BitRegClass);
1860 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
1861 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
1863 // Get the right opcodes for the displacement.
1864 LOpcode = TII->getOpcodeForOffset(LOpcode, Disp);
1865 CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
1866 assert(LOpcode && CSOpcode && "Displacement out of range");
1868 // Create virtual registers for temporary results.
1869 unsigned OrigVal = MRI.createVirtualRegister(RC);
1870 unsigned OldVal = MRI.createVirtualRegister(RC);
1871 unsigned NewVal = (BinOpcode || IsSubWord ?
1872 MRI.createVirtualRegister(RC) : Src2.getReg());
1873 unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
1874 unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
1876 // Insert a basic block for the main loop.
1877 MachineBasicBlock *StartMBB = MBB;
1878 MachineBasicBlock *DoneMBB = splitBlockAfter(MI, MBB);
1879 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
1883 // %OrigVal = L Disp(%Base)
1884 // # fall through to LoopMMB
1886 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
1887 .addOperand(Base).addImm(Disp).addReg(0);
1888 MBB->addSuccessor(LoopMBB);
1891 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, LoopMBB ]
1892 // %RotatedOldVal = RLL %OldVal, 0(%BitShift)
1893 // %RotatedNewVal = OP %RotatedOldVal, %Src2
1894 // %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
1895 // %Dest = CS %OldVal, %NewVal, Disp(%Base)
1897 // # fall through to DoneMMB
1899 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
1900 .addReg(OrigVal).addMBB(StartMBB)
1901 .addReg(Dest).addMBB(LoopMBB);
1903 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
1904 .addReg(OldVal).addReg(BitShift).addImm(0);
1906 // Perform the operation normally and then invert every bit of the field.
1907 unsigned Tmp = MRI.createVirtualRegister(RC);
1908 BuildMI(MBB, DL, TII->get(BinOpcode), Tmp)
1909 .addReg(RotatedOldVal).addOperand(Src2);
1911 // XILF with the upper BitSize bits set.
1912 BuildMI(MBB, DL, TII->get(SystemZ::XILF32), RotatedNewVal)
1913 .addReg(Tmp).addImm(uint32_t(~0 << (32 - BitSize)));
1914 else if (BitSize == 32)
1915 // XILF with every bit set.
1916 BuildMI(MBB, DL, TII->get(SystemZ::XILF32), RotatedNewVal)
1917 .addReg(Tmp).addImm(~uint32_t(0));
1919 // Use LCGR and add -1 to the result, which is more compact than
1920 // an XILF, XILH pair.
1921 unsigned Tmp2 = MRI.createVirtualRegister(RC);
1922 BuildMI(MBB, DL, TII->get(SystemZ::LCGR), Tmp2).addReg(Tmp);
1923 BuildMI(MBB, DL, TII->get(SystemZ::AGHI), RotatedNewVal)
1924 .addReg(Tmp2).addImm(-1);
1926 } else if (BinOpcode)
1927 // A simply binary operation.
1928 BuildMI(MBB, DL, TII->get(BinOpcode), RotatedNewVal)
1929 .addReg(RotatedOldVal).addOperand(Src2);
1931 // Use RISBG to rotate Src2 into position and use it to replace the
1932 // field in RotatedOldVal.
1933 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedNewVal)
1934 .addReg(RotatedOldVal).addReg(Src2.getReg())
1935 .addImm(32).addImm(31 + BitSize).addImm(32 - BitSize);
1937 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
1938 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
1939 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
1940 .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
1941 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
1942 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
1943 MBB->addSuccessor(LoopMBB);
1944 MBB->addSuccessor(DoneMBB);
1946 MI->eraseFromParent();
1950 // Implement EmitInstrWithCustomInserter for pseudo
1951 // ATOMIC_LOAD{,W}_{,U}{MIN,MAX} instruction MI. CompareOpcode is the
1952 // instruction that should be used to compare the current field with the
1953 // minimum or maximum value. KeepOldMask is the BRC condition-code mask
1954 // for when the current field should be kept. BitSize is the width of
1955 // the field in bits, or 0 if this is a partword ATOMIC_LOADW_* instruction.
1957 SystemZTargetLowering::emitAtomicLoadMinMax(MachineInstr *MI,
1958 MachineBasicBlock *MBB,
1959 unsigned CompareOpcode,
1960 unsigned KeepOldMask,
1961 unsigned BitSize) const {
1962 const SystemZInstrInfo *TII = TM.getInstrInfo();
1963 MachineFunction &MF = *MBB->getParent();
1964 MachineRegisterInfo &MRI = MF.getRegInfo();
1965 bool IsSubWord = (BitSize < 32);
1967 // Extract the operands. Base can be a register or a frame index.
1968 unsigned Dest = MI->getOperand(0).getReg();
1969 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
1970 int64_t Disp = MI->getOperand(2).getImm();
1971 unsigned Src2 = MI->getOperand(3).getReg();
1972 unsigned BitShift = (IsSubWord ? MI->getOperand(4).getReg() : 0);
1973 unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0);
1974 DebugLoc DL = MI->getDebugLoc();
1976 BitSize = MI->getOperand(6).getImm();
1978 // Subword operations use 32-bit registers.
1979 const TargetRegisterClass *RC = (BitSize <= 32 ?
1980 &SystemZ::GR32BitRegClass :
1981 &SystemZ::GR64BitRegClass);
1982 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
1983 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
1985 // Get the right opcodes for the displacement.
1986 LOpcode = TII->getOpcodeForOffset(LOpcode, Disp);
1987 CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
1988 assert(LOpcode && CSOpcode && "Displacement out of range");
1990 // Create virtual registers for temporary results.
1991 unsigned OrigVal = MRI.createVirtualRegister(RC);
1992 unsigned OldVal = MRI.createVirtualRegister(RC);
1993 unsigned NewVal = MRI.createVirtualRegister(RC);
1994 unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
1995 unsigned RotatedAltVal = (IsSubWord ? MRI.createVirtualRegister(RC) : Src2);
1996 unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
1998 // Insert 3 basic blocks for the loop.
1999 MachineBasicBlock *StartMBB = MBB;
2000 MachineBasicBlock *DoneMBB = splitBlockAfter(MI, MBB);
2001 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
2002 MachineBasicBlock *UseAltMBB = emitBlockAfter(LoopMBB);
2003 MachineBasicBlock *UpdateMBB = emitBlockAfter(UseAltMBB);
2007 // %OrigVal = L Disp(%Base)
2008 // # fall through to LoopMMB
2010 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
2011 .addOperand(Base).addImm(Disp).addReg(0);
2012 MBB->addSuccessor(LoopMBB);
2015 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, UpdateMBB ]
2016 // %RotatedOldVal = RLL %OldVal, 0(%BitShift)
2017 // CompareOpcode %RotatedOldVal, %Src2
2018 // BRC KeepOldMask, UpdateMBB
2020 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
2021 .addReg(OrigVal).addMBB(StartMBB)
2022 .addReg(Dest).addMBB(UpdateMBB);
2024 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
2025 .addReg(OldVal).addReg(BitShift).addImm(0);
2026 BuildMI(MBB, DL, TII->get(CompareOpcode))
2027 .addReg(RotatedOldVal).addReg(Src2);
2028 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2029 .addImm(SystemZ::CCMASK_ICMP).addImm(KeepOldMask).addMBB(UpdateMBB);
2030 MBB->addSuccessor(UpdateMBB);
2031 MBB->addSuccessor(UseAltMBB);
2034 // %RotatedAltVal = RISBG %RotatedOldVal, %Src2, 32, 31 + BitSize, 0
2035 // # fall through to UpdateMMB
2038 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedAltVal)
2039 .addReg(RotatedOldVal).addReg(Src2)
2040 .addImm(32).addImm(31 + BitSize).addImm(0);
2041 MBB->addSuccessor(UpdateMBB);
2044 // %RotatedNewVal = PHI [ %RotatedOldVal, LoopMBB ],
2045 // [ %RotatedAltVal, UseAltMBB ]
2046 // %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
2047 // %Dest = CS %OldVal, %NewVal, Disp(%Base)
2049 // # fall through to DoneMMB
2051 BuildMI(MBB, DL, TII->get(SystemZ::PHI), RotatedNewVal)
2052 .addReg(RotatedOldVal).addMBB(LoopMBB)
2053 .addReg(RotatedAltVal).addMBB(UseAltMBB);
2055 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
2056 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
2057 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
2058 .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
2059 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2060 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
2061 MBB->addSuccessor(LoopMBB);
2062 MBB->addSuccessor(DoneMBB);
2064 MI->eraseFromParent();
2068 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_CMP_SWAPW
2071 SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr *MI,
2072 MachineBasicBlock *MBB) const {
2073 const SystemZInstrInfo *TII = TM.getInstrInfo();
2074 MachineFunction &MF = *MBB->getParent();
2075 MachineRegisterInfo &MRI = MF.getRegInfo();
2077 // Extract the operands. Base can be a register or a frame index.
2078 unsigned Dest = MI->getOperand(0).getReg();
2079 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
2080 int64_t Disp = MI->getOperand(2).getImm();
2081 unsigned OrigCmpVal = MI->getOperand(3).getReg();
2082 unsigned OrigSwapVal = MI->getOperand(4).getReg();
2083 unsigned BitShift = MI->getOperand(5).getReg();
2084 unsigned NegBitShift = MI->getOperand(6).getReg();
2085 int64_t BitSize = MI->getOperand(7).getImm();
2086 DebugLoc DL = MI->getDebugLoc();
2088 const TargetRegisterClass *RC = &SystemZ::GR32BitRegClass;
2090 // Get the right opcodes for the displacement.
2091 unsigned LOpcode = TII->getOpcodeForOffset(SystemZ::L, Disp);
2092 unsigned CSOpcode = TII->getOpcodeForOffset(SystemZ::CS, Disp);
2093 assert(LOpcode && CSOpcode && "Displacement out of range");
2095 // Create virtual registers for temporary results.
2096 unsigned OrigOldVal = MRI.createVirtualRegister(RC);
2097 unsigned OldVal = MRI.createVirtualRegister(RC);
2098 unsigned CmpVal = MRI.createVirtualRegister(RC);
2099 unsigned SwapVal = MRI.createVirtualRegister(RC);
2100 unsigned StoreVal = MRI.createVirtualRegister(RC);
2101 unsigned RetryOldVal = MRI.createVirtualRegister(RC);
2102 unsigned RetryCmpVal = MRI.createVirtualRegister(RC);
2103 unsigned RetrySwapVal = MRI.createVirtualRegister(RC);
2105 // Insert 2 basic blocks for the loop.
2106 MachineBasicBlock *StartMBB = MBB;
2107 MachineBasicBlock *DoneMBB = splitBlockAfter(MI, MBB);
2108 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
2109 MachineBasicBlock *SetMBB = emitBlockAfter(LoopMBB);
2113 // %OrigOldVal = L Disp(%Base)
2114 // # fall through to LoopMMB
2116 BuildMI(MBB, DL, TII->get(LOpcode), OrigOldVal)
2117 .addOperand(Base).addImm(Disp).addReg(0);
2118 MBB->addSuccessor(LoopMBB);
2121 // %OldVal = phi [ %OrigOldVal, EntryBB ], [ %RetryOldVal, SetMBB ]
2122 // %CmpVal = phi [ %OrigCmpVal, EntryBB ], [ %RetryCmpVal, SetMBB ]
2123 // %SwapVal = phi [ %OrigSwapVal, EntryBB ], [ %RetrySwapVal, SetMBB ]
2124 // %Dest = RLL %OldVal, BitSize(%BitShift)
2125 // ^^ The low BitSize bits contain the field
2127 // %RetryCmpVal = RISBG32 %CmpVal, %Dest, 32, 63-BitSize, 0
2128 // ^^ Replace the upper 32-BitSize bits of the
2129 // comparison value with those that we loaded,
2130 // so that we can use a full word comparison.
2131 // CR %Dest, %RetryCmpVal
2133 // # Fall through to SetMBB
2135 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
2136 .addReg(OrigOldVal).addMBB(StartMBB)
2137 .addReg(RetryOldVal).addMBB(SetMBB);
2138 BuildMI(MBB, DL, TII->get(SystemZ::PHI), CmpVal)
2139 .addReg(OrigCmpVal).addMBB(StartMBB)
2140 .addReg(RetryCmpVal).addMBB(SetMBB);
2141 BuildMI(MBB, DL, TII->get(SystemZ::PHI), SwapVal)
2142 .addReg(OrigSwapVal).addMBB(StartMBB)
2143 .addReg(RetrySwapVal).addMBB(SetMBB);
2144 BuildMI(MBB, DL, TII->get(SystemZ::RLL), Dest)
2145 .addReg(OldVal).addReg(BitShift).addImm(BitSize);
2146 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetryCmpVal)
2147 .addReg(CmpVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
2148 BuildMI(MBB, DL, TII->get(SystemZ::CR))
2149 .addReg(Dest).addReg(RetryCmpVal);
2150 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2151 .addImm(SystemZ::CCMASK_ICMP)
2152 .addImm(SystemZ::CCMASK_CMP_NE).addMBB(DoneMBB);
2153 MBB->addSuccessor(DoneMBB);
2154 MBB->addSuccessor(SetMBB);
2157 // %RetrySwapVal = RISBG32 %SwapVal, %Dest, 32, 63-BitSize, 0
2158 // ^^ Replace the upper 32-BitSize bits of the new
2159 // value with those that we loaded.
2160 // %StoreVal = RLL %RetrySwapVal, -BitSize(%NegBitShift)
2161 // ^^ Rotate the new field to its proper position.
2162 // %RetryOldVal = CS %Dest, %StoreVal, Disp(%Base)
2164 // # fall through to ExitMMB
2166 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetrySwapVal)
2167 .addReg(SwapVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
2168 BuildMI(MBB, DL, TII->get(SystemZ::RLL), StoreVal)
2169 .addReg(RetrySwapVal).addReg(NegBitShift).addImm(-BitSize);
2170 BuildMI(MBB, DL, TII->get(CSOpcode), RetryOldVal)
2171 .addReg(OldVal).addReg(StoreVal).addOperand(Base).addImm(Disp);
2172 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2173 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
2174 MBB->addSuccessor(LoopMBB);
2175 MBB->addSuccessor(DoneMBB);
2177 MI->eraseFromParent();
2181 // Emit an extension from a GR32 or GR64 to a GR128. ClearEven is true
2182 // if the high register of the GR128 value must be cleared or false if
2183 // it's "don't care". SubReg is subreg_odd32 when extending a GR32
2184 // and subreg_odd when extending a GR64.
2186 SystemZTargetLowering::emitExt128(MachineInstr *MI,
2187 MachineBasicBlock *MBB,
2188 bool ClearEven, unsigned SubReg) const {
2189 const SystemZInstrInfo *TII = TM.getInstrInfo();
2190 MachineFunction &MF = *MBB->getParent();
2191 MachineRegisterInfo &MRI = MF.getRegInfo();
2192 DebugLoc DL = MI->getDebugLoc();
2194 unsigned Dest = MI->getOperand(0).getReg();
2195 unsigned Src = MI->getOperand(1).getReg();
2196 unsigned In128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
2198 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::IMPLICIT_DEF), In128);
2200 unsigned NewIn128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
2201 unsigned Zero64 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
2203 BuildMI(*MBB, MI, DL, TII->get(SystemZ::LLILL), Zero64)
2205 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), NewIn128)
2206 .addReg(In128).addReg(Zero64).addImm(SystemZ::subreg_high);
2209 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dest)
2210 .addReg(In128).addReg(Src).addImm(SubReg);
2212 MI->eraseFromParent();
2217 SystemZTargetLowering::emitMVCWrapper(MachineInstr *MI,
2218 MachineBasicBlock *MBB) const {
2219 const SystemZInstrInfo *TII = TM.getInstrInfo();
2220 DebugLoc DL = MI->getDebugLoc();
2222 MachineOperand DestBase = MI->getOperand(0);
2223 uint64_t DestDisp = MI->getOperand(1).getImm();
2224 MachineOperand SrcBase = MI->getOperand(2);
2225 uint64_t SrcDisp = MI->getOperand(3).getImm();
2226 uint64_t Length = MI->getOperand(4).getImm();
2228 BuildMI(*MBB, MI, DL, TII->get(SystemZ::MVC))
2229 .addOperand(DestBase).addImm(DestDisp).addImm(Length)
2230 .addOperand(SrcBase).addImm(SrcDisp);
2232 MI->eraseFromParent();
2236 MachineBasicBlock *SystemZTargetLowering::
2237 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const {
2238 switch (MI->getOpcode()) {
2239 case SystemZ::Select32:
2240 case SystemZ::SelectF32:
2241 case SystemZ::Select64:
2242 case SystemZ::SelectF64:
2243 case SystemZ::SelectF128:
2244 return emitSelect(MI, MBB);
2246 case SystemZ::CondStore8_32:
2247 return emitCondStore(MI, MBB, SystemZ::STC32, 0, false);
2248 case SystemZ::CondStore8_32Inv:
2249 return emitCondStore(MI, MBB, SystemZ::STC32, 0, true);
2250 case SystemZ::CondStore16_32:
2251 return emitCondStore(MI, MBB, SystemZ::STH32, 0, false);
2252 case SystemZ::CondStore16_32Inv:
2253 return emitCondStore(MI, MBB, SystemZ::STH32, 0, true);
2254 case SystemZ::CondStore32_32:
2255 return emitCondStore(MI, MBB, SystemZ::ST32, SystemZ::STOC32, false);
2256 case SystemZ::CondStore32_32Inv:
2257 return emitCondStore(MI, MBB, SystemZ::ST32, SystemZ::STOC32, true);
2258 case SystemZ::CondStore8:
2259 return emitCondStore(MI, MBB, SystemZ::STC, 0, false);
2260 case SystemZ::CondStore8Inv:
2261 return emitCondStore(MI, MBB, SystemZ::STC, 0, true);
2262 case SystemZ::CondStore16:
2263 return emitCondStore(MI, MBB, SystemZ::STH, 0, false);
2264 case SystemZ::CondStore16Inv:
2265 return emitCondStore(MI, MBB, SystemZ::STH, 0, true);
2266 case SystemZ::CondStore32:
2267 return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, false);
2268 case SystemZ::CondStore32Inv:
2269 return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, true);
2270 case SystemZ::CondStore64:
2271 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, false);
2272 case SystemZ::CondStore64Inv:
2273 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, true);
2274 case SystemZ::CondStoreF32:
2275 return emitCondStore(MI, MBB, SystemZ::STE, 0, false);
2276 case SystemZ::CondStoreF32Inv:
2277 return emitCondStore(MI, MBB, SystemZ::STE, 0, true);
2278 case SystemZ::CondStoreF64:
2279 return emitCondStore(MI, MBB, SystemZ::STD, 0, false);
2280 case SystemZ::CondStoreF64Inv:
2281 return emitCondStore(MI, MBB, SystemZ::STD, 0, true);
2283 case SystemZ::AEXT128_64:
2284 return emitExt128(MI, MBB, false, SystemZ::subreg_low);
2285 case SystemZ::ZEXT128_32:
2286 return emitExt128(MI, MBB, true, SystemZ::subreg_low32);
2287 case SystemZ::ZEXT128_64:
2288 return emitExt128(MI, MBB, true, SystemZ::subreg_low);
2290 case SystemZ::ATOMIC_SWAPW:
2291 return emitAtomicLoadBinary(MI, MBB, 0, 0);
2292 case SystemZ::ATOMIC_SWAP_32:
2293 return emitAtomicLoadBinary(MI, MBB, 0, 32);
2294 case SystemZ::ATOMIC_SWAP_64:
2295 return emitAtomicLoadBinary(MI, MBB, 0, 64);
2297 case SystemZ::ATOMIC_LOADW_AR:
2298 return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 0);
2299 case SystemZ::ATOMIC_LOADW_AFI:
2300 return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 0);
2301 case SystemZ::ATOMIC_LOAD_AR:
2302 return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 32);
2303 case SystemZ::ATOMIC_LOAD_AHI:
2304 return emitAtomicLoadBinary(MI, MBB, SystemZ::AHI, 32);
2305 case SystemZ::ATOMIC_LOAD_AFI:
2306 return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 32);
2307 case SystemZ::ATOMIC_LOAD_AGR:
2308 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGR, 64);
2309 case SystemZ::ATOMIC_LOAD_AGHI:
2310 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGHI, 64);
2311 case SystemZ::ATOMIC_LOAD_AGFI:
2312 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGFI, 64);
2314 case SystemZ::ATOMIC_LOADW_SR:
2315 return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 0);
2316 case SystemZ::ATOMIC_LOAD_SR:
2317 return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 32);
2318 case SystemZ::ATOMIC_LOAD_SGR:
2319 return emitAtomicLoadBinary(MI, MBB, SystemZ::SGR, 64);
2321 case SystemZ::ATOMIC_LOADW_NR:
2322 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0);
2323 case SystemZ::ATOMIC_LOADW_NILH:
2324 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH32, 0);
2325 case SystemZ::ATOMIC_LOAD_NR:
2326 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32);
2327 case SystemZ::ATOMIC_LOAD_NILL32:
2328 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL32, 32);
2329 case SystemZ::ATOMIC_LOAD_NILH32:
2330 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH32, 32);
2331 case SystemZ::ATOMIC_LOAD_NILF32:
2332 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF32, 32);
2333 case SystemZ::ATOMIC_LOAD_NGR:
2334 return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64);
2335 case SystemZ::ATOMIC_LOAD_NILL:
2336 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 64);
2337 case SystemZ::ATOMIC_LOAD_NILH:
2338 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 64);
2339 case SystemZ::ATOMIC_LOAD_NIHL:
2340 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL, 64);
2341 case SystemZ::ATOMIC_LOAD_NIHH:
2342 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH, 64);
2343 case SystemZ::ATOMIC_LOAD_NILF:
2344 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 64);
2345 case SystemZ::ATOMIC_LOAD_NIHF:
2346 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF, 64);
2348 case SystemZ::ATOMIC_LOADW_OR:
2349 return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 0);
2350 case SystemZ::ATOMIC_LOADW_OILH:
2351 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH32, 0);
2352 case SystemZ::ATOMIC_LOAD_OR:
2353 return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 32);
2354 case SystemZ::ATOMIC_LOAD_OILL32:
2355 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL32, 32);
2356 case SystemZ::ATOMIC_LOAD_OILH32:
2357 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH32, 32);
2358 case SystemZ::ATOMIC_LOAD_OILF32:
2359 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF32, 32);
2360 case SystemZ::ATOMIC_LOAD_OGR:
2361 return emitAtomicLoadBinary(MI, MBB, SystemZ::OGR, 64);
2362 case SystemZ::ATOMIC_LOAD_OILL:
2363 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL, 64);
2364 case SystemZ::ATOMIC_LOAD_OILH:
2365 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 64);
2366 case SystemZ::ATOMIC_LOAD_OIHL:
2367 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHL, 64);
2368 case SystemZ::ATOMIC_LOAD_OIHH:
2369 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHH, 64);
2370 case SystemZ::ATOMIC_LOAD_OILF:
2371 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF, 64);
2372 case SystemZ::ATOMIC_LOAD_OIHF:
2373 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHF, 64);
2375 case SystemZ::ATOMIC_LOADW_XR:
2376 return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 0);
2377 case SystemZ::ATOMIC_LOADW_XILF:
2378 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF32, 0);
2379 case SystemZ::ATOMIC_LOAD_XR:
2380 return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 32);
2381 case SystemZ::ATOMIC_LOAD_XILF32:
2382 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF32, 32);
2383 case SystemZ::ATOMIC_LOAD_XGR:
2384 return emitAtomicLoadBinary(MI, MBB, SystemZ::XGR, 64);
2385 case SystemZ::ATOMIC_LOAD_XILF:
2386 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 64);
2387 case SystemZ::ATOMIC_LOAD_XIHF:
2388 return emitAtomicLoadBinary(MI, MBB, SystemZ::XIHF, 64);
2390 case SystemZ::ATOMIC_LOADW_NRi:
2391 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0, true);
2392 case SystemZ::ATOMIC_LOADW_NILHi:
2393 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH32, 0, true);
2394 case SystemZ::ATOMIC_LOAD_NRi:
2395 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32, true);
2396 case SystemZ::ATOMIC_LOAD_NILL32i:
2397 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL32, 32, true);
2398 case SystemZ::ATOMIC_LOAD_NILH32i:
2399 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH32, 32, true);
2400 case SystemZ::ATOMIC_LOAD_NILF32i:
2401 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF32, 32, true);
2402 case SystemZ::ATOMIC_LOAD_NGRi:
2403 return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64, true);
2404 case SystemZ::ATOMIC_LOAD_NILLi:
2405 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 64, true);
2406 case SystemZ::ATOMIC_LOAD_NILHi:
2407 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 64, true);
2408 case SystemZ::ATOMIC_LOAD_NIHLi:
2409 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL, 64, true);
2410 case SystemZ::ATOMIC_LOAD_NIHHi:
2411 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH, 64, true);
2412 case SystemZ::ATOMIC_LOAD_NILFi:
2413 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 64, true);
2414 case SystemZ::ATOMIC_LOAD_NIHFi:
2415 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF, 64, true);
2417 case SystemZ::ATOMIC_LOADW_MIN:
2418 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
2419 SystemZ::CCMASK_CMP_LE, 0);
2420 case SystemZ::ATOMIC_LOAD_MIN_32:
2421 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
2422 SystemZ::CCMASK_CMP_LE, 32);
2423 case SystemZ::ATOMIC_LOAD_MIN_64:
2424 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
2425 SystemZ::CCMASK_CMP_LE, 64);
2427 case SystemZ::ATOMIC_LOADW_MAX:
2428 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
2429 SystemZ::CCMASK_CMP_GE, 0);
2430 case SystemZ::ATOMIC_LOAD_MAX_32:
2431 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
2432 SystemZ::CCMASK_CMP_GE, 32);
2433 case SystemZ::ATOMIC_LOAD_MAX_64:
2434 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
2435 SystemZ::CCMASK_CMP_GE, 64);
2437 case SystemZ::ATOMIC_LOADW_UMIN:
2438 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
2439 SystemZ::CCMASK_CMP_LE, 0);
2440 case SystemZ::ATOMIC_LOAD_UMIN_32:
2441 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
2442 SystemZ::CCMASK_CMP_LE, 32);
2443 case SystemZ::ATOMIC_LOAD_UMIN_64:
2444 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
2445 SystemZ::CCMASK_CMP_LE, 64);
2447 case SystemZ::ATOMIC_LOADW_UMAX:
2448 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
2449 SystemZ::CCMASK_CMP_GE, 0);
2450 case SystemZ::ATOMIC_LOAD_UMAX_32:
2451 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
2452 SystemZ::CCMASK_CMP_GE, 32);
2453 case SystemZ::ATOMIC_LOAD_UMAX_64:
2454 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
2455 SystemZ::CCMASK_CMP_GE, 64);
2457 case SystemZ::ATOMIC_CMP_SWAPW:
2458 return emitAtomicCmpSwapW(MI, MBB);
2459 case SystemZ::MVCWrapper:
2460 return emitMVCWrapper(MI, MBB);
2462 llvm_unreachable("Unexpected instr type to insert");