1 //===-- SystemZISelLowering.cpp - SystemZ DAG lowering implementation -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SystemZTargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "systemz-lower"
16 #include "SystemZISelLowering.h"
17 #include "SystemZCallingConv.h"
18 #include "SystemZConstantPoolValue.h"
19 #include "SystemZMachineFunctionInfo.h"
20 #include "SystemZTargetMachine.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 // Classify VT as either 32 or 64 bit.
29 static bool is32Bit(EVT VT) {
30 switch (VT.getSimpleVT().SimpleTy) {
36 llvm_unreachable("Unsupported type");
40 // Return a version of MachineOperand that can be safely used before the
42 static MachineOperand earlyUseOperand(MachineOperand Op) {
48 SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm)
49 : TargetLowering(tm, new TargetLoweringObjectFileELF()),
50 Subtarget(*tm.getSubtargetImpl()), TM(tm) {
51 MVT PtrVT = getPointerTy();
53 // Set up the register classes.
54 addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass);
55 addRegisterClass(MVT::i64, &SystemZ::GR64BitRegClass);
56 addRegisterClass(MVT::f32, &SystemZ::FP32BitRegClass);
57 addRegisterClass(MVT::f64, &SystemZ::FP64BitRegClass);
58 addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass);
60 // Compute derived properties from the register classes
61 computeRegisterProperties();
63 // Set up special registers.
64 setExceptionPointerRegister(SystemZ::R6D);
65 setExceptionSelectorRegister(SystemZ::R7D);
66 setStackPointerRegisterToSaveRestore(SystemZ::R15D);
68 // TODO: It may be better to default to latency-oriented scheduling, however
69 // LLVM's current latency-oriented scheduler can't handle physreg definitions
70 // such as SystemZ has with CC, so set this to the register-pressure
71 // scheduler, because it can.
72 setSchedulingPreference(Sched::RegPressure);
74 setBooleanContents(ZeroOrOneBooleanContent);
75 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
77 // Instructions are strings of 2-byte aligned 2-byte values.
78 setMinFunctionAlignment(2);
80 // Handle operations that are handled in a similar way for all types.
81 for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
82 I <= MVT::LAST_FP_VALUETYPE;
84 MVT VT = MVT::SimpleValueType(I);
85 if (isTypeLegal(VT)) {
86 // Expand SETCC(X, Y, COND) into SELECT_CC(X, Y, 1, 0, COND).
87 setOperationAction(ISD::SETCC, VT, Expand);
89 // Expand SELECT(C, A, B) into SELECT_CC(X, 0, A, B, NE).
90 setOperationAction(ISD::SELECT, VT, Expand);
92 // Lower SELECT_CC and BR_CC into separate comparisons and branches.
93 setOperationAction(ISD::SELECT_CC, VT, Custom);
94 setOperationAction(ISD::BR_CC, VT, Custom);
98 // Expand jump table branches as address arithmetic followed by an
100 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
102 // Expand BRCOND into a BR_CC (see above).
103 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
105 // Handle integer types.
106 for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
107 I <= MVT::LAST_INTEGER_VALUETYPE;
109 MVT VT = MVT::SimpleValueType(I);
110 if (isTypeLegal(VT)) {
111 // Expand individual DIV and REMs into DIVREMs.
112 setOperationAction(ISD::SDIV, VT, Expand);
113 setOperationAction(ISD::UDIV, VT, Expand);
114 setOperationAction(ISD::SREM, VT, Expand);
115 setOperationAction(ISD::UREM, VT, Expand);
116 setOperationAction(ISD::SDIVREM, VT, Custom);
117 setOperationAction(ISD::UDIVREM, VT, Custom);
119 // Expand ATOMIC_LOAD and ATOMIC_STORE using ATOMIC_CMP_SWAP.
120 // FIXME: probably much too conservative.
121 setOperationAction(ISD::ATOMIC_LOAD, VT, Expand);
122 setOperationAction(ISD::ATOMIC_STORE, VT, Expand);
124 // No special instructions for these.
125 setOperationAction(ISD::CTPOP, VT, Expand);
126 setOperationAction(ISD::CTTZ, VT, Expand);
127 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
128 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
129 setOperationAction(ISD::ROTR, VT, Expand);
131 // Use *MUL_LOHI where possible and a wider multiplication otherwise.
132 setOperationAction(ISD::MULHS, VT, Expand);
133 setOperationAction(ISD::MULHU, VT, Expand);
135 // We have instructions for signed but not unsigned FP conversion.
136 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
140 // Type legalization will convert 8- and 16-bit atomic operations into
141 // forms that operate on i32s (but still keeping the original memory VT).
142 // Lower them into full i32 operations.
143 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Custom);
144 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Custom);
145 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
146 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Custom);
147 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Custom);
148 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Custom);
149 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Custom);
150 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Custom);
151 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Custom);
152 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Custom);
153 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Custom);
154 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
156 // We have instructions for signed but not unsigned FP conversion.
157 // Handle unsigned 32-bit types as signed 64-bit types.
158 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote);
159 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
161 // We have native support for a 64-bit CTLZ, via FLOGR.
162 setOperationAction(ISD::CTLZ, MVT::i32, Promote);
163 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
165 // Give LowerOperation the chance to replace 64-bit ORs with subregs.
166 setOperationAction(ISD::OR, MVT::i64, Custom);
168 // The architecture has 32-bit SMUL_LOHI and UMUL_LOHI (MR and MLR),
169 // but they aren't really worth using. There is no 64-bit SMUL_LOHI,
170 // but there is a 64-bit UMUL_LOHI: MLGR.
171 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
172 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
173 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
174 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Custom);
176 // FIXME: Can we support these natively?
177 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
178 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
179 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
181 // We have native instructions for i8, i16 and i32 extensions, but not i1.
182 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
183 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
184 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
185 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
187 // Handle the various types of symbolic address.
188 setOperationAction(ISD::ConstantPool, PtrVT, Custom);
189 setOperationAction(ISD::GlobalAddress, PtrVT, Custom);
190 setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom);
191 setOperationAction(ISD::BlockAddress, PtrVT, Custom);
192 setOperationAction(ISD::JumpTable, PtrVT, Custom);
194 // We need to handle dynamic allocations specially because of the
195 // 160-byte area at the bottom of the stack.
196 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
198 // Use custom expanders so that we can force the function to use
200 setOperationAction(ISD::STACKSAVE, MVT::Other, Custom);
201 setOperationAction(ISD::STACKRESTORE, MVT::Other, Custom);
203 // Handle floating-point types.
204 for (unsigned I = MVT::FIRST_FP_VALUETYPE;
205 I <= MVT::LAST_FP_VALUETYPE;
207 MVT VT = MVT::SimpleValueType(I);
208 if (isTypeLegal(VT)) {
209 // We can use FI for FRINT.
210 setOperationAction(ISD::FRINT, VT, Legal);
212 // No special instructions for these.
213 setOperationAction(ISD::FSIN, VT, Expand);
214 setOperationAction(ISD::FCOS, VT, Expand);
215 setOperationAction(ISD::FREM, VT, Expand);
219 // We have fused multiply-addition for f32 and f64 but not f128.
220 setOperationAction(ISD::FMA, MVT::f32, Legal);
221 setOperationAction(ISD::FMA, MVT::f64, Legal);
222 setOperationAction(ISD::FMA, MVT::f128, Expand);
224 // Needed so that we don't try to implement f128 constant loads using
225 // a load-and-extend of a f80 constant (in cases where the constant
226 // would fit in an f80).
227 setLoadExtAction(ISD::EXTLOAD, MVT::f80, Expand);
229 // Floating-point truncation and stores need to be done separately.
230 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
231 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
232 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
234 // We have 64-bit FPR<->GPR moves, but need special handling for
236 setOperationAction(ISD::BITCAST, MVT::i32, Custom);
237 setOperationAction(ISD::BITCAST, MVT::f32, Custom);
239 // VASTART and VACOPY need to deal with the SystemZ-specific varargs
240 // structure, but VAEND is a no-op.
241 setOperationAction(ISD::VASTART, MVT::Other, Custom);
242 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
243 setOperationAction(ISD::VAEND, MVT::Other, Expand);
245 // We want to use MVC in preference to even a single load/store pair.
246 MaxStoresPerMemcpy = 0;
247 MaxStoresPerMemcpyOptSize = 0;
249 // The main memset sequence is a byte store followed by an MVC.
250 // Two STC or MV..I stores win over that, but the kind of fused stores
251 // generated by target-independent code don't when the byte value is
252 // variable. E.g. "STC <reg>;MHI <reg>,257;STH <reg>" is not better
253 // than "STC;MVC". Handle the choice in target-specific code instead.
254 MaxStoresPerMemset = 0;
255 MaxStoresPerMemsetOptSize = 0;
259 SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
260 VT = VT.getScalarType();
265 switch (VT.getSimpleVT().SimpleTy) {
278 bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
279 // We can load zero using LZ?R and negative zero using LZ?R;LC?BR.
280 return Imm.isZero() || Imm.isNegZero();
283 bool SystemZTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
285 // Unaligned accesses should never be slower than the expanded version.
286 // We check specifically for aligned accesses in the few cases where
287 // they are required.
293 bool SystemZTargetLowering::isLegalAddressingMode(const AddrMode &AM,
295 // Punt on globals for now, although they can be used in limited
296 // RELATIVE LONG cases.
300 // Require a 20-bit signed offset.
301 if (!isInt<20>(AM.BaseOffs))
304 // Indexing is OK but no scale factor can be applied.
305 return AM.Scale == 0 || AM.Scale == 1;
308 //===----------------------------------------------------------------------===//
309 // Inline asm support
310 //===----------------------------------------------------------------------===//
312 TargetLowering::ConstraintType
313 SystemZTargetLowering::getConstraintType(const std::string &Constraint) const {
314 if (Constraint.size() == 1) {
315 switch (Constraint[0]) {
316 case 'a': // Address register
317 case 'd': // Data register (equivalent to 'r')
318 case 'f': // Floating-point register
319 case 'r': // General-purpose register
320 return C_RegisterClass;
322 case 'Q': // Memory with base and unsigned 12-bit displacement
323 case 'R': // Likewise, plus an index
324 case 'S': // Memory with base and signed 20-bit displacement
325 case 'T': // Likewise, plus an index
326 case 'm': // Equivalent to 'T'.
329 case 'I': // Unsigned 8-bit constant
330 case 'J': // Unsigned 12-bit constant
331 case 'K': // Signed 16-bit constant
332 case 'L': // Signed 20-bit displacement (on all targets we support)
333 case 'M': // 0x7fffffff
340 return TargetLowering::getConstraintType(Constraint);
343 TargetLowering::ConstraintWeight SystemZTargetLowering::
344 getSingleConstraintMatchWeight(AsmOperandInfo &info,
345 const char *constraint) const {
346 ConstraintWeight weight = CW_Invalid;
347 Value *CallOperandVal = info.CallOperandVal;
348 // If we don't have a value, we can't do a match,
349 // but allow it at the lowest weight.
350 if (CallOperandVal == NULL)
352 Type *type = CallOperandVal->getType();
353 // Look at the constraint type.
354 switch (*constraint) {
356 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
359 case 'a': // Address register
360 case 'd': // Data register (equivalent to 'r')
361 case 'r': // General-purpose register
362 if (CallOperandVal->getType()->isIntegerTy())
363 weight = CW_Register;
366 case 'f': // Floating-point register
367 if (type->isFloatingPointTy())
368 weight = CW_Register;
371 case 'I': // Unsigned 8-bit constant
372 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
373 if (isUInt<8>(C->getZExtValue()))
374 weight = CW_Constant;
377 case 'J': // Unsigned 12-bit constant
378 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
379 if (isUInt<12>(C->getZExtValue()))
380 weight = CW_Constant;
383 case 'K': // Signed 16-bit constant
384 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
385 if (isInt<16>(C->getSExtValue()))
386 weight = CW_Constant;
389 case 'L': // Signed 20-bit displacement (on all targets we support)
390 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
391 if (isInt<20>(C->getSExtValue()))
392 weight = CW_Constant;
395 case 'M': // 0x7fffffff
396 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
397 if (C->getZExtValue() == 0x7fffffff)
398 weight = CW_Constant;
404 // Parse a "{tNNN}" register constraint for which the register type "t"
405 // has already been verified. MC is the class associated with "t" and
406 // Map maps 0-based register numbers to LLVM register numbers.
407 static std::pair<unsigned, const TargetRegisterClass *>
408 parseRegisterNumber(const std::string &Constraint,
409 const TargetRegisterClass *RC, const unsigned *Map) {
410 assert(*(Constraint.end()-1) == '}' && "Missing '}'");
411 if (isdigit(Constraint[2])) {
412 std::string Suffix(Constraint.data() + 2, Constraint.size() - 2);
413 unsigned Index = atoi(Suffix.c_str());
414 if (Index < 16 && Map[Index])
415 return std::make_pair(Map[Index], RC);
417 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
420 std::pair<unsigned, const TargetRegisterClass *> SystemZTargetLowering::
421 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const {
422 if (Constraint.size() == 1) {
423 // GCC Constraint Letters
424 switch (Constraint[0]) {
426 case 'd': // Data register (equivalent to 'r')
427 case 'r': // General-purpose register
429 return std::make_pair(0U, &SystemZ::GR64BitRegClass);
430 else if (VT == MVT::i128)
431 return std::make_pair(0U, &SystemZ::GR128BitRegClass);
432 return std::make_pair(0U, &SystemZ::GR32BitRegClass);
434 case 'a': // Address register
436 return std::make_pair(0U, &SystemZ::ADDR64BitRegClass);
437 else if (VT == MVT::i128)
438 return std::make_pair(0U, &SystemZ::ADDR128BitRegClass);
439 return std::make_pair(0U, &SystemZ::ADDR32BitRegClass);
441 case 'f': // Floating-point register
443 return std::make_pair(0U, &SystemZ::FP64BitRegClass);
444 else if (VT == MVT::f128)
445 return std::make_pair(0U, &SystemZ::FP128BitRegClass);
446 return std::make_pair(0U, &SystemZ::FP32BitRegClass);
449 if (Constraint[0] == '{') {
450 // We need to override the default register parsing for GPRs and FPRs
451 // because the interpretation depends on VT. The internal names of
452 // the registers are also different from the external names
453 // (F0D and F0S instead of F0, etc.).
454 if (Constraint[1] == 'r') {
456 return parseRegisterNumber(Constraint, &SystemZ::GR32BitRegClass,
457 SystemZMC::GR32Regs);
459 return parseRegisterNumber(Constraint, &SystemZ::GR128BitRegClass,
460 SystemZMC::GR128Regs);
461 return parseRegisterNumber(Constraint, &SystemZ::GR64BitRegClass,
462 SystemZMC::GR64Regs);
464 if (Constraint[1] == 'f') {
466 return parseRegisterNumber(Constraint, &SystemZ::FP32BitRegClass,
467 SystemZMC::FP32Regs);
469 return parseRegisterNumber(Constraint, &SystemZ::FP128BitRegClass,
470 SystemZMC::FP128Regs);
471 return parseRegisterNumber(Constraint, &SystemZ::FP64BitRegClass,
472 SystemZMC::FP64Regs);
475 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
478 void SystemZTargetLowering::
479 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
480 std::vector<SDValue> &Ops,
481 SelectionDAG &DAG) const {
482 // Only support length 1 constraints for now.
483 if (Constraint.length() == 1) {
484 switch (Constraint[0]) {
485 case 'I': // Unsigned 8-bit constant
486 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
487 if (isUInt<8>(C->getZExtValue()))
488 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
492 case 'J': // Unsigned 12-bit constant
493 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
494 if (isUInt<12>(C->getZExtValue()))
495 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
499 case 'K': // Signed 16-bit constant
500 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
501 if (isInt<16>(C->getSExtValue()))
502 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
506 case 'L': // Signed 20-bit displacement (on all targets we support)
507 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
508 if (isInt<20>(C->getSExtValue()))
509 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
513 case 'M': // 0x7fffffff
514 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
515 if (C->getZExtValue() == 0x7fffffff)
516 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
521 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
524 //===----------------------------------------------------------------------===//
525 // Calling conventions
526 //===----------------------------------------------------------------------===//
528 #include "SystemZGenCallingConv.inc"
530 // Value is a value that has been passed to us in the location described by VA
531 // (and so has type VA.getLocVT()). Convert Value to VA.getValVT(), chaining
532 // any loads onto Chain.
533 static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDLoc DL,
534 CCValAssign &VA, SDValue Chain,
536 // If the argument has been promoted from a smaller type, insert an
537 // assertion to capture this.
538 if (VA.getLocInfo() == CCValAssign::SExt)
539 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value,
540 DAG.getValueType(VA.getValVT()));
541 else if (VA.getLocInfo() == CCValAssign::ZExt)
542 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value,
543 DAG.getValueType(VA.getValVT()));
546 Value = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Value);
547 else if (VA.getLocInfo() == CCValAssign::Indirect)
548 Value = DAG.getLoad(VA.getValVT(), DL, Chain, Value,
549 MachinePointerInfo(), false, false, false, 0);
551 assert(VA.getLocInfo() == CCValAssign::Full && "Unsupported getLocInfo");
555 // Value is a value of type VA.getValVT() that we need to copy into
556 // the location described by VA. Return a copy of Value converted to
557 // VA.getValVT(). The caller is responsible for handling indirect values.
558 static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDLoc DL,
559 CCValAssign &VA, SDValue Value) {
560 switch (VA.getLocInfo()) {
561 case CCValAssign::SExt:
562 return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value);
563 case CCValAssign::ZExt:
564 return DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Value);
565 case CCValAssign::AExt:
566 return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value);
567 case CCValAssign::Full:
570 llvm_unreachable("Unhandled getLocInfo()");
574 SDValue SystemZTargetLowering::
575 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
576 const SmallVectorImpl<ISD::InputArg> &Ins,
577 SDLoc DL, SelectionDAG &DAG,
578 SmallVectorImpl<SDValue> &InVals) const {
579 MachineFunction &MF = DAG.getMachineFunction();
580 MachineFrameInfo *MFI = MF.getFrameInfo();
581 MachineRegisterInfo &MRI = MF.getRegInfo();
582 SystemZMachineFunctionInfo *FuncInfo =
583 MF.getInfo<SystemZMachineFunctionInfo>();
584 const SystemZFrameLowering *TFL =
585 static_cast<const SystemZFrameLowering *>(TM.getFrameLowering());
587 // Assign locations to all of the incoming arguments.
588 SmallVector<CCValAssign, 16> ArgLocs;
589 CCState CCInfo(CallConv, IsVarArg, MF, TM, ArgLocs, *DAG.getContext());
590 CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ);
592 unsigned NumFixedGPRs = 0;
593 unsigned NumFixedFPRs = 0;
594 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
596 CCValAssign &VA = ArgLocs[I];
597 EVT LocVT = VA.getLocVT();
599 // Arguments passed in registers
600 const TargetRegisterClass *RC;
601 switch (LocVT.getSimpleVT().SimpleTy) {
603 // Integers smaller than i64 should be promoted to i64.
604 llvm_unreachable("Unexpected argument type");
607 RC = &SystemZ::GR32BitRegClass;
611 RC = &SystemZ::GR64BitRegClass;
615 RC = &SystemZ::FP32BitRegClass;
619 RC = &SystemZ::FP64BitRegClass;
623 unsigned VReg = MRI.createVirtualRegister(RC);
624 MRI.addLiveIn(VA.getLocReg(), VReg);
625 ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
627 assert(VA.isMemLoc() && "Argument not register or memory");
629 // Create the frame index object for this incoming parameter.
630 int FI = MFI->CreateFixedObject(LocVT.getSizeInBits() / 8,
631 VA.getLocMemOffset(), true);
633 // Create the SelectionDAG nodes corresponding to a load
634 // from this parameter. Unpromoted ints and floats are
635 // passed as right-justified 8-byte values.
636 EVT PtrVT = getPointerTy();
637 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
638 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
639 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4));
640 ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN,
641 MachinePointerInfo::getFixedStack(FI),
642 false, false, false, 0);
645 // Convert the value of the argument register into the value that's
647 InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, ArgValue));
651 // Save the number of non-varargs registers for later use by va_start, etc.
652 FuncInfo->setVarArgsFirstGPR(NumFixedGPRs);
653 FuncInfo->setVarArgsFirstFPR(NumFixedFPRs);
655 // Likewise the address (in the form of a frame index) of where the
656 // first stack vararg would be. The 1-byte size here is arbitrary.
657 int64_t StackSize = CCInfo.getNextStackOffset();
658 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize, true));
660 // ...and a similar frame index for the caller-allocated save area
661 // that will be used to store the incoming registers.
662 int64_t RegSaveOffset = TFL->getOffsetOfLocalArea();
663 unsigned RegSaveIndex = MFI->CreateFixedObject(1, RegSaveOffset, true);
664 FuncInfo->setRegSaveFrameIndex(RegSaveIndex);
666 // Store the FPR varargs in the reserved frame slots. (We store the
667 // GPRs as part of the prologue.)
668 if (NumFixedFPRs < SystemZ::NumArgFPRs) {
669 SDValue MemOps[SystemZ::NumArgFPRs];
670 for (unsigned I = NumFixedFPRs; I < SystemZ::NumArgFPRs; ++I) {
671 unsigned Offset = TFL->getRegSpillOffset(SystemZ::ArgFPRs[I]);
672 int FI = MFI->CreateFixedObject(8, RegSaveOffset + Offset, true);
673 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
674 unsigned VReg = MF.addLiveIn(SystemZ::ArgFPRs[I],
675 &SystemZ::FP64BitRegClass);
676 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f64);
677 MemOps[I] = DAG.getStore(ArgValue.getValue(1), DL, ArgValue, FIN,
678 MachinePointerInfo::getFixedStack(FI),
682 // Join the stores, which are independent of one another.
683 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
684 &MemOps[NumFixedFPRs],
685 SystemZ::NumArgFPRs - NumFixedFPRs);
693 SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
694 SmallVectorImpl<SDValue> &InVals) const {
695 SelectionDAG &DAG = CLI.DAG;
697 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
698 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
699 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
700 SDValue Chain = CLI.Chain;
701 SDValue Callee = CLI.Callee;
702 bool &isTailCall = CLI.IsTailCall;
703 CallingConv::ID CallConv = CLI.CallConv;
704 bool IsVarArg = CLI.IsVarArg;
705 MachineFunction &MF = DAG.getMachineFunction();
706 EVT PtrVT = getPointerTy();
708 // SystemZ target does not yet support tail call optimization.
711 // Analyze the operands of the call, assigning locations to each operand.
712 SmallVector<CCValAssign, 16> ArgLocs;
713 CCState ArgCCInfo(CallConv, IsVarArg, MF, TM, ArgLocs, *DAG.getContext());
714 ArgCCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
716 // Get a count of how many bytes are to be pushed on the stack.
717 unsigned NumBytes = ArgCCInfo.getNextStackOffset();
719 // Mark the start of the call.
720 Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes, PtrVT, true),
723 // Copy argument values to their designated locations.
724 SmallVector<std::pair<unsigned, SDValue>, 9> RegsToPass;
725 SmallVector<SDValue, 8> MemOpChains;
727 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
728 CCValAssign &VA = ArgLocs[I];
729 SDValue ArgValue = OutVals[I];
731 if (VA.getLocInfo() == CCValAssign::Indirect) {
732 // Store the argument in a stack slot and pass its address.
733 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
734 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
735 MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, SpillSlot,
736 MachinePointerInfo::getFixedStack(FI),
738 ArgValue = SpillSlot;
740 ArgValue = convertValVTToLocVT(DAG, DL, VA, ArgValue);
743 // Queue up the argument copies and emit them at the end.
744 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));
746 assert(VA.isMemLoc() && "Argument not register or memory");
748 // Work out the address of the stack slot. Unpromoted ints and
749 // floats are passed as right-justified 8-byte values.
750 if (!StackPtr.getNode())
751 StackPtr = DAG.getCopyFromReg(Chain, DL, SystemZ::R15D, PtrVT);
752 unsigned Offset = SystemZMC::CallFrameSize + VA.getLocMemOffset();
753 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
755 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
756 DAG.getIntPtrConstant(Offset));
759 MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, Address,
760 MachinePointerInfo(),
765 // Join the stores, which are independent of one another.
766 if (!MemOpChains.empty())
767 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
768 &MemOpChains[0], MemOpChains.size());
770 // Build a sequence of copy-to-reg nodes, chained and glued together.
772 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {
773 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
774 RegsToPass[I].second, Glue);
775 Glue = Chain.getValue(1);
778 // Accept direct calls by converting symbolic call addresses to the
779 // associated Target* opcodes.
780 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
781 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT);
782 Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
783 } else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
784 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT);
785 Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
788 // The first call operand is the chain and the second is the target address.
789 SmallVector<SDValue, 8> Ops;
790 Ops.push_back(Chain);
791 Ops.push_back(Callee);
793 // Add argument registers to the end of the list so that they are
794 // known live into the call.
795 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I)
796 Ops.push_back(DAG.getRegister(RegsToPass[I].first,
797 RegsToPass[I].second.getValueType()));
799 // Glue the call to the argument copies, if any.
804 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
805 Chain = DAG.getNode(SystemZISD::CALL, DL, NodeTys, &Ops[0], Ops.size());
806 Glue = Chain.getValue(1);
808 // Mark the end of the call, which is glued to the call itself.
809 Chain = DAG.getCALLSEQ_END(Chain,
810 DAG.getConstant(NumBytes, PtrVT, true),
811 DAG.getConstant(0, PtrVT, true),
813 Glue = Chain.getValue(1);
815 // Assign locations to each value returned by this call.
816 SmallVector<CCValAssign, 16> RetLocs;
817 CCState RetCCInfo(CallConv, IsVarArg, MF, TM, RetLocs, *DAG.getContext());
818 RetCCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ);
820 // Copy all of the result registers out of their specified physreg.
821 for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
822 CCValAssign &VA = RetLocs[I];
824 // Copy the value out, gluing the copy to the end of the call sequence.
825 SDValue RetValue = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(),
826 VA.getLocVT(), Glue);
827 Chain = RetValue.getValue(1);
828 Glue = RetValue.getValue(2);
830 // Convert the value of the return register into the value that's
832 InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, RetValue));
839 SystemZTargetLowering::LowerReturn(SDValue Chain,
840 CallingConv::ID CallConv, bool IsVarArg,
841 const SmallVectorImpl<ISD::OutputArg> &Outs,
842 const SmallVectorImpl<SDValue> &OutVals,
843 SDLoc DL, SelectionDAG &DAG) const {
844 MachineFunction &MF = DAG.getMachineFunction();
846 // Assign locations to each returned value.
847 SmallVector<CCValAssign, 16> RetLocs;
848 CCState RetCCInfo(CallConv, IsVarArg, MF, TM, RetLocs, *DAG.getContext());
849 RetCCInfo.AnalyzeReturn(Outs, RetCC_SystemZ);
851 // Quick exit for void returns
853 return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, Chain);
855 // Copy the result values into the output registers.
857 SmallVector<SDValue, 4> RetOps;
858 RetOps.push_back(Chain);
859 for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
860 CCValAssign &VA = RetLocs[I];
861 SDValue RetValue = OutVals[I];
863 // Make the return register live on exit.
864 assert(VA.isRegLoc() && "Can only return in registers!");
866 // Promote the value as required.
867 RetValue = convertValVTToLocVT(DAG, DL, VA, RetValue);
869 // Chain and glue the copies together.
870 unsigned Reg = VA.getLocReg();
871 Chain = DAG.getCopyToReg(Chain, DL, Reg, RetValue, Glue);
872 Glue = Chain.getValue(1);
873 RetOps.push_back(DAG.getRegister(Reg, VA.getLocVT()));
876 // Update chain and glue.
879 RetOps.push_back(Glue);
881 return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other,
882 RetOps.data(), RetOps.size());
885 // CC is a comparison that will be implemented using an integer or
886 // floating-point comparison. Return the condition code mask for
887 // a branch on true. In the integer case, CCMASK_CMP_UO is set for
888 // unsigned comparisons and clear for signed ones. In the floating-point
889 // case, CCMASK_CMP_UO has its normal mask meaning (unordered).
890 static unsigned CCMaskForCondCode(ISD::CondCode CC) {
892 case ISD::SET##X: return SystemZ::CCMASK_CMP_##X; \
893 case ISD::SETO##X: return SystemZ::CCMASK_CMP_##X; \
894 case ISD::SETU##X: return SystemZ::CCMASK_CMP_UO | SystemZ::CCMASK_CMP_##X
898 llvm_unreachable("Invalid integer condition!");
907 case ISD::SETO: return SystemZ::CCMASK_CMP_O;
908 case ISD::SETUO: return SystemZ::CCMASK_CMP_UO;
913 // If a comparison described by IsUnsigned, CCMask, CmpOp0 and CmpOp1
914 // can be converted to a comparison against zero, adjust the operands
916 static void adjustZeroCmp(SelectionDAG &DAG, bool &IsUnsigned,
917 SDValue &CmpOp0, SDValue &CmpOp1,
922 ConstantSDNode *ConstOp1 = dyn_cast<ConstantSDNode>(CmpOp1.getNode());
926 int64_t Value = ConstOp1->getSExtValue();
927 if ((Value == -1 && CCMask == SystemZ::CCMASK_CMP_GT) ||
928 (Value == -1 && CCMask == SystemZ::CCMASK_CMP_LE) ||
929 (Value == 1 && CCMask == SystemZ::CCMASK_CMP_LT) ||
930 (Value == 1 && CCMask == SystemZ::CCMASK_CMP_GE)) {
931 CCMask ^= SystemZ::CCMASK_CMP_EQ;
932 CmpOp1 = DAG.getConstant(0, CmpOp1.getValueType());
936 // If a comparison described by IsUnsigned, CCMask, CmpOp0 and CmpOp1
937 // is suitable for CLI(Y), CHHSI or CLHHSI, adjust the operands as necessary.
938 static void adjustSubwordCmp(SelectionDAG &DAG, bool &IsUnsigned,
939 SDValue &CmpOp0, SDValue &CmpOp1,
941 // For us to make any changes, it must a comparison between a single-use
942 // load and a constant.
943 if (!CmpOp0.hasOneUse() ||
944 CmpOp0.getOpcode() != ISD::LOAD ||
945 CmpOp1.getOpcode() != ISD::Constant)
948 // We must have an 8- or 16-bit load.
949 LoadSDNode *Load = cast<LoadSDNode>(CmpOp0);
950 unsigned NumBits = Load->getMemoryVT().getStoreSizeInBits();
951 if (NumBits != 8 && NumBits != 16)
954 // The load must be an extending one and the constant must be within the
955 // range of the unextended value.
956 ConstantSDNode *Constant = cast<ConstantSDNode>(CmpOp1);
957 uint64_t Value = Constant->getZExtValue();
958 uint64_t Mask = (1 << NumBits) - 1;
959 if (Load->getExtensionType() == ISD::SEXTLOAD) {
960 int64_t SignedValue = Constant->getSExtValue();
961 if (uint64_t(SignedValue) + (1ULL << (NumBits - 1)) > Mask)
963 // Unsigned comparison between two sign-extended values is equivalent
964 // to unsigned comparison between two zero-extended values.
967 else if (CCMask == SystemZ::CCMASK_CMP_EQ ||
968 CCMask == SystemZ::CCMASK_CMP_NE)
969 // Any choice of IsUnsigned is OK for equality comparisons.
970 // We could use either CHHSI or CLHHSI for 16-bit comparisons,
971 // but since we use CLHHSI for zero extensions, it seems better
972 // to be consistent and do the same here.
973 Value &= Mask, IsUnsigned = true;
974 else if (NumBits == 8) {
975 // Try to treat the comparison as unsigned, so that we can use CLI.
976 // Adjust CCMask and Value as necessary.
977 if (Value == 0 && CCMask == SystemZ::CCMASK_CMP_LT)
978 // Test whether the high bit of the byte is set.
979 Value = 127, CCMask = SystemZ::CCMASK_CMP_GT, IsUnsigned = true;
980 else if (Value == 0 && CCMask == SystemZ::CCMASK_CMP_GE)
981 // Test whether the high bit of the byte is clear.
982 Value = 128, CCMask = SystemZ::CCMASK_CMP_LT, IsUnsigned = true;
984 // No instruction exists for this combination.
987 } else if (Load->getExtensionType() == ISD::ZEXTLOAD) {
990 // Signed comparison between two zero-extended values is equivalent
991 // to unsigned comparison.
996 // Make sure that the first operand is an i32 of the right extension type.
997 ISD::LoadExtType ExtType = IsUnsigned ? ISD::ZEXTLOAD : ISD::SEXTLOAD;
998 if (CmpOp0.getValueType() != MVT::i32 ||
999 Load->getExtensionType() != ExtType)
1000 CmpOp0 = DAG.getExtLoad(ExtType, SDLoc(Load), MVT::i32,
1001 Load->getChain(), Load->getBasePtr(),
1002 Load->getPointerInfo(), Load->getMemoryVT(),
1003 Load->isVolatile(), Load->isNonTemporal(),
1004 Load->getAlignment());
1006 // Make sure that the second operand is an i32 with the right value.
1007 if (CmpOp1.getValueType() != MVT::i32 ||
1008 Value != Constant->getZExtValue())
1009 CmpOp1 = DAG.getConstant(Value, MVT::i32);
1012 // Return true if a comparison described by CCMask, CmpOp0 and CmpOp1
1013 // is an equality comparison that is better implemented using unsigned
1014 // rather than signed comparison instructions.
1015 static bool preferUnsignedComparison(SelectionDAG &DAG, SDValue CmpOp0,
1016 SDValue CmpOp1, unsigned CCMask) {
1017 // The test must be for equality or inequality.
1018 if (CCMask != SystemZ::CCMASK_CMP_EQ && CCMask != SystemZ::CCMASK_CMP_NE)
1021 if (CmpOp1.getOpcode() == ISD::Constant) {
1022 uint64_t Value = cast<ConstantSDNode>(CmpOp1)->getSExtValue();
1024 // If we're comparing with memory, prefer unsigned comparisons for
1025 // values that are in the unsigned 16-bit range but not the signed
1026 // 16-bit range. We want to use CLFHSI and CLGHSI.
1027 if (CmpOp0.hasOneUse() &&
1028 ISD::isNormalLoad(CmpOp0.getNode()) &&
1029 (Value >= 32768 && Value < 65536))
1032 // Use unsigned comparisons for values that are in the CLGFI range
1033 // but not in the CGFI range.
1034 if (CmpOp0.getValueType() == MVT::i64 && (Value >> 31) == 1)
1040 // Prefer CL for zero-extended loads.
1041 if (CmpOp1.getOpcode() == ISD::ZERO_EXTEND ||
1042 ISD::isZEXTLoad(CmpOp1.getNode()))
1045 // ...and for "in-register" zero extensions.
1046 if (CmpOp1.getOpcode() == ISD::AND && CmpOp1.getValueType() == MVT::i64) {
1047 SDValue Mask = CmpOp1.getOperand(1);
1048 if (Mask.getOpcode() == ISD::Constant &&
1049 cast<ConstantSDNode>(Mask)->getZExtValue() == 0xffffffff)
1056 // Return a target node that compares CmpOp0 with CmpOp1 and stores a
1057 // 2-bit result in CC. Set CCValid to the CCMASK_* of all possible
1058 // 2-bit results and CCMask to the subset of those results that are
1059 // associated with Cond.
1060 static SDValue emitCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1,
1061 ISD::CondCode Cond, unsigned &CCValid,
1063 bool IsUnsigned = false;
1064 CCMask = CCMaskForCondCode(Cond);
1065 if (CmpOp0.getValueType().isFloatingPoint())
1066 CCValid = SystemZ::CCMASK_FCMP;
1068 IsUnsigned = CCMask & SystemZ::CCMASK_CMP_UO;
1069 CCValid = SystemZ::CCMASK_ICMP;
1071 adjustZeroCmp(DAG, IsUnsigned, CmpOp0, CmpOp1, CCMask);
1072 adjustSubwordCmp(DAG, IsUnsigned, CmpOp0, CmpOp1, CCMask);
1073 if (preferUnsignedComparison(DAG, CmpOp0, CmpOp1, CCMask))
1078 return DAG.getNode((IsUnsigned ? SystemZISD::UCMP : SystemZISD::CMP),
1079 DL, MVT::Glue, CmpOp0, CmpOp1);
1082 // Lower a binary operation that produces two VT results, one in each
1083 // half of a GR128 pair. Op0 and Op1 are the VT operands to the operation,
1084 // Extend extends Op0 to a GR128, and Opcode performs the GR128 operation
1085 // on the extended Op0 and (unextended) Op1. Store the even register result
1086 // in Even and the odd register result in Odd.
1087 static void lowerGR128Binary(SelectionDAG &DAG, SDLoc DL, EVT VT,
1088 unsigned Extend, unsigned Opcode,
1089 SDValue Op0, SDValue Op1,
1090 SDValue &Even, SDValue &Odd) {
1091 SDNode *In128 = DAG.getMachineNode(Extend, DL, MVT::Untyped, Op0);
1092 SDValue Result = DAG.getNode(Opcode, DL, MVT::Untyped,
1093 SDValue(In128, 0), Op1);
1094 bool Is32Bit = is32Bit(VT);
1095 SDValue SubReg0 = DAG.getTargetConstant(SystemZ::even128(Is32Bit), VT);
1096 SDValue SubReg1 = DAG.getTargetConstant(SystemZ::odd128(Is32Bit), VT);
1097 SDNode *Reg0 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL,
1098 VT, Result, SubReg0);
1099 SDNode *Reg1 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL,
1100 VT, Result, SubReg1);
1101 Even = SDValue(Reg0, 0);
1102 Odd = SDValue(Reg1, 0);
1105 SDValue SystemZTargetLowering::lowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
1106 SDValue Chain = Op.getOperand(0);
1107 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1108 SDValue CmpOp0 = Op.getOperand(2);
1109 SDValue CmpOp1 = Op.getOperand(3);
1110 SDValue Dest = Op.getOperand(4);
1113 unsigned CCValid, CCMask;
1114 SDValue Flags = emitCmp(DAG, CmpOp0, CmpOp1, CC, CCValid, CCMask);
1115 return DAG.getNode(SystemZISD::BR_CCMASK, DL, Op.getValueType(),
1116 Chain, DAG.getConstant(CCValid, MVT::i32),
1117 DAG.getConstant(CCMask, MVT::i32), Dest, Flags);
1120 SDValue SystemZTargetLowering::lowerSELECT_CC(SDValue Op,
1121 SelectionDAG &DAG) const {
1122 SDValue CmpOp0 = Op.getOperand(0);
1123 SDValue CmpOp1 = Op.getOperand(1);
1124 SDValue TrueOp = Op.getOperand(2);
1125 SDValue FalseOp = Op.getOperand(3);
1126 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1129 unsigned CCValid, CCMask;
1130 SDValue Flags = emitCmp(DAG, CmpOp0, CmpOp1, CC, CCValid, CCMask);
1132 SmallVector<SDValue, 5> Ops;
1133 Ops.push_back(TrueOp);
1134 Ops.push_back(FalseOp);
1135 Ops.push_back(DAG.getConstant(CCValid, MVT::i32));
1136 Ops.push_back(DAG.getConstant(CCMask, MVT::i32));
1137 Ops.push_back(Flags);
1139 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1140 return DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VTs, &Ops[0], Ops.size());
1143 SDValue SystemZTargetLowering::lowerGlobalAddress(GlobalAddressSDNode *Node,
1144 SelectionDAG &DAG) const {
1146 const GlobalValue *GV = Node->getGlobal();
1147 int64_t Offset = Node->getOffset();
1148 EVT PtrVT = getPointerTy();
1149 Reloc::Model RM = TM.getRelocationModel();
1150 CodeModel::Model CM = TM.getCodeModel();
1153 if (Subtarget.isPC32DBLSymbol(GV, RM, CM)) {
1154 // Make sure that the offset is aligned to a halfword. If it isn't,
1155 // create an "anchor" at the previous 12-bit boundary.
1156 // FIXME check whether there is a better way of handling this.
1158 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
1159 Offset & ~uint64_t(0xfff));
1162 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Offset);
1165 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1167 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, SystemZII::MO_GOT);
1168 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1169 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
1170 MachinePointerInfo::getGOT(), false, false, false, 0);
1173 // If there was a non-zero offset that we didn't fold, create an explicit
1176 Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result,
1177 DAG.getConstant(Offset, PtrVT));
1182 SDValue SystemZTargetLowering::lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
1183 SelectionDAG &DAG) const {
1185 const GlobalValue *GV = Node->getGlobal();
1186 EVT PtrVT = getPointerTy();
1187 TLSModel::Model model = TM.getTLSModel(GV);
1189 if (model != TLSModel::LocalExec)
1190 llvm_unreachable("only local-exec TLS mode supported");
1192 // The high part of the thread pointer is in access register 0.
1193 SDValue TPHi = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
1194 DAG.getConstant(0, MVT::i32));
1195 TPHi = DAG.getNode(ISD::ANY_EXTEND, DL, PtrVT, TPHi);
1197 // The low part of the thread pointer is in access register 1.
1198 SDValue TPLo = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
1199 DAG.getConstant(1, MVT::i32));
1200 TPLo = DAG.getNode(ISD::ZERO_EXTEND, DL, PtrVT, TPLo);
1202 // Merge them into a single 64-bit address.
1203 SDValue TPHiShifted = DAG.getNode(ISD::SHL, DL, PtrVT, TPHi,
1204 DAG.getConstant(32, PtrVT));
1205 SDValue TP = DAG.getNode(ISD::OR, DL, PtrVT, TPHiShifted, TPLo);
1207 // Get the offset of GA from the thread pointer.
1208 SystemZConstantPoolValue *CPV =
1209 SystemZConstantPoolValue::Create(GV, SystemZCP::NTPOFF);
1211 // Force the offset into the constant pool and load it from there.
1212 SDValue CPAddr = DAG.getConstantPool(CPV, PtrVT, 8);
1213 SDValue Offset = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(),
1214 CPAddr, MachinePointerInfo::getConstantPool(),
1215 false, false, false, 0);
1217 // Add the base and offset together.
1218 return DAG.getNode(ISD::ADD, DL, PtrVT, TP, Offset);
1221 SDValue SystemZTargetLowering::lowerBlockAddress(BlockAddressSDNode *Node,
1222 SelectionDAG &DAG) const {
1224 const BlockAddress *BA = Node->getBlockAddress();
1225 int64_t Offset = Node->getOffset();
1226 EVT PtrVT = getPointerTy();
1228 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset);
1229 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1233 SDValue SystemZTargetLowering::lowerJumpTable(JumpTableSDNode *JT,
1234 SelectionDAG &DAG) const {
1236 EVT PtrVT = getPointerTy();
1237 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1239 // Use LARL to load the address of the table.
1240 return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1243 SDValue SystemZTargetLowering::lowerConstantPool(ConstantPoolSDNode *CP,
1244 SelectionDAG &DAG) const {
1246 EVT PtrVT = getPointerTy();
1249 if (CP->isMachineConstantPoolEntry())
1250 Result = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1251 CP->getAlignment());
1253 Result = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1254 CP->getAlignment(), CP->getOffset());
1256 // Use LARL to load the address of the constant pool entry.
1257 return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1260 SDValue SystemZTargetLowering::lowerBITCAST(SDValue Op,
1261 SelectionDAG &DAG) const {
1263 SDValue In = Op.getOperand(0);
1264 EVT InVT = In.getValueType();
1265 EVT ResVT = Op.getValueType();
1267 SDValue SubReg32 = DAG.getTargetConstant(SystemZ::subreg_32bit, MVT::i64);
1268 SDValue Shift32 = DAG.getConstant(32, MVT::i64);
1269 if (InVT == MVT::i32 && ResVT == MVT::f32) {
1270 SDValue In64 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, In);
1271 SDValue Shift = DAG.getNode(ISD::SHL, DL, MVT::i64, In64, Shift32);
1272 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::f64, Shift);
1273 SDNode *Out = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL,
1274 MVT::f32, Out64, SubReg32);
1275 return SDValue(Out, 0);
1277 if (InVT == MVT::f32 && ResVT == MVT::i32) {
1278 SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::f64);
1279 SDNode *In64 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL,
1280 MVT::f64, SDValue(U64, 0), In, SubReg32);
1281 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::i64, SDValue(In64, 0));
1282 SDValue Shift = DAG.getNode(ISD::SRL, DL, MVT::i64, Out64, Shift32);
1283 SDValue Out = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Shift);
1286 llvm_unreachable("Unexpected bitcast combination");
1289 SDValue SystemZTargetLowering::lowerVASTART(SDValue Op,
1290 SelectionDAG &DAG) const {
1291 MachineFunction &MF = DAG.getMachineFunction();
1292 SystemZMachineFunctionInfo *FuncInfo =
1293 MF.getInfo<SystemZMachineFunctionInfo>();
1294 EVT PtrVT = getPointerTy();
1296 SDValue Chain = Op.getOperand(0);
1297 SDValue Addr = Op.getOperand(1);
1298 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1301 // The initial values of each field.
1302 const unsigned NumFields = 4;
1303 SDValue Fields[NumFields] = {
1304 DAG.getConstant(FuncInfo->getVarArgsFirstGPR(), PtrVT),
1305 DAG.getConstant(FuncInfo->getVarArgsFirstFPR(), PtrVT),
1306 DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT),
1307 DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT)
1310 // Store each field into its respective slot.
1311 SDValue MemOps[NumFields];
1312 unsigned Offset = 0;
1313 for (unsigned I = 0; I < NumFields; ++I) {
1314 SDValue FieldAddr = Addr;
1316 FieldAddr = DAG.getNode(ISD::ADD, DL, PtrVT, FieldAddr,
1317 DAG.getIntPtrConstant(Offset));
1318 MemOps[I] = DAG.getStore(Chain, DL, Fields[I], FieldAddr,
1319 MachinePointerInfo(SV, Offset),
1323 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps, NumFields);
1326 SDValue SystemZTargetLowering::lowerVACOPY(SDValue Op,
1327 SelectionDAG &DAG) const {
1328 SDValue Chain = Op.getOperand(0);
1329 SDValue DstPtr = Op.getOperand(1);
1330 SDValue SrcPtr = Op.getOperand(2);
1331 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
1332 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
1335 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, DAG.getIntPtrConstant(32),
1336 /*Align*/8, /*isVolatile*/false, /*AlwaysInline*/false,
1337 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
1340 SDValue SystemZTargetLowering::
1341 lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
1342 SDValue Chain = Op.getOperand(0);
1343 SDValue Size = Op.getOperand(1);
1346 unsigned SPReg = getStackPointerRegisterToSaveRestore();
1348 // Get a reference to the stack pointer.
1349 SDValue OldSP = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i64);
1351 // Get the new stack pointer value.
1352 SDValue NewSP = DAG.getNode(ISD::SUB, DL, MVT::i64, OldSP, Size);
1354 // Copy the new stack pointer back.
1355 Chain = DAG.getCopyToReg(Chain, DL, SPReg, NewSP);
1357 // The allocated data lives above the 160 bytes allocated for the standard
1358 // frame, plus any outgoing stack arguments. We don't know how much that
1359 // amounts to yet, so emit a special ADJDYNALLOC placeholder.
1360 SDValue ArgAdjust = DAG.getNode(SystemZISD::ADJDYNALLOC, DL, MVT::i64);
1361 SDValue Result = DAG.getNode(ISD::ADD, DL, MVT::i64, NewSP, ArgAdjust);
1363 SDValue Ops[2] = { Result, Chain };
1364 return DAG.getMergeValues(Ops, 2, DL);
1367 SDValue SystemZTargetLowering::lowerUMUL_LOHI(SDValue Op,
1368 SelectionDAG &DAG) const {
1369 EVT VT = Op.getValueType();
1371 assert(!is32Bit(VT) && "Only support 64-bit UMUL_LOHI");
1373 // UMUL_LOHI64 returns the low result in the odd register and the high
1374 // result in the even register. UMUL_LOHI is defined to return the
1375 // low half first, so the results are in reverse order.
1377 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
1378 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
1379 return DAG.getMergeValues(Ops, 2, DL);
1382 SDValue SystemZTargetLowering::lowerSDIVREM(SDValue Op,
1383 SelectionDAG &DAG) const {
1384 SDValue Op0 = Op.getOperand(0);
1385 SDValue Op1 = Op.getOperand(1);
1386 EVT VT = Op.getValueType();
1390 // We use DSGF for 32-bit division.
1392 Op0 = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op0);
1393 Opcode = SystemZISD::SDIVREM32;
1394 } else if (DAG.ComputeNumSignBits(Op1) > 32) {
1395 Op1 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op1);
1396 Opcode = SystemZISD::SDIVREM32;
1398 Opcode = SystemZISD::SDIVREM64;
1400 // DSG(F) takes a 64-bit dividend, so the even register in the GR128
1401 // input is "don't care". The instruction returns the remainder in
1402 // the even register and the quotient in the odd register.
1404 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, Opcode,
1405 Op0, Op1, Ops[1], Ops[0]);
1406 return DAG.getMergeValues(Ops, 2, DL);
1409 SDValue SystemZTargetLowering::lowerUDIVREM(SDValue Op,
1410 SelectionDAG &DAG) const {
1411 EVT VT = Op.getValueType();
1414 // DL(G) uses a double-width dividend, so we need to clear the even
1415 // register in the GR128 input. The instruction returns the remainder
1416 // in the even register and the quotient in the odd register.
1419 lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_32, SystemZISD::UDIVREM32,
1420 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
1422 lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_64, SystemZISD::UDIVREM64,
1423 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
1424 return DAG.getMergeValues(Ops, 2, DL);
1427 SDValue SystemZTargetLowering::lowerOR(SDValue Op, SelectionDAG &DAG) const {
1428 assert(Op.getValueType() == MVT::i64 && "Should be 64-bit operation");
1430 // Get the known-zero masks for each operand.
1431 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1) };
1432 APInt KnownZero[2], KnownOne[2];
1433 DAG.ComputeMaskedBits(Ops[0], KnownZero[0], KnownOne[0]);
1434 DAG.ComputeMaskedBits(Ops[1], KnownZero[1], KnownOne[1]);
1436 // See if the upper 32 bits of one operand and the lower 32 bits of the
1437 // other are known zero. They are the low and high operands respectively.
1438 uint64_t Masks[] = { KnownZero[0].getZExtValue(),
1439 KnownZero[1].getZExtValue() };
1441 if ((Masks[0] >> 32) == 0xffffffff && uint32_t(Masks[1]) == 0xffffffff)
1443 else if ((Masks[1] >> 32) == 0xffffffff && uint32_t(Masks[0]) == 0xffffffff)
1448 SDValue LowOp = Ops[Low];
1449 SDValue HighOp = Ops[High];
1451 // If the high part is a constant, we're better off using IILH.
1452 if (HighOp.getOpcode() == ISD::Constant)
1455 // If the low part is a constant that is outside the range of LHI,
1456 // then we're better off using IILF.
1457 if (LowOp.getOpcode() == ISD::Constant) {
1458 int64_t Value = int32_t(cast<ConstantSDNode>(LowOp)->getZExtValue());
1459 if (!isInt<16>(Value))
1463 // Check whether the high part is an AND that doesn't change the
1464 // high 32 bits and just masks out low bits. We can skip it if so.
1465 if (HighOp.getOpcode() == ISD::AND &&
1466 HighOp.getOperand(1).getOpcode() == ISD::Constant) {
1467 ConstantSDNode *MaskNode = cast<ConstantSDNode>(HighOp.getOperand(1));
1468 uint64_t Mask = MaskNode->getZExtValue() | Masks[High];
1469 if ((Mask >> 32) == 0xffffffff)
1470 HighOp = HighOp.getOperand(0);
1473 // Take advantage of the fact that all GR32 operations only change the
1474 // low 32 bits by truncating Low to an i32 and inserting it directly
1475 // using a subreg. The interesting cases are those where the truncation
1478 SDValue Low32 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, LowOp);
1479 SDValue SubReg32 = DAG.getTargetConstant(SystemZ::subreg_32bit, MVT::i64);
1480 SDNode *Result = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL,
1481 MVT::i64, HighOp, Low32, SubReg32);
1482 return SDValue(Result, 0);
1485 // Op is an 8-, 16-bit or 32-bit ATOMIC_LOAD_* operation. Lower the first
1486 // two into the fullword ATOMIC_LOADW_* operation given by Opcode.
1487 SDValue SystemZTargetLowering::lowerATOMIC_LOAD(SDValue Op,
1489 unsigned Opcode) const {
1490 AtomicSDNode *Node = cast<AtomicSDNode>(Op.getNode());
1492 // 32-bit operations need no code outside the main loop.
1493 EVT NarrowVT = Node->getMemoryVT();
1494 EVT WideVT = MVT::i32;
1495 if (NarrowVT == WideVT)
1498 int64_t BitSize = NarrowVT.getSizeInBits();
1499 SDValue ChainIn = Node->getChain();
1500 SDValue Addr = Node->getBasePtr();
1501 SDValue Src2 = Node->getVal();
1502 MachineMemOperand *MMO = Node->getMemOperand();
1504 EVT PtrVT = Addr.getValueType();
1506 // Convert atomic subtracts of constants into additions.
1507 if (Opcode == SystemZISD::ATOMIC_LOADW_SUB)
1508 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Src2)) {
1509 Opcode = SystemZISD::ATOMIC_LOADW_ADD;
1510 Src2 = DAG.getConstant(-Const->getSExtValue(), Src2.getValueType());
1513 // Get the address of the containing word.
1514 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
1515 DAG.getConstant(-4, PtrVT));
1517 // Get the number of bits that the word must be rotated left in order
1518 // to bring the field to the top bits of a GR32.
1519 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
1520 DAG.getConstant(3, PtrVT));
1521 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
1523 // Get the complementing shift amount, for rotating a field in the top
1524 // bits back to its proper position.
1525 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
1526 DAG.getConstant(0, WideVT), BitShift);
1528 // Extend the source operand to 32 bits and prepare it for the inner loop.
1529 // ATOMIC_SWAPW uses RISBG to rotate the field left, but all other
1530 // operations require the source to be shifted in advance. (This shift
1531 // can be folded if the source is constant.) For AND and NAND, the lower
1532 // bits must be set, while for other opcodes they should be left clear.
1533 if (Opcode != SystemZISD::ATOMIC_SWAPW)
1534 Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2,
1535 DAG.getConstant(32 - BitSize, WideVT));
1536 if (Opcode == SystemZISD::ATOMIC_LOADW_AND ||
1537 Opcode == SystemZISD::ATOMIC_LOADW_NAND)
1538 Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2,
1539 DAG.getConstant(uint32_t(-1) >> BitSize, WideVT));
1541 // Construct the ATOMIC_LOADW_* node.
1542 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
1543 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift,
1544 DAG.getConstant(BitSize, WideVT) };
1545 SDValue AtomicOp = DAG.getMemIntrinsicNode(Opcode, DL, VTList, Ops,
1546 array_lengthof(Ops),
1549 // Rotate the result of the final CS so that the field is in the lower
1550 // bits of a GR32, then truncate it.
1551 SDValue ResultShift = DAG.getNode(ISD::ADD, DL, WideVT, BitShift,
1552 DAG.getConstant(BitSize, WideVT));
1553 SDValue Result = DAG.getNode(ISD::ROTL, DL, WideVT, AtomicOp, ResultShift);
1555 SDValue RetOps[2] = { Result, AtomicOp.getValue(1) };
1556 return DAG.getMergeValues(RetOps, 2, DL);
1559 // Node is an 8- or 16-bit ATOMIC_CMP_SWAP operation. Lower the first two
1560 // into a fullword ATOMIC_CMP_SWAPW operation.
1561 SDValue SystemZTargetLowering::lowerATOMIC_CMP_SWAP(SDValue Op,
1562 SelectionDAG &DAG) const {
1563 AtomicSDNode *Node = cast<AtomicSDNode>(Op.getNode());
1565 // We have native support for 32-bit compare and swap.
1566 EVT NarrowVT = Node->getMemoryVT();
1567 EVT WideVT = MVT::i32;
1568 if (NarrowVT == WideVT)
1571 int64_t BitSize = NarrowVT.getSizeInBits();
1572 SDValue ChainIn = Node->getOperand(0);
1573 SDValue Addr = Node->getOperand(1);
1574 SDValue CmpVal = Node->getOperand(2);
1575 SDValue SwapVal = Node->getOperand(3);
1576 MachineMemOperand *MMO = Node->getMemOperand();
1578 EVT PtrVT = Addr.getValueType();
1580 // Get the address of the containing word.
1581 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
1582 DAG.getConstant(-4, PtrVT));
1584 // Get the number of bits that the word must be rotated left in order
1585 // to bring the field to the top bits of a GR32.
1586 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
1587 DAG.getConstant(3, PtrVT));
1588 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
1590 // Get the complementing shift amount, for rotating a field in the top
1591 // bits back to its proper position.
1592 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
1593 DAG.getConstant(0, WideVT), BitShift);
1595 // Construct the ATOMIC_CMP_SWAPW node.
1596 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
1597 SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift,
1598 NegBitShift, DAG.getConstant(BitSize, WideVT) };
1599 SDValue AtomicOp = DAG.getMemIntrinsicNode(SystemZISD::ATOMIC_CMP_SWAPW, DL,
1600 VTList, Ops, array_lengthof(Ops),
1605 SDValue SystemZTargetLowering::lowerSTACKSAVE(SDValue Op,
1606 SelectionDAG &DAG) const {
1607 MachineFunction &MF = DAG.getMachineFunction();
1608 MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
1609 return DAG.getCopyFromReg(Op.getOperand(0), SDLoc(Op),
1610 SystemZ::R15D, Op.getValueType());
1613 SDValue SystemZTargetLowering::lowerSTACKRESTORE(SDValue Op,
1614 SelectionDAG &DAG) const {
1615 MachineFunction &MF = DAG.getMachineFunction();
1616 MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
1617 return DAG.getCopyToReg(Op.getOperand(0), SDLoc(Op),
1618 SystemZ::R15D, Op.getOperand(1));
1621 SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
1622 SelectionDAG &DAG) const {
1623 switch (Op.getOpcode()) {
1625 return lowerBR_CC(Op, DAG);
1626 case ISD::SELECT_CC:
1627 return lowerSELECT_CC(Op, DAG);
1628 case ISD::GlobalAddress:
1629 return lowerGlobalAddress(cast<GlobalAddressSDNode>(Op), DAG);
1630 case ISD::GlobalTLSAddress:
1631 return lowerGlobalTLSAddress(cast<GlobalAddressSDNode>(Op), DAG);
1632 case ISD::BlockAddress:
1633 return lowerBlockAddress(cast<BlockAddressSDNode>(Op), DAG);
1634 case ISD::JumpTable:
1635 return lowerJumpTable(cast<JumpTableSDNode>(Op), DAG);
1636 case ISD::ConstantPool:
1637 return lowerConstantPool(cast<ConstantPoolSDNode>(Op), DAG);
1639 return lowerBITCAST(Op, DAG);
1641 return lowerVASTART(Op, DAG);
1643 return lowerVACOPY(Op, DAG);
1644 case ISD::DYNAMIC_STACKALLOC:
1645 return lowerDYNAMIC_STACKALLOC(Op, DAG);
1646 case ISD::UMUL_LOHI:
1647 return lowerUMUL_LOHI(Op, DAG);
1649 return lowerSDIVREM(Op, DAG);
1651 return lowerUDIVREM(Op, DAG);
1653 return lowerOR(Op, DAG);
1654 case ISD::ATOMIC_SWAP:
1655 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_SWAPW);
1656 case ISD::ATOMIC_LOAD_ADD:
1657 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_ADD);
1658 case ISD::ATOMIC_LOAD_SUB:
1659 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_SUB);
1660 case ISD::ATOMIC_LOAD_AND:
1661 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_AND);
1662 case ISD::ATOMIC_LOAD_OR:
1663 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_OR);
1664 case ISD::ATOMIC_LOAD_XOR:
1665 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_XOR);
1666 case ISD::ATOMIC_LOAD_NAND:
1667 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_NAND);
1668 case ISD::ATOMIC_LOAD_MIN:
1669 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_MIN);
1670 case ISD::ATOMIC_LOAD_MAX:
1671 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_MAX);
1672 case ISD::ATOMIC_LOAD_UMIN:
1673 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_UMIN);
1674 case ISD::ATOMIC_LOAD_UMAX:
1675 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_UMAX);
1676 case ISD::ATOMIC_CMP_SWAP:
1677 return lowerATOMIC_CMP_SWAP(Op, DAG);
1678 case ISD::STACKSAVE:
1679 return lowerSTACKSAVE(Op, DAG);
1680 case ISD::STACKRESTORE:
1681 return lowerSTACKRESTORE(Op, DAG);
1683 llvm_unreachable("Unexpected node to lower");
1687 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
1688 #define OPCODE(NAME) case SystemZISD::NAME: return "SystemZISD::" #NAME
1692 OPCODE(PCREL_WRAPPER);
1696 OPCODE(SELECT_CCMASK);
1697 OPCODE(ADJDYNALLOC);
1698 OPCODE(EXTRACT_ACCESS);
1699 OPCODE(UMUL_LOHI64);
1707 OPCODE(SEARCH_STRING);
1709 OPCODE(ATOMIC_SWAPW);
1710 OPCODE(ATOMIC_LOADW_ADD);
1711 OPCODE(ATOMIC_LOADW_SUB);
1712 OPCODE(ATOMIC_LOADW_AND);
1713 OPCODE(ATOMIC_LOADW_OR);
1714 OPCODE(ATOMIC_LOADW_XOR);
1715 OPCODE(ATOMIC_LOADW_NAND);
1716 OPCODE(ATOMIC_LOADW_MIN);
1717 OPCODE(ATOMIC_LOADW_MAX);
1718 OPCODE(ATOMIC_LOADW_UMIN);
1719 OPCODE(ATOMIC_LOADW_UMAX);
1720 OPCODE(ATOMIC_CMP_SWAPW);
1726 //===----------------------------------------------------------------------===//
1728 //===----------------------------------------------------------------------===//
1730 // Create a new basic block after MBB.
1731 static MachineBasicBlock *emitBlockAfter(MachineBasicBlock *MBB) {
1732 MachineFunction &MF = *MBB->getParent();
1733 MachineBasicBlock *NewMBB = MF.CreateMachineBasicBlock(MBB->getBasicBlock());
1734 MF.insert(llvm::next(MachineFunction::iterator(MBB)), NewMBB);
1738 // Split MBB after MI and return the new block (the one that contains
1739 // instructions after MI).
1740 static MachineBasicBlock *splitBlockAfter(MachineInstr *MI,
1741 MachineBasicBlock *MBB) {
1742 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
1743 NewMBB->splice(NewMBB->begin(), MBB,
1744 llvm::next(MachineBasicBlock::iterator(MI)),
1746 NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
1750 // Implement EmitInstrWithCustomInserter for pseudo Select* instruction MI.
1752 SystemZTargetLowering::emitSelect(MachineInstr *MI,
1753 MachineBasicBlock *MBB) const {
1754 const SystemZInstrInfo *TII = TM.getInstrInfo();
1756 unsigned DestReg = MI->getOperand(0).getReg();
1757 unsigned TrueReg = MI->getOperand(1).getReg();
1758 unsigned FalseReg = MI->getOperand(2).getReg();
1759 unsigned CCValid = MI->getOperand(3).getImm();
1760 unsigned CCMask = MI->getOperand(4).getImm();
1761 DebugLoc DL = MI->getDebugLoc();
1763 MachineBasicBlock *StartMBB = MBB;
1764 MachineBasicBlock *JoinMBB = splitBlockAfter(MI, MBB);
1765 MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
1768 // BRC CCMask, JoinMBB
1769 // # fallthrough to FalseMBB
1771 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
1772 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
1773 MBB->addSuccessor(JoinMBB);
1774 MBB->addSuccessor(FalseMBB);
1777 // # fallthrough to JoinMBB
1779 MBB->addSuccessor(JoinMBB);
1782 // %Result = phi [ %FalseReg, FalseMBB ], [ %TrueReg, StartMBB ]
1785 BuildMI(*MBB, MBB->begin(), DL, TII->get(SystemZ::PHI), DestReg)
1786 .addReg(TrueReg).addMBB(StartMBB)
1787 .addReg(FalseReg).addMBB(FalseMBB);
1789 MI->eraseFromParent();
1793 // Implement EmitInstrWithCustomInserter for pseudo CondStore* instruction MI.
1794 // StoreOpcode is the store to use and Invert says whether the store should
1795 // happen when the condition is false rather than true. If a STORE ON
1796 // CONDITION is available, STOCOpcode is its opcode, otherwise it is 0.
1798 SystemZTargetLowering::emitCondStore(MachineInstr *MI,
1799 MachineBasicBlock *MBB,
1800 unsigned StoreOpcode, unsigned STOCOpcode,
1801 bool Invert) const {
1802 const SystemZInstrInfo *TII = TM.getInstrInfo();
1804 unsigned SrcReg = MI->getOperand(0).getReg();
1805 MachineOperand Base = MI->getOperand(1);
1806 int64_t Disp = MI->getOperand(2).getImm();
1807 unsigned IndexReg = MI->getOperand(3).getReg();
1808 unsigned CCValid = MI->getOperand(4).getImm();
1809 unsigned CCMask = MI->getOperand(5).getImm();
1810 DebugLoc DL = MI->getDebugLoc();
1812 StoreOpcode = TII->getOpcodeForOffset(StoreOpcode, Disp);
1814 // Use STOCOpcode if possible. We could use different store patterns in
1815 // order to avoid matching the index register, but the performance trade-offs
1816 // might be more complicated in that case.
1817 if (STOCOpcode && !IndexReg && TM.getSubtargetImpl()->hasLoadStoreOnCond()) {
1820 BuildMI(*MBB, MI, DL, TII->get(STOCOpcode))
1821 .addReg(SrcReg).addOperand(Base).addImm(Disp)
1822 .addImm(CCValid).addImm(CCMask);
1823 MI->eraseFromParent();
1827 // Get the condition needed to branch around the store.
1831 MachineBasicBlock *StartMBB = MBB;
1832 MachineBasicBlock *JoinMBB = splitBlockAfter(MI, MBB);
1833 MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
1836 // BRC CCMask, JoinMBB
1837 // # fallthrough to FalseMBB
1839 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
1840 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
1841 MBB->addSuccessor(JoinMBB);
1842 MBB->addSuccessor(FalseMBB);
1845 // store %SrcReg, %Disp(%Index,%Base)
1846 // # fallthrough to JoinMBB
1848 BuildMI(MBB, DL, TII->get(StoreOpcode))
1849 .addReg(SrcReg).addOperand(Base).addImm(Disp).addReg(IndexReg);
1850 MBB->addSuccessor(JoinMBB);
1852 MI->eraseFromParent();
1856 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_LOAD{,W}_*
1857 // or ATOMIC_SWAP{,W} instruction MI. BinOpcode is the instruction that
1858 // performs the binary operation elided by "*", or 0 for ATOMIC_SWAP{,W}.
1859 // BitSize is the width of the field in bits, or 0 if this is a partword
1860 // ATOMIC_LOADW_* or ATOMIC_SWAPW instruction, in which case the bitsize
1861 // is one of the operands. Invert says whether the field should be
1862 // inverted after performing BinOpcode (e.g. for NAND).
1864 SystemZTargetLowering::emitAtomicLoadBinary(MachineInstr *MI,
1865 MachineBasicBlock *MBB,
1868 bool Invert) const {
1869 const SystemZInstrInfo *TII = TM.getInstrInfo();
1870 MachineFunction &MF = *MBB->getParent();
1871 MachineRegisterInfo &MRI = MF.getRegInfo();
1872 bool IsSubWord = (BitSize < 32);
1874 // Extract the operands. Base can be a register or a frame index.
1875 // Src2 can be a register or immediate.
1876 unsigned Dest = MI->getOperand(0).getReg();
1877 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
1878 int64_t Disp = MI->getOperand(2).getImm();
1879 MachineOperand Src2 = earlyUseOperand(MI->getOperand(3));
1880 unsigned BitShift = (IsSubWord ? MI->getOperand(4).getReg() : 0);
1881 unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0);
1882 DebugLoc DL = MI->getDebugLoc();
1884 BitSize = MI->getOperand(6).getImm();
1886 // Subword operations use 32-bit registers.
1887 const TargetRegisterClass *RC = (BitSize <= 32 ?
1888 &SystemZ::GR32BitRegClass :
1889 &SystemZ::GR64BitRegClass);
1890 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
1891 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
1893 // Get the right opcodes for the displacement.
1894 LOpcode = TII->getOpcodeForOffset(LOpcode, Disp);
1895 CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
1896 assert(LOpcode && CSOpcode && "Displacement out of range");
1898 // Create virtual registers for temporary results.
1899 unsigned OrigVal = MRI.createVirtualRegister(RC);
1900 unsigned OldVal = MRI.createVirtualRegister(RC);
1901 unsigned NewVal = (BinOpcode || IsSubWord ?
1902 MRI.createVirtualRegister(RC) : Src2.getReg());
1903 unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
1904 unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
1906 // Insert a basic block for the main loop.
1907 MachineBasicBlock *StartMBB = MBB;
1908 MachineBasicBlock *DoneMBB = splitBlockAfter(MI, MBB);
1909 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
1913 // %OrigVal = L Disp(%Base)
1914 // # fall through to LoopMMB
1916 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
1917 .addOperand(Base).addImm(Disp).addReg(0);
1918 MBB->addSuccessor(LoopMBB);
1921 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, LoopMBB ]
1922 // %RotatedOldVal = RLL %OldVal, 0(%BitShift)
1923 // %RotatedNewVal = OP %RotatedOldVal, %Src2
1924 // %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
1925 // %Dest = CS %OldVal, %NewVal, Disp(%Base)
1927 // # fall through to DoneMMB
1929 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
1930 .addReg(OrigVal).addMBB(StartMBB)
1931 .addReg(Dest).addMBB(LoopMBB);
1933 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
1934 .addReg(OldVal).addReg(BitShift).addImm(0);
1936 // Perform the operation normally and then invert every bit of the field.
1937 unsigned Tmp = MRI.createVirtualRegister(RC);
1938 BuildMI(MBB, DL, TII->get(BinOpcode), Tmp)
1939 .addReg(RotatedOldVal).addOperand(Src2);
1941 // XILF with the upper BitSize bits set.
1942 BuildMI(MBB, DL, TII->get(SystemZ::XILF32), RotatedNewVal)
1943 .addReg(Tmp).addImm(uint32_t(~0 << (32 - BitSize)));
1944 else if (BitSize == 32)
1945 // XILF with every bit set.
1946 BuildMI(MBB, DL, TII->get(SystemZ::XILF32), RotatedNewVal)
1947 .addReg(Tmp).addImm(~uint32_t(0));
1949 // Use LCGR and add -1 to the result, which is more compact than
1950 // an XILF, XILH pair.
1951 unsigned Tmp2 = MRI.createVirtualRegister(RC);
1952 BuildMI(MBB, DL, TII->get(SystemZ::LCGR), Tmp2).addReg(Tmp);
1953 BuildMI(MBB, DL, TII->get(SystemZ::AGHI), RotatedNewVal)
1954 .addReg(Tmp2).addImm(-1);
1956 } else if (BinOpcode)
1957 // A simply binary operation.
1958 BuildMI(MBB, DL, TII->get(BinOpcode), RotatedNewVal)
1959 .addReg(RotatedOldVal).addOperand(Src2);
1961 // Use RISBG to rotate Src2 into position and use it to replace the
1962 // field in RotatedOldVal.
1963 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedNewVal)
1964 .addReg(RotatedOldVal).addReg(Src2.getReg())
1965 .addImm(32).addImm(31 + BitSize).addImm(32 - BitSize);
1967 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
1968 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
1969 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
1970 .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
1971 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
1972 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
1973 MBB->addSuccessor(LoopMBB);
1974 MBB->addSuccessor(DoneMBB);
1976 MI->eraseFromParent();
1980 // Implement EmitInstrWithCustomInserter for pseudo
1981 // ATOMIC_LOAD{,W}_{,U}{MIN,MAX} instruction MI. CompareOpcode is the
1982 // instruction that should be used to compare the current field with the
1983 // minimum or maximum value. KeepOldMask is the BRC condition-code mask
1984 // for when the current field should be kept. BitSize is the width of
1985 // the field in bits, or 0 if this is a partword ATOMIC_LOADW_* instruction.
1987 SystemZTargetLowering::emitAtomicLoadMinMax(MachineInstr *MI,
1988 MachineBasicBlock *MBB,
1989 unsigned CompareOpcode,
1990 unsigned KeepOldMask,
1991 unsigned BitSize) const {
1992 const SystemZInstrInfo *TII = TM.getInstrInfo();
1993 MachineFunction &MF = *MBB->getParent();
1994 MachineRegisterInfo &MRI = MF.getRegInfo();
1995 bool IsSubWord = (BitSize < 32);
1997 // Extract the operands. Base can be a register or a frame index.
1998 unsigned Dest = MI->getOperand(0).getReg();
1999 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
2000 int64_t Disp = MI->getOperand(2).getImm();
2001 unsigned Src2 = MI->getOperand(3).getReg();
2002 unsigned BitShift = (IsSubWord ? MI->getOperand(4).getReg() : 0);
2003 unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0);
2004 DebugLoc DL = MI->getDebugLoc();
2006 BitSize = MI->getOperand(6).getImm();
2008 // Subword operations use 32-bit registers.
2009 const TargetRegisterClass *RC = (BitSize <= 32 ?
2010 &SystemZ::GR32BitRegClass :
2011 &SystemZ::GR64BitRegClass);
2012 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
2013 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
2015 // Get the right opcodes for the displacement.
2016 LOpcode = TII->getOpcodeForOffset(LOpcode, Disp);
2017 CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
2018 assert(LOpcode && CSOpcode && "Displacement out of range");
2020 // Create virtual registers for temporary results.
2021 unsigned OrigVal = MRI.createVirtualRegister(RC);
2022 unsigned OldVal = MRI.createVirtualRegister(RC);
2023 unsigned NewVal = MRI.createVirtualRegister(RC);
2024 unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
2025 unsigned RotatedAltVal = (IsSubWord ? MRI.createVirtualRegister(RC) : Src2);
2026 unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
2028 // Insert 3 basic blocks for the loop.
2029 MachineBasicBlock *StartMBB = MBB;
2030 MachineBasicBlock *DoneMBB = splitBlockAfter(MI, MBB);
2031 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
2032 MachineBasicBlock *UseAltMBB = emitBlockAfter(LoopMBB);
2033 MachineBasicBlock *UpdateMBB = emitBlockAfter(UseAltMBB);
2037 // %OrigVal = L Disp(%Base)
2038 // # fall through to LoopMMB
2040 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
2041 .addOperand(Base).addImm(Disp).addReg(0);
2042 MBB->addSuccessor(LoopMBB);
2045 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, UpdateMBB ]
2046 // %RotatedOldVal = RLL %OldVal, 0(%BitShift)
2047 // CompareOpcode %RotatedOldVal, %Src2
2048 // BRC KeepOldMask, UpdateMBB
2050 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
2051 .addReg(OrigVal).addMBB(StartMBB)
2052 .addReg(Dest).addMBB(UpdateMBB);
2054 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
2055 .addReg(OldVal).addReg(BitShift).addImm(0);
2056 BuildMI(MBB, DL, TII->get(CompareOpcode))
2057 .addReg(RotatedOldVal).addReg(Src2);
2058 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2059 .addImm(SystemZ::CCMASK_ICMP).addImm(KeepOldMask).addMBB(UpdateMBB);
2060 MBB->addSuccessor(UpdateMBB);
2061 MBB->addSuccessor(UseAltMBB);
2064 // %RotatedAltVal = RISBG %RotatedOldVal, %Src2, 32, 31 + BitSize, 0
2065 // # fall through to UpdateMMB
2068 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedAltVal)
2069 .addReg(RotatedOldVal).addReg(Src2)
2070 .addImm(32).addImm(31 + BitSize).addImm(0);
2071 MBB->addSuccessor(UpdateMBB);
2074 // %RotatedNewVal = PHI [ %RotatedOldVal, LoopMBB ],
2075 // [ %RotatedAltVal, UseAltMBB ]
2076 // %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
2077 // %Dest = CS %OldVal, %NewVal, Disp(%Base)
2079 // # fall through to DoneMMB
2081 BuildMI(MBB, DL, TII->get(SystemZ::PHI), RotatedNewVal)
2082 .addReg(RotatedOldVal).addMBB(LoopMBB)
2083 .addReg(RotatedAltVal).addMBB(UseAltMBB);
2085 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
2086 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
2087 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
2088 .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
2089 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2090 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
2091 MBB->addSuccessor(LoopMBB);
2092 MBB->addSuccessor(DoneMBB);
2094 MI->eraseFromParent();
2098 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_CMP_SWAPW
2101 SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr *MI,
2102 MachineBasicBlock *MBB) const {
2103 const SystemZInstrInfo *TII = TM.getInstrInfo();
2104 MachineFunction &MF = *MBB->getParent();
2105 MachineRegisterInfo &MRI = MF.getRegInfo();
2107 // Extract the operands. Base can be a register or a frame index.
2108 unsigned Dest = MI->getOperand(0).getReg();
2109 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
2110 int64_t Disp = MI->getOperand(2).getImm();
2111 unsigned OrigCmpVal = MI->getOperand(3).getReg();
2112 unsigned OrigSwapVal = MI->getOperand(4).getReg();
2113 unsigned BitShift = MI->getOperand(5).getReg();
2114 unsigned NegBitShift = MI->getOperand(6).getReg();
2115 int64_t BitSize = MI->getOperand(7).getImm();
2116 DebugLoc DL = MI->getDebugLoc();
2118 const TargetRegisterClass *RC = &SystemZ::GR32BitRegClass;
2120 // Get the right opcodes for the displacement.
2121 unsigned LOpcode = TII->getOpcodeForOffset(SystemZ::L, Disp);
2122 unsigned CSOpcode = TII->getOpcodeForOffset(SystemZ::CS, Disp);
2123 assert(LOpcode && CSOpcode && "Displacement out of range");
2125 // Create virtual registers for temporary results.
2126 unsigned OrigOldVal = MRI.createVirtualRegister(RC);
2127 unsigned OldVal = MRI.createVirtualRegister(RC);
2128 unsigned CmpVal = MRI.createVirtualRegister(RC);
2129 unsigned SwapVal = MRI.createVirtualRegister(RC);
2130 unsigned StoreVal = MRI.createVirtualRegister(RC);
2131 unsigned RetryOldVal = MRI.createVirtualRegister(RC);
2132 unsigned RetryCmpVal = MRI.createVirtualRegister(RC);
2133 unsigned RetrySwapVal = MRI.createVirtualRegister(RC);
2135 // Insert 2 basic blocks for the loop.
2136 MachineBasicBlock *StartMBB = MBB;
2137 MachineBasicBlock *DoneMBB = splitBlockAfter(MI, MBB);
2138 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
2139 MachineBasicBlock *SetMBB = emitBlockAfter(LoopMBB);
2143 // %OrigOldVal = L Disp(%Base)
2144 // # fall through to LoopMMB
2146 BuildMI(MBB, DL, TII->get(LOpcode), OrigOldVal)
2147 .addOperand(Base).addImm(Disp).addReg(0);
2148 MBB->addSuccessor(LoopMBB);
2151 // %OldVal = phi [ %OrigOldVal, EntryBB ], [ %RetryOldVal, SetMBB ]
2152 // %CmpVal = phi [ %OrigCmpVal, EntryBB ], [ %RetryCmpVal, SetMBB ]
2153 // %SwapVal = phi [ %OrigSwapVal, EntryBB ], [ %RetrySwapVal, SetMBB ]
2154 // %Dest = RLL %OldVal, BitSize(%BitShift)
2155 // ^^ The low BitSize bits contain the field
2157 // %RetryCmpVal = RISBG32 %CmpVal, %Dest, 32, 63-BitSize, 0
2158 // ^^ Replace the upper 32-BitSize bits of the
2159 // comparison value with those that we loaded,
2160 // so that we can use a full word comparison.
2161 // CR %Dest, %RetryCmpVal
2163 // # Fall through to SetMBB
2165 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
2166 .addReg(OrigOldVal).addMBB(StartMBB)
2167 .addReg(RetryOldVal).addMBB(SetMBB);
2168 BuildMI(MBB, DL, TII->get(SystemZ::PHI), CmpVal)
2169 .addReg(OrigCmpVal).addMBB(StartMBB)
2170 .addReg(RetryCmpVal).addMBB(SetMBB);
2171 BuildMI(MBB, DL, TII->get(SystemZ::PHI), SwapVal)
2172 .addReg(OrigSwapVal).addMBB(StartMBB)
2173 .addReg(RetrySwapVal).addMBB(SetMBB);
2174 BuildMI(MBB, DL, TII->get(SystemZ::RLL), Dest)
2175 .addReg(OldVal).addReg(BitShift).addImm(BitSize);
2176 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetryCmpVal)
2177 .addReg(CmpVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
2178 BuildMI(MBB, DL, TII->get(SystemZ::CR))
2179 .addReg(Dest).addReg(RetryCmpVal);
2180 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2181 .addImm(SystemZ::CCMASK_ICMP)
2182 .addImm(SystemZ::CCMASK_CMP_NE).addMBB(DoneMBB);
2183 MBB->addSuccessor(DoneMBB);
2184 MBB->addSuccessor(SetMBB);
2187 // %RetrySwapVal = RISBG32 %SwapVal, %Dest, 32, 63-BitSize, 0
2188 // ^^ Replace the upper 32-BitSize bits of the new
2189 // value with those that we loaded.
2190 // %StoreVal = RLL %RetrySwapVal, -BitSize(%NegBitShift)
2191 // ^^ Rotate the new field to its proper position.
2192 // %RetryOldVal = CS %Dest, %StoreVal, Disp(%Base)
2194 // # fall through to ExitMMB
2196 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetrySwapVal)
2197 .addReg(SwapVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
2198 BuildMI(MBB, DL, TII->get(SystemZ::RLL), StoreVal)
2199 .addReg(RetrySwapVal).addReg(NegBitShift).addImm(-BitSize);
2200 BuildMI(MBB, DL, TII->get(CSOpcode), RetryOldVal)
2201 .addReg(OldVal).addReg(StoreVal).addOperand(Base).addImm(Disp);
2202 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2203 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
2204 MBB->addSuccessor(LoopMBB);
2205 MBB->addSuccessor(DoneMBB);
2207 MI->eraseFromParent();
2211 // Emit an extension from a GR32 or GR64 to a GR128. ClearEven is true
2212 // if the high register of the GR128 value must be cleared or false if
2213 // it's "don't care". SubReg is subreg_odd32 when extending a GR32
2214 // and subreg_odd when extending a GR64.
2216 SystemZTargetLowering::emitExt128(MachineInstr *MI,
2217 MachineBasicBlock *MBB,
2218 bool ClearEven, unsigned SubReg) const {
2219 const SystemZInstrInfo *TII = TM.getInstrInfo();
2220 MachineFunction &MF = *MBB->getParent();
2221 MachineRegisterInfo &MRI = MF.getRegInfo();
2222 DebugLoc DL = MI->getDebugLoc();
2224 unsigned Dest = MI->getOperand(0).getReg();
2225 unsigned Src = MI->getOperand(1).getReg();
2226 unsigned In128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
2228 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::IMPLICIT_DEF), In128);
2230 unsigned NewIn128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
2231 unsigned Zero64 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
2233 BuildMI(*MBB, MI, DL, TII->get(SystemZ::LLILL), Zero64)
2235 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), NewIn128)
2236 .addReg(In128).addReg(Zero64).addImm(SystemZ::subreg_high);
2239 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dest)
2240 .addReg(In128).addReg(Src).addImm(SubReg);
2242 MI->eraseFromParent();
2247 SystemZTargetLowering::emitMemMemWrapper(MachineInstr *MI,
2248 MachineBasicBlock *MBB,
2249 unsigned Opcode) const {
2250 const SystemZInstrInfo *TII = TM.getInstrInfo();
2251 DebugLoc DL = MI->getDebugLoc();
2253 MachineOperand DestBase = MI->getOperand(0);
2254 uint64_t DestDisp = MI->getOperand(1).getImm();
2255 MachineOperand SrcBase = MI->getOperand(2);
2256 uint64_t SrcDisp = MI->getOperand(3).getImm();
2257 uint64_t Length = MI->getOperand(4).getImm();
2259 BuildMI(*MBB, MI, DL, TII->get(Opcode))
2260 .addOperand(DestBase).addImm(DestDisp).addImm(Length)
2261 .addOperand(SrcBase).addImm(SrcDisp);
2263 MI->eraseFromParent();
2267 // Decompose string pseudo-instruction MI into a loop that continually performs
2268 // Opcode until CC != 3.
2270 SystemZTargetLowering::emitStringWrapper(MachineInstr *MI,
2271 MachineBasicBlock *MBB,
2272 unsigned Opcode) const {
2273 const SystemZInstrInfo *TII = TM.getInstrInfo();
2274 MachineFunction &MF = *MBB->getParent();
2275 MachineRegisterInfo &MRI = MF.getRegInfo();
2276 DebugLoc DL = MI->getDebugLoc();
2278 uint64_t End1Reg = MI->getOperand(0).getReg();
2279 uint64_t Start1Reg = MI->getOperand(1).getReg();
2280 uint64_t Start2Reg = MI->getOperand(2).getReg();
2281 uint64_t CharReg = MI->getOperand(3).getReg();
2283 const TargetRegisterClass *RC = &SystemZ::GR64BitRegClass;
2284 uint64_t This1Reg = MRI.createVirtualRegister(RC);
2285 uint64_t This2Reg = MRI.createVirtualRegister(RC);
2286 uint64_t End2Reg = MRI.createVirtualRegister(RC);
2288 MachineBasicBlock *StartMBB = MBB;
2289 MachineBasicBlock *DoneMBB = splitBlockAfter(MI, MBB);
2290 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
2294 // # fall through to LoopMMB
2295 BuildMI(MBB, DL, TII->get(TargetOpcode::COPY), SystemZ::R0W).addReg(CharReg);
2296 MBB->addSuccessor(LoopMBB);
2299 // %This1Reg = phi [ %Start1Reg, StartMBB ], [ %End1Reg, LoopMBB ]
2300 // %This2Reg = phi [ %Start2Reg, StartMBB ], [ %End2Reg, LoopMBB ]
2301 // %End1Reg, %End2Reg = CLST %This1Reg, %This2Reg -- uses R0W
2303 // # fall through to DoneMMB
2305 MBB->addLiveIn(SystemZ::R0W);
2307 BuildMI(MBB, DL, TII->get(SystemZ::PHI), This1Reg)
2308 .addReg(Start1Reg).addMBB(StartMBB)
2309 .addReg(End1Reg).addMBB(LoopMBB);
2310 BuildMI(MBB, DL, TII->get(SystemZ::PHI), This2Reg)
2311 .addReg(Start2Reg).addMBB(StartMBB)
2312 .addReg(End2Reg).addMBB(LoopMBB);
2313 BuildMI(MBB, DL, TII->get(Opcode))
2314 .addReg(End1Reg, RegState::Define).addReg(End2Reg, RegState::Define)
2315 .addReg(This1Reg).addReg(This2Reg);
2316 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2317 .addImm(SystemZ::CCMASK_ANY).addImm(SystemZ::CCMASK_3).addMBB(LoopMBB);
2318 MBB->addSuccessor(LoopMBB);
2319 MBB->addSuccessor(DoneMBB);
2321 DoneMBB->addLiveIn(SystemZ::CC);
2323 MI->eraseFromParent();
2327 MachineBasicBlock *SystemZTargetLowering::
2328 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const {
2329 switch (MI->getOpcode()) {
2330 case SystemZ::Select32:
2331 case SystemZ::SelectF32:
2332 case SystemZ::Select64:
2333 case SystemZ::SelectF64:
2334 case SystemZ::SelectF128:
2335 return emitSelect(MI, MBB);
2337 case SystemZ::CondStore8_32:
2338 return emitCondStore(MI, MBB, SystemZ::STC32, 0, false);
2339 case SystemZ::CondStore8_32Inv:
2340 return emitCondStore(MI, MBB, SystemZ::STC32, 0, true);
2341 case SystemZ::CondStore16_32:
2342 return emitCondStore(MI, MBB, SystemZ::STH32, 0, false);
2343 case SystemZ::CondStore16_32Inv:
2344 return emitCondStore(MI, MBB, SystemZ::STH32, 0, true);
2345 case SystemZ::CondStore32_32:
2346 return emitCondStore(MI, MBB, SystemZ::ST32, SystemZ::STOC32, false);
2347 case SystemZ::CondStore32_32Inv:
2348 return emitCondStore(MI, MBB, SystemZ::ST32, SystemZ::STOC32, true);
2349 case SystemZ::CondStore8:
2350 return emitCondStore(MI, MBB, SystemZ::STC, 0, false);
2351 case SystemZ::CondStore8Inv:
2352 return emitCondStore(MI, MBB, SystemZ::STC, 0, true);
2353 case SystemZ::CondStore16:
2354 return emitCondStore(MI, MBB, SystemZ::STH, 0, false);
2355 case SystemZ::CondStore16Inv:
2356 return emitCondStore(MI, MBB, SystemZ::STH, 0, true);
2357 case SystemZ::CondStore32:
2358 return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, false);
2359 case SystemZ::CondStore32Inv:
2360 return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, true);
2361 case SystemZ::CondStore64:
2362 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, false);
2363 case SystemZ::CondStore64Inv:
2364 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, true);
2365 case SystemZ::CondStoreF32:
2366 return emitCondStore(MI, MBB, SystemZ::STE, 0, false);
2367 case SystemZ::CondStoreF32Inv:
2368 return emitCondStore(MI, MBB, SystemZ::STE, 0, true);
2369 case SystemZ::CondStoreF64:
2370 return emitCondStore(MI, MBB, SystemZ::STD, 0, false);
2371 case SystemZ::CondStoreF64Inv:
2372 return emitCondStore(MI, MBB, SystemZ::STD, 0, true);
2374 case SystemZ::AEXT128_64:
2375 return emitExt128(MI, MBB, false, SystemZ::subreg_low);
2376 case SystemZ::ZEXT128_32:
2377 return emitExt128(MI, MBB, true, SystemZ::subreg_low32);
2378 case SystemZ::ZEXT128_64:
2379 return emitExt128(MI, MBB, true, SystemZ::subreg_low);
2381 case SystemZ::ATOMIC_SWAPW:
2382 return emitAtomicLoadBinary(MI, MBB, 0, 0);
2383 case SystemZ::ATOMIC_SWAP_32:
2384 return emitAtomicLoadBinary(MI, MBB, 0, 32);
2385 case SystemZ::ATOMIC_SWAP_64:
2386 return emitAtomicLoadBinary(MI, MBB, 0, 64);
2388 case SystemZ::ATOMIC_LOADW_AR:
2389 return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 0);
2390 case SystemZ::ATOMIC_LOADW_AFI:
2391 return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 0);
2392 case SystemZ::ATOMIC_LOAD_AR:
2393 return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 32);
2394 case SystemZ::ATOMIC_LOAD_AHI:
2395 return emitAtomicLoadBinary(MI, MBB, SystemZ::AHI, 32);
2396 case SystemZ::ATOMIC_LOAD_AFI:
2397 return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 32);
2398 case SystemZ::ATOMIC_LOAD_AGR:
2399 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGR, 64);
2400 case SystemZ::ATOMIC_LOAD_AGHI:
2401 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGHI, 64);
2402 case SystemZ::ATOMIC_LOAD_AGFI:
2403 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGFI, 64);
2405 case SystemZ::ATOMIC_LOADW_SR:
2406 return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 0);
2407 case SystemZ::ATOMIC_LOAD_SR:
2408 return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 32);
2409 case SystemZ::ATOMIC_LOAD_SGR:
2410 return emitAtomicLoadBinary(MI, MBB, SystemZ::SGR, 64);
2412 case SystemZ::ATOMIC_LOADW_NR:
2413 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0);
2414 case SystemZ::ATOMIC_LOADW_NILH:
2415 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH32, 0);
2416 case SystemZ::ATOMIC_LOAD_NR:
2417 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32);
2418 case SystemZ::ATOMIC_LOAD_NILL32:
2419 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL32, 32);
2420 case SystemZ::ATOMIC_LOAD_NILH32:
2421 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH32, 32);
2422 case SystemZ::ATOMIC_LOAD_NILF32:
2423 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF32, 32);
2424 case SystemZ::ATOMIC_LOAD_NGR:
2425 return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64);
2426 case SystemZ::ATOMIC_LOAD_NILL:
2427 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 64);
2428 case SystemZ::ATOMIC_LOAD_NILH:
2429 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 64);
2430 case SystemZ::ATOMIC_LOAD_NIHL:
2431 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL, 64);
2432 case SystemZ::ATOMIC_LOAD_NIHH:
2433 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH, 64);
2434 case SystemZ::ATOMIC_LOAD_NILF:
2435 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 64);
2436 case SystemZ::ATOMIC_LOAD_NIHF:
2437 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF, 64);
2439 case SystemZ::ATOMIC_LOADW_OR:
2440 return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 0);
2441 case SystemZ::ATOMIC_LOADW_OILH:
2442 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH32, 0);
2443 case SystemZ::ATOMIC_LOAD_OR:
2444 return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 32);
2445 case SystemZ::ATOMIC_LOAD_OILL32:
2446 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL32, 32);
2447 case SystemZ::ATOMIC_LOAD_OILH32:
2448 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH32, 32);
2449 case SystemZ::ATOMIC_LOAD_OILF32:
2450 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF32, 32);
2451 case SystemZ::ATOMIC_LOAD_OGR:
2452 return emitAtomicLoadBinary(MI, MBB, SystemZ::OGR, 64);
2453 case SystemZ::ATOMIC_LOAD_OILL:
2454 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL, 64);
2455 case SystemZ::ATOMIC_LOAD_OILH:
2456 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 64);
2457 case SystemZ::ATOMIC_LOAD_OIHL:
2458 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHL, 64);
2459 case SystemZ::ATOMIC_LOAD_OIHH:
2460 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHH, 64);
2461 case SystemZ::ATOMIC_LOAD_OILF:
2462 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF, 64);
2463 case SystemZ::ATOMIC_LOAD_OIHF:
2464 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHF, 64);
2466 case SystemZ::ATOMIC_LOADW_XR:
2467 return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 0);
2468 case SystemZ::ATOMIC_LOADW_XILF:
2469 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF32, 0);
2470 case SystemZ::ATOMIC_LOAD_XR:
2471 return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 32);
2472 case SystemZ::ATOMIC_LOAD_XILF32:
2473 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF32, 32);
2474 case SystemZ::ATOMIC_LOAD_XGR:
2475 return emitAtomicLoadBinary(MI, MBB, SystemZ::XGR, 64);
2476 case SystemZ::ATOMIC_LOAD_XILF:
2477 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 64);
2478 case SystemZ::ATOMIC_LOAD_XIHF:
2479 return emitAtomicLoadBinary(MI, MBB, SystemZ::XIHF, 64);
2481 case SystemZ::ATOMIC_LOADW_NRi:
2482 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0, true);
2483 case SystemZ::ATOMIC_LOADW_NILHi:
2484 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH32, 0, true);
2485 case SystemZ::ATOMIC_LOAD_NRi:
2486 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32, true);
2487 case SystemZ::ATOMIC_LOAD_NILL32i:
2488 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL32, 32, true);
2489 case SystemZ::ATOMIC_LOAD_NILH32i:
2490 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH32, 32, true);
2491 case SystemZ::ATOMIC_LOAD_NILF32i:
2492 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF32, 32, true);
2493 case SystemZ::ATOMIC_LOAD_NGRi:
2494 return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64, true);
2495 case SystemZ::ATOMIC_LOAD_NILLi:
2496 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 64, true);
2497 case SystemZ::ATOMIC_LOAD_NILHi:
2498 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 64, true);
2499 case SystemZ::ATOMIC_LOAD_NIHLi:
2500 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL, 64, true);
2501 case SystemZ::ATOMIC_LOAD_NIHHi:
2502 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH, 64, true);
2503 case SystemZ::ATOMIC_LOAD_NILFi:
2504 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 64, true);
2505 case SystemZ::ATOMIC_LOAD_NIHFi:
2506 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF, 64, true);
2508 case SystemZ::ATOMIC_LOADW_MIN:
2509 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
2510 SystemZ::CCMASK_CMP_LE, 0);
2511 case SystemZ::ATOMIC_LOAD_MIN_32:
2512 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
2513 SystemZ::CCMASK_CMP_LE, 32);
2514 case SystemZ::ATOMIC_LOAD_MIN_64:
2515 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
2516 SystemZ::CCMASK_CMP_LE, 64);
2518 case SystemZ::ATOMIC_LOADW_MAX:
2519 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
2520 SystemZ::CCMASK_CMP_GE, 0);
2521 case SystemZ::ATOMIC_LOAD_MAX_32:
2522 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
2523 SystemZ::CCMASK_CMP_GE, 32);
2524 case SystemZ::ATOMIC_LOAD_MAX_64:
2525 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
2526 SystemZ::CCMASK_CMP_GE, 64);
2528 case SystemZ::ATOMIC_LOADW_UMIN:
2529 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
2530 SystemZ::CCMASK_CMP_LE, 0);
2531 case SystemZ::ATOMIC_LOAD_UMIN_32:
2532 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
2533 SystemZ::CCMASK_CMP_LE, 32);
2534 case SystemZ::ATOMIC_LOAD_UMIN_64:
2535 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
2536 SystemZ::CCMASK_CMP_LE, 64);
2538 case SystemZ::ATOMIC_LOADW_UMAX:
2539 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
2540 SystemZ::CCMASK_CMP_GE, 0);
2541 case SystemZ::ATOMIC_LOAD_UMAX_32:
2542 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
2543 SystemZ::CCMASK_CMP_GE, 32);
2544 case SystemZ::ATOMIC_LOAD_UMAX_64:
2545 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
2546 SystemZ::CCMASK_CMP_GE, 64);
2548 case SystemZ::ATOMIC_CMP_SWAPW:
2549 return emitAtomicCmpSwapW(MI, MBB);
2550 case SystemZ::MVCWrapper:
2551 return emitMemMemWrapper(MI, MBB, SystemZ::MVC);
2552 case SystemZ::CLCWrapper:
2553 return emitMemMemWrapper(MI, MBB, SystemZ::CLC);
2554 case SystemZ::CLSTLoop:
2555 return emitStringWrapper(MI, MBB, SystemZ::CLST);
2556 case SystemZ::MVSTLoop:
2557 return emitStringWrapper(MI, MBB, SystemZ::MVST);
2558 case SystemZ::SRSTLoop:
2559 return emitStringWrapper(MI, MBB, SystemZ::SRST);
2561 llvm_unreachable("Unexpected instr type to insert");