1 //===-- SystemZISelLowering.cpp - SystemZ DAG lowering implementation -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SystemZTargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "systemz-lower"
16 #include "SystemZISelLowering.h"
17 #include "SystemZCallingConv.h"
18 #include "SystemZConstantPoolValue.h"
19 #include "SystemZMachineFunctionInfo.h"
20 #include "SystemZTargetMachine.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 // Classify VT as either 32 or 64 bit.
29 static bool is32Bit(EVT VT) {
30 switch (VT.getSimpleVT().SimpleTy) {
36 llvm_unreachable("Unsupported type");
40 // Return a version of MachineOperand that can be safely used before the
42 static MachineOperand earlyUseOperand(MachineOperand Op) {
48 SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm)
49 : TargetLowering(tm, new TargetLoweringObjectFileELF()),
50 Subtarget(*tm.getSubtargetImpl()), TM(tm) {
51 MVT PtrVT = getPointerTy();
53 // Set up the register classes.
54 addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass);
55 addRegisterClass(MVT::i64, &SystemZ::GR64BitRegClass);
56 addRegisterClass(MVT::f32, &SystemZ::FP32BitRegClass);
57 addRegisterClass(MVT::f64, &SystemZ::FP64BitRegClass);
58 addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass);
60 // Compute derived properties from the register classes
61 computeRegisterProperties();
63 // Set up special registers.
64 setExceptionPointerRegister(SystemZ::R6D);
65 setExceptionSelectorRegister(SystemZ::R7D);
66 setStackPointerRegisterToSaveRestore(SystemZ::R15D);
68 // TODO: It may be better to default to latency-oriented scheduling, however
69 // LLVM's current latency-oriented scheduler can't handle physreg definitions
70 // such as SystemZ has with CC, so set this to the register-pressure
71 // scheduler, because it can.
72 setSchedulingPreference(Sched::RegPressure);
74 setBooleanContents(ZeroOrOneBooleanContent);
75 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
77 // Instructions are strings of 2-byte aligned 2-byte values.
78 setMinFunctionAlignment(2);
80 // Handle operations that are handled in a similar way for all types.
81 for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
82 I <= MVT::LAST_FP_VALUETYPE;
84 MVT VT = MVT::SimpleValueType(I);
85 if (isTypeLegal(VT)) {
86 // Expand SETCC(X, Y, COND) into SELECT_CC(X, Y, 1, 0, COND).
87 setOperationAction(ISD::SETCC, VT, Expand);
89 // Expand SELECT(C, A, B) into SELECT_CC(X, 0, A, B, NE).
90 setOperationAction(ISD::SELECT, VT, Expand);
92 // Lower SELECT_CC and BR_CC into separate comparisons and branches.
93 setOperationAction(ISD::SELECT_CC, VT, Custom);
94 setOperationAction(ISD::BR_CC, VT, Custom);
98 // Expand jump table branches as address arithmetic followed by an
100 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
102 // Expand BRCOND into a BR_CC (see above).
103 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
105 // Handle integer types.
106 for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
107 I <= MVT::LAST_INTEGER_VALUETYPE;
109 MVT VT = MVT::SimpleValueType(I);
110 if (isTypeLegal(VT)) {
111 // Expand individual DIV and REMs into DIVREMs.
112 setOperationAction(ISD::SDIV, VT, Expand);
113 setOperationAction(ISD::UDIV, VT, Expand);
114 setOperationAction(ISD::SREM, VT, Expand);
115 setOperationAction(ISD::UREM, VT, Expand);
116 setOperationAction(ISD::SDIVREM, VT, Custom);
117 setOperationAction(ISD::UDIVREM, VT, Custom);
119 // Expand ATOMIC_LOAD and ATOMIC_STORE using ATOMIC_CMP_SWAP.
120 // FIXME: probably much too conservative.
121 setOperationAction(ISD::ATOMIC_LOAD, VT, Expand);
122 setOperationAction(ISD::ATOMIC_STORE, VT, Expand);
124 // No special instructions for these.
125 setOperationAction(ISD::CTPOP, VT, Expand);
126 setOperationAction(ISD::CTTZ, VT, Expand);
127 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
128 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
129 setOperationAction(ISD::ROTR, VT, Expand);
131 // Use *MUL_LOHI where possible instead of MULH*.
132 setOperationAction(ISD::MULHS, VT, Expand);
133 setOperationAction(ISD::MULHU, VT, Expand);
134 setOperationAction(ISD::SMUL_LOHI, VT, Custom);
135 setOperationAction(ISD::UMUL_LOHI, VT, Custom);
137 // We have instructions for signed but not unsigned FP conversion.
138 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
142 // Type legalization will convert 8- and 16-bit atomic operations into
143 // forms that operate on i32s (but still keeping the original memory VT).
144 // Lower them into full i32 operations.
145 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Custom);
146 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Custom);
147 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
148 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Custom);
149 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Custom);
150 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Custom);
151 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Custom);
152 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Custom);
153 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Custom);
154 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Custom);
155 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Custom);
156 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
158 // We have instructions for signed but not unsigned FP conversion.
159 // Handle unsigned 32-bit types as signed 64-bit types.
160 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote);
161 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
163 // We have native support for a 64-bit CTLZ, via FLOGR.
164 setOperationAction(ISD::CTLZ, MVT::i32, Promote);
165 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
167 // Give LowerOperation the chance to replace 64-bit ORs with subregs.
168 setOperationAction(ISD::OR, MVT::i64, Custom);
170 // FIXME: Can we support these natively?
171 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
172 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
173 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
175 // We have native instructions for i8, i16 and i32 extensions, but not i1.
176 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
177 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
178 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
179 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
181 // Handle the various types of symbolic address.
182 setOperationAction(ISD::ConstantPool, PtrVT, Custom);
183 setOperationAction(ISD::GlobalAddress, PtrVT, Custom);
184 setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom);
185 setOperationAction(ISD::BlockAddress, PtrVT, Custom);
186 setOperationAction(ISD::JumpTable, PtrVT, Custom);
188 // We need to handle dynamic allocations specially because of the
189 // 160-byte area at the bottom of the stack.
190 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
192 // Use custom expanders so that we can force the function to use
194 setOperationAction(ISD::STACKSAVE, MVT::Other, Custom);
195 setOperationAction(ISD::STACKRESTORE, MVT::Other, Custom);
197 // Handle prefetches with PFD or PFDRL.
198 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
200 // Handle floating-point types.
201 for (unsigned I = MVT::FIRST_FP_VALUETYPE;
202 I <= MVT::LAST_FP_VALUETYPE;
204 MVT VT = MVT::SimpleValueType(I);
205 if (isTypeLegal(VT)) {
206 // We can use FI for FRINT.
207 setOperationAction(ISD::FRINT, VT, Legal);
209 // We can use the extended form of FI for other rounding operations.
210 if (Subtarget.hasFPExtension()) {
211 setOperationAction(ISD::FNEARBYINT, VT, Legal);
212 setOperationAction(ISD::FFLOOR, VT, Legal);
213 setOperationAction(ISD::FCEIL, VT, Legal);
214 setOperationAction(ISD::FTRUNC, VT, Legal);
215 setOperationAction(ISD::FROUND, VT, Legal);
218 // No special instructions for these.
219 setOperationAction(ISD::FSIN, VT, Expand);
220 setOperationAction(ISD::FCOS, VT, Expand);
221 setOperationAction(ISD::FREM, VT, Expand);
225 // We have fused multiply-addition for f32 and f64 but not f128.
226 setOperationAction(ISD::FMA, MVT::f32, Legal);
227 setOperationAction(ISD::FMA, MVT::f64, Legal);
228 setOperationAction(ISD::FMA, MVT::f128, Expand);
230 // Needed so that we don't try to implement f128 constant loads using
231 // a load-and-extend of a f80 constant (in cases where the constant
232 // would fit in an f80).
233 setLoadExtAction(ISD::EXTLOAD, MVT::f80, Expand);
235 // Floating-point truncation and stores need to be done separately.
236 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
237 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
238 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
240 // We have 64-bit FPR<->GPR moves, but need special handling for
242 setOperationAction(ISD::BITCAST, MVT::i32, Custom);
243 setOperationAction(ISD::BITCAST, MVT::f32, Custom);
245 // VASTART and VACOPY need to deal with the SystemZ-specific varargs
246 // structure, but VAEND is a no-op.
247 setOperationAction(ISD::VASTART, MVT::Other, Custom);
248 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
249 setOperationAction(ISD::VAEND, MVT::Other, Expand);
251 // We want to use MVC in preference to even a single load/store pair.
252 MaxStoresPerMemcpy = 0;
253 MaxStoresPerMemcpyOptSize = 0;
255 // The main memset sequence is a byte store followed by an MVC.
256 // Two STC or MV..I stores win over that, but the kind of fused stores
257 // generated by target-independent code don't when the byte value is
258 // variable. E.g. "STC <reg>;MHI <reg>,257;STH <reg>" is not better
259 // than "STC;MVC". Handle the choice in target-specific code instead.
260 MaxStoresPerMemset = 0;
261 MaxStoresPerMemsetOptSize = 0;
265 SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
266 VT = VT.getScalarType();
271 switch (VT.getSimpleVT().SimpleTy) {
284 bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
285 // We can load zero using LZ?R and negative zero using LZ?R;LC?BR.
286 return Imm.isZero() || Imm.isNegZero();
289 bool SystemZTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
291 // Unaligned accesses should never be slower than the expanded version.
292 // We check specifically for aligned accesses in the few cases where
293 // they are required.
299 bool SystemZTargetLowering::isLegalAddressingMode(const AddrMode &AM,
301 // Punt on globals for now, although they can be used in limited
302 // RELATIVE LONG cases.
306 // Require a 20-bit signed offset.
307 if (!isInt<20>(AM.BaseOffs))
310 // Indexing is OK but no scale factor can be applied.
311 return AM.Scale == 0 || AM.Scale == 1;
314 bool SystemZTargetLowering::isTruncateFree(Type *FromType, Type *ToType) const {
315 if (!FromType->isIntegerTy() || !ToType->isIntegerTy())
317 unsigned FromBits = FromType->getPrimitiveSizeInBits();
318 unsigned ToBits = ToType->getPrimitiveSizeInBits();
319 return FromBits > ToBits;
322 bool SystemZTargetLowering::isTruncateFree(EVT FromVT, EVT ToVT) const {
323 if (!FromVT.isInteger() || !ToVT.isInteger())
325 unsigned FromBits = FromVT.getSizeInBits();
326 unsigned ToBits = ToVT.getSizeInBits();
327 return FromBits > ToBits;
330 //===----------------------------------------------------------------------===//
331 // Inline asm support
332 //===----------------------------------------------------------------------===//
334 TargetLowering::ConstraintType
335 SystemZTargetLowering::getConstraintType(const std::string &Constraint) const {
336 if (Constraint.size() == 1) {
337 switch (Constraint[0]) {
338 case 'a': // Address register
339 case 'd': // Data register (equivalent to 'r')
340 case 'f': // Floating-point register
341 case 'r': // General-purpose register
342 return C_RegisterClass;
344 case 'Q': // Memory with base and unsigned 12-bit displacement
345 case 'R': // Likewise, plus an index
346 case 'S': // Memory with base and signed 20-bit displacement
347 case 'T': // Likewise, plus an index
348 case 'm': // Equivalent to 'T'.
351 case 'I': // Unsigned 8-bit constant
352 case 'J': // Unsigned 12-bit constant
353 case 'K': // Signed 16-bit constant
354 case 'L': // Signed 20-bit displacement (on all targets we support)
355 case 'M': // 0x7fffffff
362 return TargetLowering::getConstraintType(Constraint);
365 TargetLowering::ConstraintWeight SystemZTargetLowering::
366 getSingleConstraintMatchWeight(AsmOperandInfo &info,
367 const char *constraint) const {
368 ConstraintWeight weight = CW_Invalid;
369 Value *CallOperandVal = info.CallOperandVal;
370 // If we don't have a value, we can't do a match,
371 // but allow it at the lowest weight.
372 if (CallOperandVal == NULL)
374 Type *type = CallOperandVal->getType();
375 // Look at the constraint type.
376 switch (*constraint) {
378 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
381 case 'a': // Address register
382 case 'd': // Data register (equivalent to 'r')
383 case 'r': // General-purpose register
384 if (CallOperandVal->getType()->isIntegerTy())
385 weight = CW_Register;
388 case 'f': // Floating-point register
389 if (type->isFloatingPointTy())
390 weight = CW_Register;
393 case 'I': // Unsigned 8-bit constant
394 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
395 if (isUInt<8>(C->getZExtValue()))
396 weight = CW_Constant;
399 case 'J': // Unsigned 12-bit constant
400 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
401 if (isUInt<12>(C->getZExtValue()))
402 weight = CW_Constant;
405 case 'K': // Signed 16-bit constant
406 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
407 if (isInt<16>(C->getSExtValue()))
408 weight = CW_Constant;
411 case 'L': // Signed 20-bit displacement (on all targets we support)
412 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
413 if (isInt<20>(C->getSExtValue()))
414 weight = CW_Constant;
417 case 'M': // 0x7fffffff
418 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
419 if (C->getZExtValue() == 0x7fffffff)
420 weight = CW_Constant;
426 // Parse a "{tNNN}" register constraint for which the register type "t"
427 // has already been verified. MC is the class associated with "t" and
428 // Map maps 0-based register numbers to LLVM register numbers.
429 static std::pair<unsigned, const TargetRegisterClass *>
430 parseRegisterNumber(const std::string &Constraint,
431 const TargetRegisterClass *RC, const unsigned *Map) {
432 assert(*(Constraint.end()-1) == '}' && "Missing '}'");
433 if (isdigit(Constraint[2])) {
434 std::string Suffix(Constraint.data() + 2, Constraint.size() - 2);
435 unsigned Index = atoi(Suffix.c_str());
436 if (Index < 16 && Map[Index])
437 return std::make_pair(Map[Index], RC);
439 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
442 std::pair<unsigned, const TargetRegisterClass *> SystemZTargetLowering::
443 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const {
444 if (Constraint.size() == 1) {
445 // GCC Constraint Letters
446 switch (Constraint[0]) {
448 case 'd': // Data register (equivalent to 'r')
449 case 'r': // General-purpose register
451 return std::make_pair(0U, &SystemZ::GR64BitRegClass);
452 else if (VT == MVT::i128)
453 return std::make_pair(0U, &SystemZ::GR128BitRegClass);
454 return std::make_pair(0U, &SystemZ::GR32BitRegClass);
456 case 'a': // Address register
458 return std::make_pair(0U, &SystemZ::ADDR64BitRegClass);
459 else if (VT == MVT::i128)
460 return std::make_pair(0U, &SystemZ::ADDR128BitRegClass);
461 return std::make_pair(0U, &SystemZ::ADDR32BitRegClass);
463 case 'f': // Floating-point register
465 return std::make_pair(0U, &SystemZ::FP64BitRegClass);
466 else if (VT == MVT::f128)
467 return std::make_pair(0U, &SystemZ::FP128BitRegClass);
468 return std::make_pair(0U, &SystemZ::FP32BitRegClass);
471 if (Constraint[0] == '{') {
472 // We need to override the default register parsing for GPRs and FPRs
473 // because the interpretation depends on VT. The internal names of
474 // the registers are also different from the external names
475 // (F0D and F0S instead of F0, etc.).
476 if (Constraint[1] == 'r') {
478 return parseRegisterNumber(Constraint, &SystemZ::GR32BitRegClass,
479 SystemZMC::GR32Regs);
481 return parseRegisterNumber(Constraint, &SystemZ::GR128BitRegClass,
482 SystemZMC::GR128Regs);
483 return parseRegisterNumber(Constraint, &SystemZ::GR64BitRegClass,
484 SystemZMC::GR64Regs);
486 if (Constraint[1] == 'f') {
488 return parseRegisterNumber(Constraint, &SystemZ::FP32BitRegClass,
489 SystemZMC::FP32Regs);
491 return parseRegisterNumber(Constraint, &SystemZ::FP128BitRegClass,
492 SystemZMC::FP128Regs);
493 return parseRegisterNumber(Constraint, &SystemZ::FP64BitRegClass,
494 SystemZMC::FP64Regs);
497 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
500 void SystemZTargetLowering::
501 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
502 std::vector<SDValue> &Ops,
503 SelectionDAG &DAG) const {
504 // Only support length 1 constraints for now.
505 if (Constraint.length() == 1) {
506 switch (Constraint[0]) {
507 case 'I': // Unsigned 8-bit constant
508 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
509 if (isUInt<8>(C->getZExtValue()))
510 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
514 case 'J': // Unsigned 12-bit constant
515 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
516 if (isUInt<12>(C->getZExtValue()))
517 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
521 case 'K': // Signed 16-bit constant
522 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
523 if (isInt<16>(C->getSExtValue()))
524 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
528 case 'L': // Signed 20-bit displacement (on all targets we support)
529 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
530 if (isInt<20>(C->getSExtValue()))
531 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
535 case 'M': // 0x7fffffff
536 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
537 if (C->getZExtValue() == 0x7fffffff)
538 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
543 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
546 //===----------------------------------------------------------------------===//
547 // Calling conventions
548 //===----------------------------------------------------------------------===//
550 #include "SystemZGenCallingConv.inc"
552 bool SystemZTargetLowering::allowTruncateForTailCall(Type *FromType,
553 Type *ToType) const {
554 return isTruncateFree(FromType, ToType);
557 bool SystemZTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
558 if (!CI->isTailCall())
563 // Value is a value that has been passed to us in the location described by VA
564 // (and so has type VA.getLocVT()). Convert Value to VA.getValVT(), chaining
565 // any loads onto Chain.
566 static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDLoc DL,
567 CCValAssign &VA, SDValue Chain,
569 // If the argument has been promoted from a smaller type, insert an
570 // assertion to capture this.
571 if (VA.getLocInfo() == CCValAssign::SExt)
572 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value,
573 DAG.getValueType(VA.getValVT()));
574 else if (VA.getLocInfo() == CCValAssign::ZExt)
575 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value,
576 DAG.getValueType(VA.getValVT()));
579 Value = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Value);
580 else if (VA.getLocInfo() == CCValAssign::Indirect)
581 Value = DAG.getLoad(VA.getValVT(), DL, Chain, Value,
582 MachinePointerInfo(), false, false, false, 0);
584 assert(VA.getLocInfo() == CCValAssign::Full && "Unsupported getLocInfo");
588 // Value is a value of type VA.getValVT() that we need to copy into
589 // the location described by VA. Return a copy of Value converted to
590 // VA.getValVT(). The caller is responsible for handling indirect values.
591 static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDLoc DL,
592 CCValAssign &VA, SDValue Value) {
593 switch (VA.getLocInfo()) {
594 case CCValAssign::SExt:
595 return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value);
596 case CCValAssign::ZExt:
597 return DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Value);
598 case CCValAssign::AExt:
599 return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value);
600 case CCValAssign::Full:
603 llvm_unreachable("Unhandled getLocInfo()");
607 SDValue SystemZTargetLowering::
608 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
609 const SmallVectorImpl<ISD::InputArg> &Ins,
610 SDLoc DL, SelectionDAG &DAG,
611 SmallVectorImpl<SDValue> &InVals) const {
612 MachineFunction &MF = DAG.getMachineFunction();
613 MachineFrameInfo *MFI = MF.getFrameInfo();
614 MachineRegisterInfo &MRI = MF.getRegInfo();
615 SystemZMachineFunctionInfo *FuncInfo =
616 MF.getInfo<SystemZMachineFunctionInfo>();
617 const SystemZFrameLowering *TFL =
618 static_cast<const SystemZFrameLowering *>(TM.getFrameLowering());
620 // Assign locations to all of the incoming arguments.
621 SmallVector<CCValAssign, 16> ArgLocs;
622 CCState CCInfo(CallConv, IsVarArg, MF, TM, ArgLocs, *DAG.getContext());
623 CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ);
625 unsigned NumFixedGPRs = 0;
626 unsigned NumFixedFPRs = 0;
627 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
629 CCValAssign &VA = ArgLocs[I];
630 EVT LocVT = VA.getLocVT();
632 // Arguments passed in registers
633 const TargetRegisterClass *RC;
634 switch (LocVT.getSimpleVT().SimpleTy) {
636 // Integers smaller than i64 should be promoted to i64.
637 llvm_unreachable("Unexpected argument type");
640 RC = &SystemZ::GR32BitRegClass;
644 RC = &SystemZ::GR64BitRegClass;
648 RC = &SystemZ::FP32BitRegClass;
652 RC = &SystemZ::FP64BitRegClass;
656 unsigned VReg = MRI.createVirtualRegister(RC);
657 MRI.addLiveIn(VA.getLocReg(), VReg);
658 ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
660 assert(VA.isMemLoc() && "Argument not register or memory");
662 // Create the frame index object for this incoming parameter.
663 int FI = MFI->CreateFixedObject(LocVT.getSizeInBits() / 8,
664 VA.getLocMemOffset(), true);
666 // Create the SelectionDAG nodes corresponding to a load
667 // from this parameter. Unpromoted ints and floats are
668 // passed as right-justified 8-byte values.
669 EVT PtrVT = getPointerTy();
670 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
671 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
672 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4));
673 ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN,
674 MachinePointerInfo::getFixedStack(FI),
675 false, false, false, 0);
678 // Convert the value of the argument register into the value that's
680 InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, ArgValue));
684 // Save the number of non-varargs registers for later use by va_start, etc.
685 FuncInfo->setVarArgsFirstGPR(NumFixedGPRs);
686 FuncInfo->setVarArgsFirstFPR(NumFixedFPRs);
688 // Likewise the address (in the form of a frame index) of where the
689 // first stack vararg would be. The 1-byte size here is arbitrary.
690 int64_t StackSize = CCInfo.getNextStackOffset();
691 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize, true));
693 // ...and a similar frame index for the caller-allocated save area
694 // that will be used to store the incoming registers.
695 int64_t RegSaveOffset = TFL->getOffsetOfLocalArea();
696 unsigned RegSaveIndex = MFI->CreateFixedObject(1, RegSaveOffset, true);
697 FuncInfo->setRegSaveFrameIndex(RegSaveIndex);
699 // Store the FPR varargs in the reserved frame slots. (We store the
700 // GPRs as part of the prologue.)
701 if (NumFixedFPRs < SystemZ::NumArgFPRs) {
702 SDValue MemOps[SystemZ::NumArgFPRs];
703 for (unsigned I = NumFixedFPRs; I < SystemZ::NumArgFPRs; ++I) {
704 unsigned Offset = TFL->getRegSpillOffset(SystemZ::ArgFPRs[I]);
705 int FI = MFI->CreateFixedObject(8, RegSaveOffset + Offset, true);
706 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
707 unsigned VReg = MF.addLiveIn(SystemZ::ArgFPRs[I],
708 &SystemZ::FP64BitRegClass);
709 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f64);
710 MemOps[I] = DAG.getStore(ArgValue.getValue(1), DL, ArgValue, FIN,
711 MachinePointerInfo::getFixedStack(FI),
715 // Join the stores, which are independent of one another.
716 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
717 &MemOps[NumFixedFPRs],
718 SystemZ::NumArgFPRs - NumFixedFPRs);
725 static bool canUseSiblingCall(CCState ArgCCInfo,
726 SmallVectorImpl<CCValAssign> &ArgLocs) {
727 // Punt if there are any indirect or stack arguments, or if the call
728 // needs the call-saved argument register R6.
729 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
730 CCValAssign &VA = ArgLocs[I];
731 if (VA.getLocInfo() == CCValAssign::Indirect)
735 unsigned Reg = VA.getLocReg();
736 if (Reg == SystemZ::R6W || Reg == SystemZ::R6D)
743 SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
744 SmallVectorImpl<SDValue> &InVals) const {
745 SelectionDAG &DAG = CLI.DAG;
747 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
748 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
749 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
750 SDValue Chain = CLI.Chain;
751 SDValue Callee = CLI.Callee;
752 bool &IsTailCall = CLI.IsTailCall;
753 CallingConv::ID CallConv = CLI.CallConv;
754 bool IsVarArg = CLI.IsVarArg;
755 MachineFunction &MF = DAG.getMachineFunction();
756 EVT PtrVT = getPointerTy();
758 // Analyze the operands of the call, assigning locations to each operand.
759 SmallVector<CCValAssign, 16> ArgLocs;
760 CCState ArgCCInfo(CallConv, IsVarArg, MF, TM, ArgLocs, *DAG.getContext());
761 ArgCCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
763 // We don't support GuaranteedTailCallOpt, only automatically-detected
765 if (IsTailCall && !canUseSiblingCall(ArgCCInfo, ArgLocs))
768 // Get a count of how many bytes are to be pushed on the stack.
769 unsigned NumBytes = ArgCCInfo.getNextStackOffset();
771 // Mark the start of the call.
773 Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes, PtrVT, true),
776 // Copy argument values to their designated locations.
777 SmallVector<std::pair<unsigned, SDValue>, 9> RegsToPass;
778 SmallVector<SDValue, 8> MemOpChains;
780 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
781 CCValAssign &VA = ArgLocs[I];
782 SDValue ArgValue = OutVals[I];
784 if (VA.getLocInfo() == CCValAssign::Indirect) {
785 // Store the argument in a stack slot and pass its address.
786 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
787 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
788 MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, SpillSlot,
789 MachinePointerInfo::getFixedStack(FI),
791 ArgValue = SpillSlot;
793 ArgValue = convertValVTToLocVT(DAG, DL, VA, ArgValue);
796 // Queue up the argument copies and emit them at the end.
797 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));
799 assert(VA.isMemLoc() && "Argument not register or memory");
801 // Work out the address of the stack slot. Unpromoted ints and
802 // floats are passed as right-justified 8-byte values.
803 if (!StackPtr.getNode())
804 StackPtr = DAG.getCopyFromReg(Chain, DL, SystemZ::R15D, PtrVT);
805 unsigned Offset = SystemZMC::CallFrameSize + VA.getLocMemOffset();
806 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
808 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
809 DAG.getIntPtrConstant(Offset));
812 MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, Address,
813 MachinePointerInfo(),
818 // Join the stores, which are independent of one another.
819 if (!MemOpChains.empty())
820 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
821 &MemOpChains[0], MemOpChains.size());
823 // Accept direct calls by converting symbolic call addresses to the
824 // associated Target* opcodes. Force %r1 to be used for indirect
827 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
828 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT);
829 Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
830 } else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
831 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT);
832 Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
833 } else if (IsTailCall) {
834 Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R1D, Callee, Glue);
835 Glue = Chain.getValue(1);
836 Callee = DAG.getRegister(SystemZ::R1D, Callee.getValueType());
839 // Build a sequence of copy-to-reg nodes, chained and glued together.
840 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {
841 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
842 RegsToPass[I].second, Glue);
843 Glue = Chain.getValue(1);
846 // The first call operand is the chain and the second is the target address.
847 SmallVector<SDValue, 8> Ops;
848 Ops.push_back(Chain);
849 Ops.push_back(Callee);
851 // Add argument registers to the end of the list so that they are
852 // known live into the call.
853 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I)
854 Ops.push_back(DAG.getRegister(RegsToPass[I].first,
855 RegsToPass[I].second.getValueType()));
857 // Glue the call to the argument copies, if any.
862 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
864 return DAG.getNode(SystemZISD::SIBCALL, DL, NodeTys, &Ops[0], Ops.size());
865 Chain = DAG.getNode(SystemZISD::CALL, DL, NodeTys, &Ops[0], Ops.size());
866 Glue = Chain.getValue(1);
868 // Mark the end of the call, which is glued to the call itself.
869 Chain = DAG.getCALLSEQ_END(Chain,
870 DAG.getConstant(NumBytes, PtrVT, true),
871 DAG.getConstant(0, PtrVT, true),
873 Glue = Chain.getValue(1);
875 // Assign locations to each value returned by this call.
876 SmallVector<CCValAssign, 16> RetLocs;
877 CCState RetCCInfo(CallConv, IsVarArg, MF, TM, RetLocs, *DAG.getContext());
878 RetCCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ);
880 // Copy all of the result registers out of their specified physreg.
881 for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
882 CCValAssign &VA = RetLocs[I];
884 // Copy the value out, gluing the copy to the end of the call sequence.
885 SDValue RetValue = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(),
886 VA.getLocVT(), Glue);
887 Chain = RetValue.getValue(1);
888 Glue = RetValue.getValue(2);
890 // Convert the value of the return register into the value that's
892 InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, RetValue));
899 SystemZTargetLowering::LowerReturn(SDValue Chain,
900 CallingConv::ID CallConv, bool IsVarArg,
901 const SmallVectorImpl<ISD::OutputArg> &Outs,
902 const SmallVectorImpl<SDValue> &OutVals,
903 SDLoc DL, SelectionDAG &DAG) const {
904 MachineFunction &MF = DAG.getMachineFunction();
906 // Assign locations to each returned value.
907 SmallVector<CCValAssign, 16> RetLocs;
908 CCState RetCCInfo(CallConv, IsVarArg, MF, TM, RetLocs, *DAG.getContext());
909 RetCCInfo.AnalyzeReturn(Outs, RetCC_SystemZ);
911 // Quick exit for void returns
913 return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, Chain);
915 // Copy the result values into the output registers.
917 SmallVector<SDValue, 4> RetOps;
918 RetOps.push_back(Chain);
919 for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
920 CCValAssign &VA = RetLocs[I];
921 SDValue RetValue = OutVals[I];
923 // Make the return register live on exit.
924 assert(VA.isRegLoc() && "Can only return in registers!");
926 // Promote the value as required.
927 RetValue = convertValVTToLocVT(DAG, DL, VA, RetValue);
929 // Chain and glue the copies together.
930 unsigned Reg = VA.getLocReg();
931 Chain = DAG.getCopyToReg(Chain, DL, Reg, RetValue, Glue);
932 Glue = Chain.getValue(1);
933 RetOps.push_back(DAG.getRegister(Reg, VA.getLocVT()));
936 // Update chain and glue.
939 RetOps.push_back(Glue);
941 return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other,
942 RetOps.data(), RetOps.size());
945 // CC is a comparison that will be implemented using an integer or
946 // floating-point comparison. Return the condition code mask for
947 // a branch on true. In the integer case, CCMASK_CMP_UO is set for
948 // unsigned comparisons and clear for signed ones. In the floating-point
949 // case, CCMASK_CMP_UO has its normal mask meaning (unordered).
950 static unsigned CCMaskForCondCode(ISD::CondCode CC) {
952 case ISD::SET##X: return SystemZ::CCMASK_CMP_##X; \
953 case ISD::SETO##X: return SystemZ::CCMASK_CMP_##X; \
954 case ISD::SETU##X: return SystemZ::CCMASK_CMP_UO | SystemZ::CCMASK_CMP_##X
958 llvm_unreachable("Invalid integer condition!");
967 case ISD::SETO: return SystemZ::CCMASK_CMP_O;
968 case ISD::SETUO: return SystemZ::CCMASK_CMP_UO;
973 // If a comparison described by IsUnsigned, CCMask, CmpOp0 and CmpOp1
974 // can be converted to a comparison against zero, adjust the operands
976 static void adjustZeroCmp(SelectionDAG &DAG, bool &IsUnsigned,
977 SDValue &CmpOp0, SDValue &CmpOp1,
982 ConstantSDNode *ConstOp1 = dyn_cast<ConstantSDNode>(CmpOp1.getNode());
986 int64_t Value = ConstOp1->getSExtValue();
987 if ((Value == -1 && CCMask == SystemZ::CCMASK_CMP_GT) ||
988 (Value == -1 && CCMask == SystemZ::CCMASK_CMP_LE) ||
989 (Value == 1 && CCMask == SystemZ::CCMASK_CMP_LT) ||
990 (Value == 1 && CCMask == SystemZ::CCMASK_CMP_GE)) {
991 CCMask ^= SystemZ::CCMASK_CMP_EQ;
992 CmpOp1 = DAG.getConstant(0, CmpOp1.getValueType());
996 // If a comparison described by IsUnsigned, CCMask, CmpOp0 and CmpOp1
997 // is suitable for CLI(Y), CHHSI or CLHHSI, adjust the operands as necessary.
998 static void adjustSubwordCmp(SelectionDAG &DAG, bool &IsUnsigned,
999 SDValue &CmpOp0, SDValue &CmpOp1,
1001 // For us to make any changes, it must a comparison between a single-use
1002 // load and a constant.
1003 if (!CmpOp0.hasOneUse() ||
1004 CmpOp0.getOpcode() != ISD::LOAD ||
1005 CmpOp1.getOpcode() != ISD::Constant)
1008 // We must have an 8- or 16-bit load.
1009 LoadSDNode *Load = cast<LoadSDNode>(CmpOp0);
1010 unsigned NumBits = Load->getMemoryVT().getStoreSizeInBits();
1011 if (NumBits != 8 && NumBits != 16)
1014 // The load must be an extending one and the constant must be within the
1015 // range of the unextended value.
1016 ConstantSDNode *Constant = cast<ConstantSDNode>(CmpOp1);
1017 uint64_t Value = Constant->getZExtValue();
1018 uint64_t Mask = (1 << NumBits) - 1;
1019 if (Load->getExtensionType() == ISD::SEXTLOAD) {
1020 int64_t SignedValue = Constant->getSExtValue();
1021 if (uint64_t(SignedValue) + (1ULL << (NumBits - 1)) > Mask)
1023 // Unsigned comparison between two sign-extended values is equivalent
1024 // to unsigned comparison between two zero-extended values.
1027 else if (CCMask == SystemZ::CCMASK_CMP_EQ ||
1028 CCMask == SystemZ::CCMASK_CMP_NE)
1029 // Any choice of IsUnsigned is OK for equality comparisons.
1030 // We could use either CHHSI or CLHHSI for 16-bit comparisons,
1031 // but since we use CLHHSI for zero extensions, it seems better
1032 // to be consistent and do the same here.
1033 Value &= Mask, IsUnsigned = true;
1034 else if (NumBits == 8) {
1035 // Try to treat the comparison as unsigned, so that we can use CLI.
1036 // Adjust CCMask and Value as necessary.
1037 if (Value == 0 && CCMask == SystemZ::CCMASK_CMP_LT)
1038 // Test whether the high bit of the byte is set.
1039 Value = 127, CCMask = SystemZ::CCMASK_CMP_GT, IsUnsigned = true;
1040 else if (Value == 0 && CCMask == SystemZ::CCMASK_CMP_GE)
1041 // Test whether the high bit of the byte is clear.
1042 Value = 128, CCMask = SystemZ::CCMASK_CMP_LT, IsUnsigned = true;
1044 // No instruction exists for this combination.
1047 } else if (Load->getExtensionType() == ISD::ZEXTLOAD) {
1050 // Signed comparison between two zero-extended values is equivalent
1051 // to unsigned comparison.
1056 // Make sure that the first operand is an i32 of the right extension type.
1057 ISD::LoadExtType ExtType = IsUnsigned ? ISD::ZEXTLOAD : ISD::SEXTLOAD;
1058 if (CmpOp0.getValueType() != MVT::i32 ||
1059 Load->getExtensionType() != ExtType)
1060 CmpOp0 = DAG.getExtLoad(ExtType, SDLoc(Load), MVT::i32,
1061 Load->getChain(), Load->getBasePtr(),
1062 Load->getPointerInfo(), Load->getMemoryVT(),
1063 Load->isVolatile(), Load->isNonTemporal(),
1064 Load->getAlignment());
1066 // Make sure that the second operand is an i32 with the right value.
1067 if (CmpOp1.getValueType() != MVT::i32 ||
1068 Value != Constant->getZExtValue())
1069 CmpOp1 = DAG.getConstant(Value, MVT::i32);
1072 // Return true if Op is either an unextended load, or a load suitable
1073 // for integer register-memory comparisons of type ICmpType.
1074 static bool isNaturalMemoryOperand(SDValue Op, unsigned ICmpType) {
1075 LoadSDNode *Load = dyn_cast<LoadSDNode>(Op.getNode());
1077 // There are no instructions to compare a register with a memory byte.
1078 if (Load->getMemoryVT() == MVT::i8)
1080 // Otherwise decide on extension type.
1081 switch (Load->getExtensionType()) {
1082 case ISD::NON_EXTLOAD:
1085 return ICmpType != SystemZICMP::UnsignedOnly;
1087 return ICmpType != SystemZICMP::SignedOnly;
1095 // Return true if it is better to swap comparison operands Op0 and Op1.
1096 // ICmpType is the type of an integer comparison.
1097 static bool shouldSwapCmpOperands(SDValue Op0, SDValue Op1,
1098 unsigned ICmpType) {
1099 // Leave f128 comparisons alone, since they have no memory forms.
1100 if (Op0.getValueType() == MVT::f128)
1103 // Always keep a floating-point constant second, since comparisons with
1104 // zero can use LOAD TEST and comparisons with other constants make a
1105 // natural memory operand.
1106 if (isa<ConstantFPSDNode>(Op1))
1109 // Never swap comparisons with zero since there are many ways to optimize
1111 ConstantSDNode *COp1 = dyn_cast<ConstantSDNode>(Op1);
1112 if (COp1 && COp1->getZExtValue() == 0)
1115 // Look for cases where Cmp0 is a single-use load and Cmp1 isn't.
1116 // In that case we generally prefer the memory to be second.
1117 if ((isNaturalMemoryOperand(Op0, ICmpType) && Op0.hasOneUse()) &&
1118 !(isNaturalMemoryOperand(Op1, ICmpType) && Op1.hasOneUse())) {
1119 // The only exceptions are when the second operand is a constant and
1120 // we can use things like CHHSI.
1123 // The unsigned memory-immediate instructions can handle 16-bit
1124 // unsigned integers.
1125 if (ICmpType != SystemZICMP::SignedOnly &&
1126 isUInt<16>(COp1->getZExtValue()))
1128 // The signed memory-immediate instructions can handle 16-bit
1130 if (ICmpType != SystemZICMP::UnsignedOnly &&
1131 isInt<16>(COp1->getSExtValue()))
1138 // Return true if shift operation N has an in-range constant shift value.
1139 // Store it in ShiftVal if so.
1140 static bool isSimpleShift(SDValue N, unsigned &ShiftVal) {
1141 ConstantSDNode *Shift = dyn_cast<ConstantSDNode>(N.getOperand(1));
1145 uint64_t Amount = Shift->getZExtValue();
1146 if (Amount >= N.getValueType().getSizeInBits())
1153 // Check whether an AND with Mask is suitable for a TEST UNDER MASK
1154 // instruction and whether the CC value is descriptive enough to handle
1155 // a comparison of type Opcode between the AND result and CmpVal.
1156 // CCMask says which comparison result is being tested and BitSize is
1157 // the number of bits in the operands. If TEST UNDER MASK can be used,
1158 // return the corresponding CC mask, otherwise return 0.
1159 static unsigned getTestUnderMaskCond(unsigned BitSize, unsigned CCMask,
1160 uint64_t Mask, uint64_t CmpVal,
1161 unsigned ICmpType) {
1162 assert(Mask != 0 && "ANDs with zero should have been removed by now");
1164 // Check whether the mask is suitable for TMHH, TMHL, TMLH or TMLL.
1165 if (!SystemZ::isImmLL(Mask) && !SystemZ::isImmLH(Mask) &&
1166 !SystemZ::isImmHL(Mask) && !SystemZ::isImmHH(Mask))
1169 // Work out the masks for the lowest and highest bits.
1170 unsigned HighShift = 63 - countLeadingZeros(Mask);
1171 uint64_t High = uint64_t(1) << HighShift;
1172 uint64_t Low = uint64_t(1) << countTrailingZeros(Mask);
1174 // Signed ordered comparisons are effectively unsigned if the sign
1176 bool EffectivelyUnsigned = (ICmpType != SystemZICMP::SignedOnly);
1178 // Check for equality comparisons with 0, or the equivalent.
1180 if (CCMask == SystemZ::CCMASK_CMP_EQ)
1181 return SystemZ::CCMASK_TM_ALL_0;
1182 if (CCMask == SystemZ::CCMASK_CMP_NE)
1183 return SystemZ::CCMASK_TM_SOME_1;
1185 if (EffectivelyUnsigned && CmpVal <= Low) {
1186 if (CCMask == SystemZ::CCMASK_CMP_LT)
1187 return SystemZ::CCMASK_TM_ALL_0;
1188 if (CCMask == SystemZ::CCMASK_CMP_GE)
1189 return SystemZ::CCMASK_TM_SOME_1;
1191 if (EffectivelyUnsigned && CmpVal < Low) {
1192 if (CCMask == SystemZ::CCMASK_CMP_LE)
1193 return SystemZ::CCMASK_TM_ALL_0;
1194 if (CCMask == SystemZ::CCMASK_CMP_GT)
1195 return SystemZ::CCMASK_TM_SOME_1;
1198 // Check for equality comparisons with the mask, or the equivalent.
1199 if (CmpVal == Mask) {
1200 if (CCMask == SystemZ::CCMASK_CMP_EQ)
1201 return SystemZ::CCMASK_TM_ALL_1;
1202 if (CCMask == SystemZ::CCMASK_CMP_NE)
1203 return SystemZ::CCMASK_TM_SOME_0;
1205 if (EffectivelyUnsigned && CmpVal >= Mask - Low && CmpVal < Mask) {
1206 if (CCMask == SystemZ::CCMASK_CMP_GT)
1207 return SystemZ::CCMASK_TM_ALL_1;
1208 if (CCMask == SystemZ::CCMASK_CMP_LE)
1209 return SystemZ::CCMASK_TM_SOME_0;
1211 if (EffectivelyUnsigned && CmpVal > Mask - Low && CmpVal <= Mask) {
1212 if (CCMask == SystemZ::CCMASK_CMP_GE)
1213 return SystemZ::CCMASK_TM_ALL_1;
1214 if (CCMask == SystemZ::CCMASK_CMP_LT)
1215 return SystemZ::CCMASK_TM_SOME_0;
1218 // Check for ordered comparisons with the top bit.
1219 if (EffectivelyUnsigned && CmpVal >= Mask - High && CmpVal < High) {
1220 if (CCMask == SystemZ::CCMASK_CMP_LE)
1221 return SystemZ::CCMASK_TM_MSB_0;
1222 if (CCMask == SystemZ::CCMASK_CMP_GT)
1223 return SystemZ::CCMASK_TM_MSB_1;
1225 if (EffectivelyUnsigned && CmpVal > Mask - High && CmpVal <= High) {
1226 if (CCMask == SystemZ::CCMASK_CMP_LT)
1227 return SystemZ::CCMASK_TM_MSB_0;
1228 if (CCMask == SystemZ::CCMASK_CMP_GE)
1229 return SystemZ::CCMASK_TM_MSB_1;
1232 // If there are just two bits, we can do equality checks for Low and High
1234 if (Mask == Low + High) {
1235 if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == Low)
1236 return SystemZ::CCMASK_TM_MIXED_MSB_0;
1237 if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == Low)
1238 return SystemZ::CCMASK_TM_MIXED_MSB_0 ^ SystemZ::CCMASK_ANY;
1239 if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == High)
1240 return SystemZ::CCMASK_TM_MIXED_MSB_1;
1241 if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == High)
1242 return SystemZ::CCMASK_TM_MIXED_MSB_1 ^ SystemZ::CCMASK_ANY;
1245 // Looks like we've exhausted our options.
1249 // See whether the comparison (Opcode CmpOp0, CmpOp1, ICmpType) can be
1250 // implemented as a TEST UNDER MASK instruction when the condition being
1251 // tested is as described by CCValid and CCMask. Update the arguments
1252 // with the TM version if so.
1253 static void adjustForTestUnderMask(SelectionDAG &DAG, unsigned &Opcode,
1254 SDValue &CmpOp0, SDValue &CmpOp1,
1255 unsigned &CCValid, unsigned &CCMask,
1256 unsigned &ICmpType) {
1257 // Check that we have a comparison with a constant.
1258 ConstantSDNode *ConstCmpOp1 = dyn_cast<ConstantSDNode>(CmpOp1);
1261 uint64_t CmpVal = ConstCmpOp1->getZExtValue();
1263 // Check whether the nonconstant input is an AND with a constant mask.
1264 if (CmpOp0.getOpcode() != ISD::AND)
1266 SDValue AndOp0 = CmpOp0.getOperand(0);
1267 SDValue AndOp1 = CmpOp0.getOperand(1);
1268 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(AndOp1.getNode());
1271 uint64_t MaskVal = Mask->getZExtValue();
1273 // Check whether the combination of mask, comparison value and comparison
1274 // type are suitable.
1275 unsigned BitSize = CmpOp0.getValueType().getSizeInBits();
1276 unsigned NewCCMask, ShiftVal;
1277 if (ICmpType != SystemZICMP::SignedOnly &&
1278 AndOp0.getOpcode() == ISD::SHL &&
1279 isSimpleShift(AndOp0, ShiftVal) &&
1280 (NewCCMask = getTestUnderMaskCond(BitSize, CCMask, MaskVal >> ShiftVal,
1282 SystemZICMP::Any))) {
1283 AndOp0 = AndOp0.getOperand(0);
1284 AndOp1 = DAG.getConstant(MaskVal >> ShiftVal, AndOp0.getValueType());
1285 } else if (ICmpType != SystemZICMP::SignedOnly &&
1286 AndOp0.getOpcode() == ISD::SRL &&
1287 isSimpleShift(AndOp0, ShiftVal) &&
1288 (NewCCMask = getTestUnderMaskCond(BitSize, CCMask,
1289 MaskVal << ShiftVal,
1291 SystemZICMP::UnsignedOnly))) {
1292 AndOp0 = AndOp0.getOperand(0);
1293 AndOp1 = DAG.getConstant(MaskVal << ShiftVal, AndOp0.getValueType());
1295 NewCCMask = getTestUnderMaskCond(BitSize, CCMask, MaskVal, CmpVal,
1301 // Go ahead and make the change.
1302 Opcode = SystemZISD::TM;
1305 ICmpType = (bool(NewCCMask & SystemZ::CCMASK_TM_MIXED_MSB_0) !=
1306 bool(NewCCMask & SystemZ::CCMASK_TM_MIXED_MSB_1));
1307 CCValid = SystemZ::CCMASK_TM;
1311 // Return a target node that compares CmpOp0 with CmpOp1 and stores a
1312 // 2-bit result in CC. Set CCValid to the CCMASK_* of all possible
1313 // 2-bit results and CCMask to the subset of those results that are
1314 // associated with Cond.
1315 static SDValue emitCmp(const SystemZTargetMachine &TM, SelectionDAG &DAG,
1316 SDLoc DL, SDValue CmpOp0, SDValue CmpOp1,
1317 ISD::CondCode Cond, unsigned &CCValid,
1319 bool IsUnsigned = false;
1320 CCMask = CCMaskForCondCode(Cond);
1321 unsigned Opcode, ICmpType = 0;
1322 if (CmpOp0.getValueType().isFloatingPoint()) {
1323 CCValid = SystemZ::CCMASK_FCMP;
1324 Opcode = SystemZISD::FCMP;
1326 IsUnsigned = CCMask & SystemZ::CCMASK_CMP_UO;
1327 CCValid = SystemZ::CCMASK_ICMP;
1329 adjustZeroCmp(DAG, IsUnsigned, CmpOp0, CmpOp1, CCMask);
1330 adjustSubwordCmp(DAG, IsUnsigned, CmpOp0, CmpOp1, CCMask);
1331 Opcode = SystemZISD::ICMP;
1332 // Choose the type of comparison. Equality and inequality tests can
1333 // use either signed or unsigned comparisons. The choice also doesn't
1334 // matter if both sign bits are known to be clear. In those cases we
1335 // want to give the main isel code the freedom to choose whichever
1337 if (CCMask == SystemZ::CCMASK_CMP_EQ ||
1338 CCMask == SystemZ::CCMASK_CMP_NE ||
1339 (DAG.SignBitIsZero(CmpOp0) && DAG.SignBitIsZero(CmpOp1)))
1340 ICmpType = SystemZICMP::Any;
1341 else if (IsUnsigned)
1342 ICmpType = SystemZICMP::UnsignedOnly;
1344 ICmpType = SystemZICMP::SignedOnly;
1347 if (shouldSwapCmpOperands(CmpOp0, CmpOp1, ICmpType)) {
1348 std::swap(CmpOp0, CmpOp1);
1349 CCMask = ((CCMask & SystemZ::CCMASK_CMP_EQ) |
1350 (CCMask & SystemZ::CCMASK_CMP_GT ? SystemZ::CCMASK_CMP_LT : 0) |
1351 (CCMask & SystemZ::CCMASK_CMP_LT ? SystemZ::CCMASK_CMP_GT : 0) |
1352 (CCMask & SystemZ::CCMASK_CMP_UO));
1355 adjustForTestUnderMask(DAG, Opcode, CmpOp0, CmpOp1, CCValid, CCMask,
1357 if (Opcode == SystemZISD::ICMP || Opcode == SystemZISD::TM)
1358 return DAG.getNode(Opcode, DL, MVT::Glue, CmpOp0, CmpOp1,
1359 DAG.getConstant(ICmpType, MVT::i32));
1360 return DAG.getNode(Opcode, DL, MVT::Glue, CmpOp0, CmpOp1);
1363 // Implement a 32-bit *MUL_LOHI operation by extending both operands to
1364 // 64 bits. Extend is the extension type to use. Store the high part
1365 // in Hi and the low part in Lo.
1366 static void lowerMUL_LOHI32(SelectionDAG &DAG, SDLoc DL,
1367 unsigned Extend, SDValue Op0, SDValue Op1,
1368 SDValue &Hi, SDValue &Lo) {
1369 Op0 = DAG.getNode(Extend, DL, MVT::i64, Op0);
1370 Op1 = DAG.getNode(Extend, DL, MVT::i64, Op1);
1371 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, Op0, Op1);
1372 Hi = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul, DAG.getConstant(32, MVT::i64));
1373 Hi = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Hi);
1374 Lo = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mul);
1377 // Lower a binary operation that produces two VT results, one in each
1378 // half of a GR128 pair. Op0 and Op1 are the VT operands to the operation,
1379 // Extend extends Op0 to a GR128, and Opcode performs the GR128 operation
1380 // on the extended Op0 and (unextended) Op1. Store the even register result
1381 // in Even and the odd register result in Odd.
1382 static void lowerGR128Binary(SelectionDAG &DAG, SDLoc DL, EVT VT,
1383 unsigned Extend, unsigned Opcode,
1384 SDValue Op0, SDValue Op1,
1385 SDValue &Even, SDValue &Odd) {
1386 SDNode *In128 = DAG.getMachineNode(Extend, DL, MVT::Untyped, Op0);
1387 SDValue Result = DAG.getNode(Opcode, DL, MVT::Untyped,
1388 SDValue(In128, 0), Op1);
1389 bool Is32Bit = is32Bit(VT);
1390 Even = DAG.getTargetExtractSubreg(SystemZ::even128(Is32Bit), DL, VT, Result);
1391 Odd = DAG.getTargetExtractSubreg(SystemZ::odd128(Is32Bit), DL, VT, Result);
1394 SDValue SystemZTargetLowering::lowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
1395 SDValue Chain = Op.getOperand(0);
1396 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1397 SDValue CmpOp0 = Op.getOperand(2);
1398 SDValue CmpOp1 = Op.getOperand(3);
1399 SDValue Dest = Op.getOperand(4);
1402 unsigned CCValid, CCMask;
1403 SDValue Flags = emitCmp(TM, DAG, DL, CmpOp0, CmpOp1, CC, CCValid, CCMask);
1404 return DAG.getNode(SystemZISD::BR_CCMASK, DL, Op.getValueType(),
1405 Chain, DAG.getConstant(CCValid, MVT::i32),
1406 DAG.getConstant(CCMask, MVT::i32), Dest, Flags);
1409 SDValue SystemZTargetLowering::lowerSELECT_CC(SDValue Op,
1410 SelectionDAG &DAG) const {
1411 SDValue CmpOp0 = Op.getOperand(0);
1412 SDValue CmpOp1 = Op.getOperand(1);
1413 SDValue TrueOp = Op.getOperand(2);
1414 SDValue FalseOp = Op.getOperand(3);
1415 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1418 unsigned CCValid, CCMask;
1419 SDValue Flags = emitCmp(TM, DAG, DL, CmpOp0, CmpOp1, CC, CCValid, CCMask);
1421 SmallVector<SDValue, 5> Ops;
1422 Ops.push_back(TrueOp);
1423 Ops.push_back(FalseOp);
1424 Ops.push_back(DAG.getConstant(CCValid, MVT::i32));
1425 Ops.push_back(DAG.getConstant(CCMask, MVT::i32));
1426 Ops.push_back(Flags);
1428 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1429 return DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VTs, &Ops[0], Ops.size());
1432 SDValue SystemZTargetLowering::lowerGlobalAddress(GlobalAddressSDNode *Node,
1433 SelectionDAG &DAG) const {
1435 const GlobalValue *GV = Node->getGlobal();
1436 int64_t Offset = Node->getOffset();
1437 EVT PtrVT = getPointerTy();
1438 Reloc::Model RM = TM.getRelocationModel();
1439 CodeModel::Model CM = TM.getCodeModel();
1442 if (Subtarget.isPC32DBLSymbol(GV, RM, CM)) {
1443 // Make sure that the offset is aligned to a halfword. If it isn't,
1444 // create an "anchor" at the previous 12-bit boundary.
1445 // FIXME check whether there is a better way of handling this.
1447 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
1448 Offset & ~uint64_t(0xfff));
1451 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Offset);
1454 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1456 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, SystemZII::MO_GOT);
1457 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1458 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
1459 MachinePointerInfo::getGOT(), false, false, false, 0);
1462 // If there was a non-zero offset that we didn't fold, create an explicit
1465 Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result,
1466 DAG.getConstant(Offset, PtrVT));
1471 SDValue SystemZTargetLowering::lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
1472 SelectionDAG &DAG) const {
1474 const GlobalValue *GV = Node->getGlobal();
1475 EVT PtrVT = getPointerTy();
1476 TLSModel::Model model = TM.getTLSModel(GV);
1478 if (model != TLSModel::LocalExec)
1479 llvm_unreachable("only local-exec TLS mode supported");
1481 // The high part of the thread pointer is in access register 0.
1482 SDValue TPHi = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
1483 DAG.getConstant(0, MVT::i32));
1484 TPHi = DAG.getNode(ISD::ANY_EXTEND, DL, PtrVT, TPHi);
1486 // The low part of the thread pointer is in access register 1.
1487 SDValue TPLo = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
1488 DAG.getConstant(1, MVT::i32));
1489 TPLo = DAG.getNode(ISD::ZERO_EXTEND, DL, PtrVT, TPLo);
1491 // Merge them into a single 64-bit address.
1492 SDValue TPHiShifted = DAG.getNode(ISD::SHL, DL, PtrVT, TPHi,
1493 DAG.getConstant(32, PtrVT));
1494 SDValue TP = DAG.getNode(ISD::OR, DL, PtrVT, TPHiShifted, TPLo);
1496 // Get the offset of GA from the thread pointer.
1497 SystemZConstantPoolValue *CPV =
1498 SystemZConstantPoolValue::Create(GV, SystemZCP::NTPOFF);
1500 // Force the offset into the constant pool and load it from there.
1501 SDValue CPAddr = DAG.getConstantPool(CPV, PtrVT, 8);
1502 SDValue Offset = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(),
1503 CPAddr, MachinePointerInfo::getConstantPool(),
1504 false, false, false, 0);
1506 // Add the base and offset together.
1507 return DAG.getNode(ISD::ADD, DL, PtrVT, TP, Offset);
1510 SDValue SystemZTargetLowering::lowerBlockAddress(BlockAddressSDNode *Node,
1511 SelectionDAG &DAG) const {
1513 const BlockAddress *BA = Node->getBlockAddress();
1514 int64_t Offset = Node->getOffset();
1515 EVT PtrVT = getPointerTy();
1517 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset);
1518 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1522 SDValue SystemZTargetLowering::lowerJumpTable(JumpTableSDNode *JT,
1523 SelectionDAG &DAG) const {
1525 EVT PtrVT = getPointerTy();
1526 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1528 // Use LARL to load the address of the table.
1529 return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1532 SDValue SystemZTargetLowering::lowerConstantPool(ConstantPoolSDNode *CP,
1533 SelectionDAG &DAG) const {
1535 EVT PtrVT = getPointerTy();
1538 if (CP->isMachineConstantPoolEntry())
1539 Result = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1540 CP->getAlignment());
1542 Result = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1543 CP->getAlignment(), CP->getOffset());
1545 // Use LARL to load the address of the constant pool entry.
1546 return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1549 SDValue SystemZTargetLowering::lowerBITCAST(SDValue Op,
1550 SelectionDAG &DAG) const {
1552 SDValue In = Op.getOperand(0);
1553 EVT InVT = In.getValueType();
1554 EVT ResVT = Op.getValueType();
1556 SDValue Shift32 = DAG.getConstant(32, MVT::i64);
1557 if (InVT == MVT::i32 && ResVT == MVT::f32) {
1558 SDValue In64 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, In);
1559 SDValue Shift = DAG.getNode(ISD::SHL, DL, MVT::i64, In64, Shift32);
1560 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::f64, Shift);
1561 return DAG.getTargetExtractSubreg(SystemZ::subreg_32bit,
1562 DL, MVT::f32, Out64);
1564 if (InVT == MVT::f32 && ResVT == MVT::i32) {
1565 SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::f64);
1566 SDValue In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_32bit, DL,
1567 MVT::f64, SDValue(U64, 0), In);
1568 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::i64, In64);
1569 SDValue Shift = DAG.getNode(ISD::SRL, DL, MVT::i64, Out64, Shift32);
1570 SDValue Out = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Shift);
1573 llvm_unreachable("Unexpected bitcast combination");
1576 SDValue SystemZTargetLowering::lowerVASTART(SDValue Op,
1577 SelectionDAG &DAG) const {
1578 MachineFunction &MF = DAG.getMachineFunction();
1579 SystemZMachineFunctionInfo *FuncInfo =
1580 MF.getInfo<SystemZMachineFunctionInfo>();
1581 EVT PtrVT = getPointerTy();
1583 SDValue Chain = Op.getOperand(0);
1584 SDValue Addr = Op.getOperand(1);
1585 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1588 // The initial values of each field.
1589 const unsigned NumFields = 4;
1590 SDValue Fields[NumFields] = {
1591 DAG.getConstant(FuncInfo->getVarArgsFirstGPR(), PtrVT),
1592 DAG.getConstant(FuncInfo->getVarArgsFirstFPR(), PtrVT),
1593 DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT),
1594 DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT)
1597 // Store each field into its respective slot.
1598 SDValue MemOps[NumFields];
1599 unsigned Offset = 0;
1600 for (unsigned I = 0; I < NumFields; ++I) {
1601 SDValue FieldAddr = Addr;
1603 FieldAddr = DAG.getNode(ISD::ADD, DL, PtrVT, FieldAddr,
1604 DAG.getIntPtrConstant(Offset));
1605 MemOps[I] = DAG.getStore(Chain, DL, Fields[I], FieldAddr,
1606 MachinePointerInfo(SV, Offset),
1610 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps, NumFields);
1613 SDValue SystemZTargetLowering::lowerVACOPY(SDValue Op,
1614 SelectionDAG &DAG) const {
1615 SDValue Chain = Op.getOperand(0);
1616 SDValue DstPtr = Op.getOperand(1);
1617 SDValue SrcPtr = Op.getOperand(2);
1618 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
1619 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
1622 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, DAG.getIntPtrConstant(32),
1623 /*Align*/8, /*isVolatile*/false, /*AlwaysInline*/false,
1624 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
1627 SDValue SystemZTargetLowering::
1628 lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
1629 SDValue Chain = Op.getOperand(0);
1630 SDValue Size = Op.getOperand(1);
1633 unsigned SPReg = getStackPointerRegisterToSaveRestore();
1635 // Get a reference to the stack pointer.
1636 SDValue OldSP = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i64);
1638 // Get the new stack pointer value.
1639 SDValue NewSP = DAG.getNode(ISD::SUB, DL, MVT::i64, OldSP, Size);
1641 // Copy the new stack pointer back.
1642 Chain = DAG.getCopyToReg(Chain, DL, SPReg, NewSP);
1644 // The allocated data lives above the 160 bytes allocated for the standard
1645 // frame, plus any outgoing stack arguments. We don't know how much that
1646 // amounts to yet, so emit a special ADJDYNALLOC placeholder.
1647 SDValue ArgAdjust = DAG.getNode(SystemZISD::ADJDYNALLOC, DL, MVT::i64);
1648 SDValue Result = DAG.getNode(ISD::ADD, DL, MVT::i64, NewSP, ArgAdjust);
1650 SDValue Ops[2] = { Result, Chain };
1651 return DAG.getMergeValues(Ops, 2, DL);
1654 SDValue SystemZTargetLowering::lowerSMUL_LOHI(SDValue Op,
1655 SelectionDAG &DAG) const {
1656 EVT VT = Op.getValueType();
1660 // Just do a normal 64-bit multiplication and extract the results.
1661 // We define this so that it can be used for constant division.
1662 lowerMUL_LOHI32(DAG, DL, ISD::SIGN_EXTEND, Op.getOperand(0),
1663 Op.getOperand(1), Ops[1], Ops[0]);
1665 // Do a full 128-bit multiplication based on UMUL_LOHI64:
1667 // (ll * rl) + ((lh * rl) << 64) + ((ll * rh) << 64)
1669 // but using the fact that the upper halves are either all zeros
1672 // (ll * rl) - ((lh & rl) << 64) - ((ll & rh) << 64)
1674 // and grouping the right terms together since they are quicker than the
1677 // (ll * rl) - (((lh & rl) + (ll & rh)) << 64)
1678 SDValue C63 = DAG.getConstant(63, MVT::i64);
1679 SDValue LL = Op.getOperand(0);
1680 SDValue RL = Op.getOperand(1);
1681 SDValue LH = DAG.getNode(ISD::SRA, DL, VT, LL, C63);
1682 SDValue RH = DAG.getNode(ISD::SRA, DL, VT, RL, C63);
1683 // UMUL_LOHI64 returns the low result in the odd register and the high
1684 // result in the even register. SMUL_LOHI is defined to return the
1685 // low half first, so the results are in reverse order.
1686 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
1687 LL, RL, Ops[1], Ops[0]);
1688 SDValue NegLLTimesRH = DAG.getNode(ISD::AND, DL, VT, LL, RH);
1689 SDValue NegLHTimesRL = DAG.getNode(ISD::AND, DL, VT, LH, RL);
1690 SDValue NegSum = DAG.getNode(ISD::ADD, DL, VT, NegLLTimesRH, NegLHTimesRL);
1691 Ops[1] = DAG.getNode(ISD::SUB, DL, VT, Ops[1], NegSum);
1693 return DAG.getMergeValues(Ops, 2, DL);
1696 SDValue SystemZTargetLowering::lowerUMUL_LOHI(SDValue Op,
1697 SelectionDAG &DAG) const {
1698 EVT VT = Op.getValueType();
1702 // Just do a normal 64-bit multiplication and extract the results.
1703 // We define this so that it can be used for constant division.
1704 lowerMUL_LOHI32(DAG, DL, ISD::ZERO_EXTEND, Op.getOperand(0),
1705 Op.getOperand(1), Ops[1], Ops[0]);
1707 // UMUL_LOHI64 returns the low result in the odd register and the high
1708 // result in the even register. UMUL_LOHI is defined to return the
1709 // low half first, so the results are in reverse order.
1710 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
1711 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
1712 return DAG.getMergeValues(Ops, 2, DL);
1715 SDValue SystemZTargetLowering::lowerSDIVREM(SDValue Op,
1716 SelectionDAG &DAG) const {
1717 SDValue Op0 = Op.getOperand(0);
1718 SDValue Op1 = Op.getOperand(1);
1719 EVT VT = Op.getValueType();
1723 // We use DSGF for 32-bit division.
1725 Op0 = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op0);
1726 Opcode = SystemZISD::SDIVREM32;
1727 } else if (DAG.ComputeNumSignBits(Op1) > 32) {
1728 Op1 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op1);
1729 Opcode = SystemZISD::SDIVREM32;
1731 Opcode = SystemZISD::SDIVREM64;
1733 // DSG(F) takes a 64-bit dividend, so the even register in the GR128
1734 // input is "don't care". The instruction returns the remainder in
1735 // the even register and the quotient in the odd register.
1737 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, Opcode,
1738 Op0, Op1, Ops[1], Ops[0]);
1739 return DAG.getMergeValues(Ops, 2, DL);
1742 SDValue SystemZTargetLowering::lowerUDIVREM(SDValue Op,
1743 SelectionDAG &DAG) const {
1744 EVT VT = Op.getValueType();
1747 // DL(G) uses a double-width dividend, so we need to clear the even
1748 // register in the GR128 input. The instruction returns the remainder
1749 // in the even register and the quotient in the odd register.
1752 lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_32, SystemZISD::UDIVREM32,
1753 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
1755 lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_64, SystemZISD::UDIVREM64,
1756 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
1757 return DAG.getMergeValues(Ops, 2, DL);
1760 SDValue SystemZTargetLowering::lowerOR(SDValue Op, SelectionDAG &DAG) const {
1761 assert(Op.getValueType() == MVT::i64 && "Should be 64-bit operation");
1763 // Get the known-zero masks for each operand.
1764 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1) };
1765 APInt KnownZero[2], KnownOne[2];
1766 DAG.ComputeMaskedBits(Ops[0], KnownZero[0], KnownOne[0]);
1767 DAG.ComputeMaskedBits(Ops[1], KnownZero[1], KnownOne[1]);
1769 // See if the upper 32 bits of one operand and the lower 32 bits of the
1770 // other are known zero. They are the low and high operands respectively.
1771 uint64_t Masks[] = { KnownZero[0].getZExtValue(),
1772 KnownZero[1].getZExtValue() };
1774 if ((Masks[0] >> 32) == 0xffffffff && uint32_t(Masks[1]) == 0xffffffff)
1776 else if ((Masks[1] >> 32) == 0xffffffff && uint32_t(Masks[0]) == 0xffffffff)
1781 SDValue LowOp = Ops[Low];
1782 SDValue HighOp = Ops[High];
1784 // If the high part is a constant, we're better off using IILH.
1785 if (HighOp.getOpcode() == ISD::Constant)
1788 // If the low part is a constant that is outside the range of LHI,
1789 // then we're better off using IILF.
1790 if (LowOp.getOpcode() == ISD::Constant) {
1791 int64_t Value = int32_t(cast<ConstantSDNode>(LowOp)->getZExtValue());
1792 if (!isInt<16>(Value))
1796 // Check whether the high part is an AND that doesn't change the
1797 // high 32 bits and just masks out low bits. We can skip it if so.
1798 if (HighOp.getOpcode() == ISD::AND &&
1799 HighOp.getOperand(1).getOpcode() == ISD::Constant) {
1800 ConstantSDNode *MaskNode = cast<ConstantSDNode>(HighOp.getOperand(1));
1801 uint64_t Mask = MaskNode->getZExtValue() | Masks[High];
1802 if ((Mask >> 32) == 0xffffffff)
1803 HighOp = HighOp.getOperand(0);
1806 // Take advantage of the fact that all GR32 operations only change the
1807 // low 32 bits by truncating Low to an i32 and inserting it directly
1808 // using a subreg. The interesting cases are those where the truncation
1811 SDValue Low32 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, LowOp);
1812 return DAG.getTargetInsertSubreg(SystemZ::subreg_32bit, DL,
1813 MVT::i64, HighOp, Low32);
1816 // Op is an 8-, 16-bit or 32-bit ATOMIC_LOAD_* operation. Lower the first
1817 // two into the fullword ATOMIC_LOADW_* operation given by Opcode.
1818 SDValue SystemZTargetLowering::lowerATOMIC_LOAD(SDValue Op,
1820 unsigned Opcode) const {
1821 AtomicSDNode *Node = cast<AtomicSDNode>(Op.getNode());
1823 // 32-bit operations need no code outside the main loop.
1824 EVT NarrowVT = Node->getMemoryVT();
1825 EVT WideVT = MVT::i32;
1826 if (NarrowVT == WideVT)
1829 int64_t BitSize = NarrowVT.getSizeInBits();
1830 SDValue ChainIn = Node->getChain();
1831 SDValue Addr = Node->getBasePtr();
1832 SDValue Src2 = Node->getVal();
1833 MachineMemOperand *MMO = Node->getMemOperand();
1835 EVT PtrVT = Addr.getValueType();
1837 // Convert atomic subtracts of constants into additions.
1838 if (Opcode == SystemZISD::ATOMIC_LOADW_SUB)
1839 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Src2)) {
1840 Opcode = SystemZISD::ATOMIC_LOADW_ADD;
1841 Src2 = DAG.getConstant(-Const->getSExtValue(), Src2.getValueType());
1844 // Get the address of the containing word.
1845 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
1846 DAG.getConstant(-4, PtrVT));
1848 // Get the number of bits that the word must be rotated left in order
1849 // to bring the field to the top bits of a GR32.
1850 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
1851 DAG.getConstant(3, PtrVT));
1852 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
1854 // Get the complementing shift amount, for rotating a field in the top
1855 // bits back to its proper position.
1856 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
1857 DAG.getConstant(0, WideVT), BitShift);
1859 // Extend the source operand to 32 bits and prepare it for the inner loop.
1860 // ATOMIC_SWAPW uses RISBG to rotate the field left, but all other
1861 // operations require the source to be shifted in advance. (This shift
1862 // can be folded if the source is constant.) For AND and NAND, the lower
1863 // bits must be set, while for other opcodes they should be left clear.
1864 if (Opcode != SystemZISD::ATOMIC_SWAPW)
1865 Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2,
1866 DAG.getConstant(32 - BitSize, WideVT));
1867 if (Opcode == SystemZISD::ATOMIC_LOADW_AND ||
1868 Opcode == SystemZISD::ATOMIC_LOADW_NAND)
1869 Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2,
1870 DAG.getConstant(uint32_t(-1) >> BitSize, WideVT));
1872 // Construct the ATOMIC_LOADW_* node.
1873 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
1874 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift,
1875 DAG.getConstant(BitSize, WideVT) };
1876 SDValue AtomicOp = DAG.getMemIntrinsicNode(Opcode, DL, VTList, Ops,
1877 array_lengthof(Ops),
1880 // Rotate the result of the final CS so that the field is in the lower
1881 // bits of a GR32, then truncate it.
1882 SDValue ResultShift = DAG.getNode(ISD::ADD, DL, WideVT, BitShift,
1883 DAG.getConstant(BitSize, WideVT));
1884 SDValue Result = DAG.getNode(ISD::ROTL, DL, WideVT, AtomicOp, ResultShift);
1886 SDValue RetOps[2] = { Result, AtomicOp.getValue(1) };
1887 return DAG.getMergeValues(RetOps, 2, DL);
1890 // Node is an 8- or 16-bit ATOMIC_CMP_SWAP operation. Lower the first two
1891 // into a fullword ATOMIC_CMP_SWAPW operation.
1892 SDValue SystemZTargetLowering::lowerATOMIC_CMP_SWAP(SDValue Op,
1893 SelectionDAG &DAG) const {
1894 AtomicSDNode *Node = cast<AtomicSDNode>(Op.getNode());
1896 // We have native support for 32-bit compare and swap.
1897 EVT NarrowVT = Node->getMemoryVT();
1898 EVT WideVT = MVT::i32;
1899 if (NarrowVT == WideVT)
1902 int64_t BitSize = NarrowVT.getSizeInBits();
1903 SDValue ChainIn = Node->getOperand(0);
1904 SDValue Addr = Node->getOperand(1);
1905 SDValue CmpVal = Node->getOperand(2);
1906 SDValue SwapVal = Node->getOperand(3);
1907 MachineMemOperand *MMO = Node->getMemOperand();
1909 EVT PtrVT = Addr.getValueType();
1911 // Get the address of the containing word.
1912 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
1913 DAG.getConstant(-4, PtrVT));
1915 // Get the number of bits that the word must be rotated left in order
1916 // to bring the field to the top bits of a GR32.
1917 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
1918 DAG.getConstant(3, PtrVT));
1919 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
1921 // Get the complementing shift amount, for rotating a field in the top
1922 // bits back to its proper position.
1923 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
1924 DAG.getConstant(0, WideVT), BitShift);
1926 // Construct the ATOMIC_CMP_SWAPW node.
1927 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
1928 SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift,
1929 NegBitShift, DAG.getConstant(BitSize, WideVT) };
1930 SDValue AtomicOp = DAG.getMemIntrinsicNode(SystemZISD::ATOMIC_CMP_SWAPW, DL,
1931 VTList, Ops, array_lengthof(Ops),
1936 SDValue SystemZTargetLowering::lowerSTACKSAVE(SDValue Op,
1937 SelectionDAG &DAG) const {
1938 MachineFunction &MF = DAG.getMachineFunction();
1939 MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
1940 return DAG.getCopyFromReg(Op.getOperand(0), SDLoc(Op),
1941 SystemZ::R15D, Op.getValueType());
1944 SDValue SystemZTargetLowering::lowerSTACKRESTORE(SDValue Op,
1945 SelectionDAG &DAG) const {
1946 MachineFunction &MF = DAG.getMachineFunction();
1947 MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
1948 return DAG.getCopyToReg(Op.getOperand(0), SDLoc(Op),
1949 SystemZ::R15D, Op.getOperand(1));
1952 SDValue SystemZTargetLowering::lowerPREFETCH(SDValue Op,
1953 SelectionDAG &DAG) const {
1954 bool IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
1956 // Just preserve the chain.
1957 return Op.getOperand(0);
1959 bool IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
1960 unsigned Code = IsWrite ? SystemZ::PFD_WRITE : SystemZ::PFD_READ;
1961 MemIntrinsicSDNode *Node = cast<MemIntrinsicSDNode>(Op.getNode());
1964 DAG.getConstant(Code, MVT::i32),
1967 return DAG.getMemIntrinsicNode(SystemZISD::PREFETCH, SDLoc(Op),
1968 Node->getVTList(), Ops, array_lengthof(Ops),
1969 Node->getMemoryVT(), Node->getMemOperand());
1972 SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
1973 SelectionDAG &DAG) const {
1974 switch (Op.getOpcode()) {
1976 return lowerBR_CC(Op, DAG);
1977 case ISD::SELECT_CC:
1978 return lowerSELECT_CC(Op, DAG);
1979 case ISD::GlobalAddress:
1980 return lowerGlobalAddress(cast<GlobalAddressSDNode>(Op), DAG);
1981 case ISD::GlobalTLSAddress:
1982 return lowerGlobalTLSAddress(cast<GlobalAddressSDNode>(Op), DAG);
1983 case ISD::BlockAddress:
1984 return lowerBlockAddress(cast<BlockAddressSDNode>(Op), DAG);
1985 case ISD::JumpTable:
1986 return lowerJumpTable(cast<JumpTableSDNode>(Op), DAG);
1987 case ISD::ConstantPool:
1988 return lowerConstantPool(cast<ConstantPoolSDNode>(Op), DAG);
1990 return lowerBITCAST(Op, DAG);
1992 return lowerVASTART(Op, DAG);
1994 return lowerVACOPY(Op, DAG);
1995 case ISD::DYNAMIC_STACKALLOC:
1996 return lowerDYNAMIC_STACKALLOC(Op, DAG);
1997 case ISD::SMUL_LOHI:
1998 return lowerSMUL_LOHI(Op, DAG);
1999 case ISD::UMUL_LOHI:
2000 return lowerUMUL_LOHI(Op, DAG);
2002 return lowerSDIVREM(Op, DAG);
2004 return lowerUDIVREM(Op, DAG);
2006 return lowerOR(Op, DAG);
2007 case ISD::ATOMIC_SWAP:
2008 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_SWAPW);
2009 case ISD::ATOMIC_LOAD_ADD:
2010 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_ADD);
2011 case ISD::ATOMIC_LOAD_SUB:
2012 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_SUB);
2013 case ISD::ATOMIC_LOAD_AND:
2014 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_AND);
2015 case ISD::ATOMIC_LOAD_OR:
2016 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_OR);
2017 case ISD::ATOMIC_LOAD_XOR:
2018 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_XOR);
2019 case ISD::ATOMIC_LOAD_NAND:
2020 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_NAND);
2021 case ISD::ATOMIC_LOAD_MIN:
2022 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_MIN);
2023 case ISD::ATOMIC_LOAD_MAX:
2024 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_MAX);
2025 case ISD::ATOMIC_LOAD_UMIN:
2026 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_UMIN);
2027 case ISD::ATOMIC_LOAD_UMAX:
2028 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_UMAX);
2029 case ISD::ATOMIC_CMP_SWAP:
2030 return lowerATOMIC_CMP_SWAP(Op, DAG);
2031 case ISD::STACKSAVE:
2032 return lowerSTACKSAVE(Op, DAG);
2033 case ISD::STACKRESTORE:
2034 return lowerSTACKRESTORE(Op, DAG);
2036 return lowerPREFETCH(Op, DAG);
2038 llvm_unreachable("Unexpected node to lower");
2042 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
2043 #define OPCODE(NAME) case SystemZISD::NAME: return "SystemZISD::" #NAME
2048 OPCODE(PCREL_WRAPPER);
2053 OPCODE(SELECT_CCMASK);
2054 OPCODE(ADJDYNALLOC);
2055 OPCODE(EXTRACT_ACCESS);
2056 OPCODE(UMUL_LOHI64);
2072 OPCODE(SEARCH_STRING);
2074 OPCODE(ATOMIC_SWAPW);
2075 OPCODE(ATOMIC_LOADW_ADD);
2076 OPCODE(ATOMIC_LOADW_SUB);
2077 OPCODE(ATOMIC_LOADW_AND);
2078 OPCODE(ATOMIC_LOADW_OR);
2079 OPCODE(ATOMIC_LOADW_XOR);
2080 OPCODE(ATOMIC_LOADW_NAND);
2081 OPCODE(ATOMIC_LOADW_MIN);
2082 OPCODE(ATOMIC_LOADW_MAX);
2083 OPCODE(ATOMIC_LOADW_UMIN);
2084 OPCODE(ATOMIC_LOADW_UMAX);
2085 OPCODE(ATOMIC_CMP_SWAPW);
2092 //===----------------------------------------------------------------------===//
2094 //===----------------------------------------------------------------------===//
2096 // Create a new basic block after MBB.
2097 static MachineBasicBlock *emitBlockAfter(MachineBasicBlock *MBB) {
2098 MachineFunction &MF = *MBB->getParent();
2099 MachineBasicBlock *NewMBB = MF.CreateMachineBasicBlock(MBB->getBasicBlock());
2100 MF.insert(llvm::next(MachineFunction::iterator(MBB)), NewMBB);
2104 // Split MBB after MI and return the new block (the one that contains
2105 // instructions after MI).
2106 static MachineBasicBlock *splitBlockAfter(MachineInstr *MI,
2107 MachineBasicBlock *MBB) {
2108 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
2109 NewMBB->splice(NewMBB->begin(), MBB,
2110 llvm::next(MachineBasicBlock::iterator(MI)),
2112 NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
2116 // Split MBB before MI and return the new block (the one that contains MI).
2117 static MachineBasicBlock *splitBlockBefore(MachineInstr *MI,
2118 MachineBasicBlock *MBB) {
2119 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
2120 NewMBB->splice(NewMBB->begin(), MBB, MI, MBB->end());
2121 NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
2125 // Force base value Base into a register before MI. Return the register.
2126 static unsigned forceReg(MachineInstr *MI, MachineOperand &Base,
2127 const SystemZInstrInfo *TII) {
2129 return Base.getReg();
2131 MachineBasicBlock *MBB = MI->getParent();
2132 MachineFunction &MF = *MBB->getParent();
2133 MachineRegisterInfo &MRI = MF.getRegInfo();
2135 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
2136 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LA), Reg)
2137 .addOperand(Base).addImm(0).addReg(0);
2141 // Implement EmitInstrWithCustomInserter for pseudo Select* instruction MI.
2143 SystemZTargetLowering::emitSelect(MachineInstr *MI,
2144 MachineBasicBlock *MBB) const {
2145 const SystemZInstrInfo *TII = TM.getInstrInfo();
2147 unsigned DestReg = MI->getOperand(0).getReg();
2148 unsigned TrueReg = MI->getOperand(1).getReg();
2149 unsigned FalseReg = MI->getOperand(2).getReg();
2150 unsigned CCValid = MI->getOperand(3).getImm();
2151 unsigned CCMask = MI->getOperand(4).getImm();
2152 DebugLoc DL = MI->getDebugLoc();
2154 MachineBasicBlock *StartMBB = MBB;
2155 MachineBasicBlock *JoinMBB = splitBlockBefore(MI, MBB);
2156 MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
2159 // BRC CCMask, JoinMBB
2160 // # fallthrough to FalseMBB
2162 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2163 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
2164 MBB->addSuccessor(JoinMBB);
2165 MBB->addSuccessor(FalseMBB);
2168 // # fallthrough to JoinMBB
2170 MBB->addSuccessor(JoinMBB);
2173 // %Result = phi [ %FalseReg, FalseMBB ], [ %TrueReg, StartMBB ]
2176 BuildMI(*MBB, MI, DL, TII->get(SystemZ::PHI), DestReg)
2177 .addReg(TrueReg).addMBB(StartMBB)
2178 .addReg(FalseReg).addMBB(FalseMBB);
2180 MI->eraseFromParent();
2184 // Implement EmitInstrWithCustomInserter for pseudo CondStore* instruction MI.
2185 // StoreOpcode is the store to use and Invert says whether the store should
2186 // happen when the condition is false rather than true. If a STORE ON
2187 // CONDITION is available, STOCOpcode is its opcode, otherwise it is 0.
2189 SystemZTargetLowering::emitCondStore(MachineInstr *MI,
2190 MachineBasicBlock *MBB,
2191 unsigned StoreOpcode, unsigned STOCOpcode,
2192 bool Invert) const {
2193 const SystemZInstrInfo *TII = TM.getInstrInfo();
2195 unsigned SrcReg = MI->getOperand(0).getReg();
2196 MachineOperand Base = MI->getOperand(1);
2197 int64_t Disp = MI->getOperand(2).getImm();
2198 unsigned IndexReg = MI->getOperand(3).getReg();
2199 unsigned CCValid = MI->getOperand(4).getImm();
2200 unsigned CCMask = MI->getOperand(5).getImm();
2201 DebugLoc DL = MI->getDebugLoc();
2203 StoreOpcode = TII->getOpcodeForOffset(StoreOpcode, Disp);
2205 // Use STOCOpcode if possible. We could use different store patterns in
2206 // order to avoid matching the index register, but the performance trade-offs
2207 // might be more complicated in that case.
2208 if (STOCOpcode && !IndexReg && TM.getSubtargetImpl()->hasLoadStoreOnCond()) {
2211 BuildMI(*MBB, MI, DL, TII->get(STOCOpcode))
2212 .addReg(SrcReg).addOperand(Base).addImm(Disp)
2213 .addImm(CCValid).addImm(CCMask);
2214 MI->eraseFromParent();
2218 // Get the condition needed to branch around the store.
2222 MachineBasicBlock *StartMBB = MBB;
2223 MachineBasicBlock *JoinMBB = splitBlockBefore(MI, MBB);
2224 MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
2227 // BRC CCMask, JoinMBB
2228 // # fallthrough to FalseMBB
2230 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2231 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
2232 MBB->addSuccessor(JoinMBB);
2233 MBB->addSuccessor(FalseMBB);
2236 // store %SrcReg, %Disp(%Index,%Base)
2237 // # fallthrough to JoinMBB
2239 BuildMI(MBB, DL, TII->get(StoreOpcode))
2240 .addReg(SrcReg).addOperand(Base).addImm(Disp).addReg(IndexReg);
2241 MBB->addSuccessor(JoinMBB);
2243 MI->eraseFromParent();
2247 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_LOAD{,W}_*
2248 // or ATOMIC_SWAP{,W} instruction MI. BinOpcode is the instruction that
2249 // performs the binary operation elided by "*", or 0 for ATOMIC_SWAP{,W}.
2250 // BitSize is the width of the field in bits, or 0 if this is a partword
2251 // ATOMIC_LOADW_* or ATOMIC_SWAPW instruction, in which case the bitsize
2252 // is one of the operands. Invert says whether the field should be
2253 // inverted after performing BinOpcode (e.g. for NAND).
2255 SystemZTargetLowering::emitAtomicLoadBinary(MachineInstr *MI,
2256 MachineBasicBlock *MBB,
2259 bool Invert) const {
2260 const SystemZInstrInfo *TII = TM.getInstrInfo();
2261 MachineFunction &MF = *MBB->getParent();
2262 MachineRegisterInfo &MRI = MF.getRegInfo();
2263 bool IsSubWord = (BitSize < 32);
2265 // Extract the operands. Base can be a register or a frame index.
2266 // Src2 can be a register or immediate.
2267 unsigned Dest = MI->getOperand(0).getReg();
2268 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
2269 int64_t Disp = MI->getOperand(2).getImm();
2270 MachineOperand Src2 = earlyUseOperand(MI->getOperand(3));
2271 unsigned BitShift = (IsSubWord ? MI->getOperand(4).getReg() : 0);
2272 unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0);
2273 DebugLoc DL = MI->getDebugLoc();
2275 BitSize = MI->getOperand(6).getImm();
2277 // Subword operations use 32-bit registers.
2278 const TargetRegisterClass *RC = (BitSize <= 32 ?
2279 &SystemZ::GR32BitRegClass :
2280 &SystemZ::GR64BitRegClass);
2281 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
2282 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
2284 // Get the right opcodes for the displacement.
2285 LOpcode = TII->getOpcodeForOffset(LOpcode, Disp);
2286 CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
2287 assert(LOpcode && CSOpcode && "Displacement out of range");
2289 // Create virtual registers for temporary results.
2290 unsigned OrigVal = MRI.createVirtualRegister(RC);
2291 unsigned OldVal = MRI.createVirtualRegister(RC);
2292 unsigned NewVal = (BinOpcode || IsSubWord ?
2293 MRI.createVirtualRegister(RC) : Src2.getReg());
2294 unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
2295 unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
2297 // Insert a basic block for the main loop.
2298 MachineBasicBlock *StartMBB = MBB;
2299 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
2300 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
2304 // %OrigVal = L Disp(%Base)
2305 // # fall through to LoopMMB
2307 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
2308 .addOperand(Base).addImm(Disp).addReg(0);
2309 MBB->addSuccessor(LoopMBB);
2312 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, LoopMBB ]
2313 // %RotatedOldVal = RLL %OldVal, 0(%BitShift)
2314 // %RotatedNewVal = OP %RotatedOldVal, %Src2
2315 // %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
2316 // %Dest = CS %OldVal, %NewVal, Disp(%Base)
2318 // # fall through to DoneMMB
2320 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
2321 .addReg(OrigVal).addMBB(StartMBB)
2322 .addReg(Dest).addMBB(LoopMBB);
2324 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
2325 .addReg(OldVal).addReg(BitShift).addImm(0);
2327 // Perform the operation normally and then invert every bit of the field.
2328 unsigned Tmp = MRI.createVirtualRegister(RC);
2329 BuildMI(MBB, DL, TII->get(BinOpcode), Tmp)
2330 .addReg(RotatedOldVal).addOperand(Src2);
2332 // XILF with the upper BitSize bits set.
2333 BuildMI(MBB, DL, TII->get(SystemZ::XILF32), RotatedNewVal)
2334 .addReg(Tmp).addImm(uint32_t(~0 << (32 - BitSize)));
2335 else if (BitSize == 32)
2336 // XILF with every bit set.
2337 BuildMI(MBB, DL, TII->get(SystemZ::XILF32), RotatedNewVal)
2338 .addReg(Tmp).addImm(~uint32_t(0));
2340 // Use LCGR and add -1 to the result, which is more compact than
2341 // an XILF, XILH pair.
2342 unsigned Tmp2 = MRI.createVirtualRegister(RC);
2343 BuildMI(MBB, DL, TII->get(SystemZ::LCGR), Tmp2).addReg(Tmp);
2344 BuildMI(MBB, DL, TII->get(SystemZ::AGHI), RotatedNewVal)
2345 .addReg(Tmp2).addImm(-1);
2347 } else if (BinOpcode)
2348 // A simply binary operation.
2349 BuildMI(MBB, DL, TII->get(BinOpcode), RotatedNewVal)
2350 .addReg(RotatedOldVal).addOperand(Src2);
2352 // Use RISBG to rotate Src2 into position and use it to replace the
2353 // field in RotatedOldVal.
2354 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedNewVal)
2355 .addReg(RotatedOldVal).addReg(Src2.getReg())
2356 .addImm(32).addImm(31 + BitSize).addImm(32 - BitSize);
2358 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
2359 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
2360 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
2361 .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
2362 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2363 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
2364 MBB->addSuccessor(LoopMBB);
2365 MBB->addSuccessor(DoneMBB);
2367 MI->eraseFromParent();
2371 // Implement EmitInstrWithCustomInserter for pseudo
2372 // ATOMIC_LOAD{,W}_{,U}{MIN,MAX} instruction MI. CompareOpcode is the
2373 // instruction that should be used to compare the current field with the
2374 // minimum or maximum value. KeepOldMask is the BRC condition-code mask
2375 // for when the current field should be kept. BitSize is the width of
2376 // the field in bits, or 0 if this is a partword ATOMIC_LOADW_* instruction.
2378 SystemZTargetLowering::emitAtomicLoadMinMax(MachineInstr *MI,
2379 MachineBasicBlock *MBB,
2380 unsigned CompareOpcode,
2381 unsigned KeepOldMask,
2382 unsigned BitSize) const {
2383 const SystemZInstrInfo *TII = TM.getInstrInfo();
2384 MachineFunction &MF = *MBB->getParent();
2385 MachineRegisterInfo &MRI = MF.getRegInfo();
2386 bool IsSubWord = (BitSize < 32);
2388 // Extract the operands. Base can be a register or a frame index.
2389 unsigned Dest = MI->getOperand(0).getReg();
2390 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
2391 int64_t Disp = MI->getOperand(2).getImm();
2392 unsigned Src2 = MI->getOperand(3).getReg();
2393 unsigned BitShift = (IsSubWord ? MI->getOperand(4).getReg() : 0);
2394 unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0);
2395 DebugLoc DL = MI->getDebugLoc();
2397 BitSize = MI->getOperand(6).getImm();
2399 // Subword operations use 32-bit registers.
2400 const TargetRegisterClass *RC = (BitSize <= 32 ?
2401 &SystemZ::GR32BitRegClass :
2402 &SystemZ::GR64BitRegClass);
2403 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
2404 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
2406 // Get the right opcodes for the displacement.
2407 LOpcode = TII->getOpcodeForOffset(LOpcode, Disp);
2408 CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
2409 assert(LOpcode && CSOpcode && "Displacement out of range");
2411 // Create virtual registers for temporary results.
2412 unsigned OrigVal = MRI.createVirtualRegister(RC);
2413 unsigned OldVal = MRI.createVirtualRegister(RC);
2414 unsigned NewVal = MRI.createVirtualRegister(RC);
2415 unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
2416 unsigned RotatedAltVal = (IsSubWord ? MRI.createVirtualRegister(RC) : Src2);
2417 unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
2419 // Insert 3 basic blocks for the loop.
2420 MachineBasicBlock *StartMBB = MBB;
2421 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
2422 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
2423 MachineBasicBlock *UseAltMBB = emitBlockAfter(LoopMBB);
2424 MachineBasicBlock *UpdateMBB = emitBlockAfter(UseAltMBB);
2428 // %OrigVal = L Disp(%Base)
2429 // # fall through to LoopMMB
2431 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
2432 .addOperand(Base).addImm(Disp).addReg(0);
2433 MBB->addSuccessor(LoopMBB);
2436 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, UpdateMBB ]
2437 // %RotatedOldVal = RLL %OldVal, 0(%BitShift)
2438 // CompareOpcode %RotatedOldVal, %Src2
2439 // BRC KeepOldMask, UpdateMBB
2441 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
2442 .addReg(OrigVal).addMBB(StartMBB)
2443 .addReg(Dest).addMBB(UpdateMBB);
2445 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
2446 .addReg(OldVal).addReg(BitShift).addImm(0);
2447 BuildMI(MBB, DL, TII->get(CompareOpcode))
2448 .addReg(RotatedOldVal).addReg(Src2);
2449 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2450 .addImm(SystemZ::CCMASK_ICMP).addImm(KeepOldMask).addMBB(UpdateMBB);
2451 MBB->addSuccessor(UpdateMBB);
2452 MBB->addSuccessor(UseAltMBB);
2455 // %RotatedAltVal = RISBG %RotatedOldVal, %Src2, 32, 31 + BitSize, 0
2456 // # fall through to UpdateMMB
2459 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedAltVal)
2460 .addReg(RotatedOldVal).addReg(Src2)
2461 .addImm(32).addImm(31 + BitSize).addImm(0);
2462 MBB->addSuccessor(UpdateMBB);
2465 // %RotatedNewVal = PHI [ %RotatedOldVal, LoopMBB ],
2466 // [ %RotatedAltVal, UseAltMBB ]
2467 // %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
2468 // %Dest = CS %OldVal, %NewVal, Disp(%Base)
2470 // # fall through to DoneMMB
2472 BuildMI(MBB, DL, TII->get(SystemZ::PHI), RotatedNewVal)
2473 .addReg(RotatedOldVal).addMBB(LoopMBB)
2474 .addReg(RotatedAltVal).addMBB(UseAltMBB);
2476 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
2477 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
2478 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
2479 .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
2480 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2481 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
2482 MBB->addSuccessor(LoopMBB);
2483 MBB->addSuccessor(DoneMBB);
2485 MI->eraseFromParent();
2489 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_CMP_SWAPW
2492 SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr *MI,
2493 MachineBasicBlock *MBB) const {
2494 const SystemZInstrInfo *TII = TM.getInstrInfo();
2495 MachineFunction &MF = *MBB->getParent();
2496 MachineRegisterInfo &MRI = MF.getRegInfo();
2498 // Extract the operands. Base can be a register or a frame index.
2499 unsigned Dest = MI->getOperand(0).getReg();
2500 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
2501 int64_t Disp = MI->getOperand(2).getImm();
2502 unsigned OrigCmpVal = MI->getOperand(3).getReg();
2503 unsigned OrigSwapVal = MI->getOperand(4).getReg();
2504 unsigned BitShift = MI->getOperand(5).getReg();
2505 unsigned NegBitShift = MI->getOperand(6).getReg();
2506 int64_t BitSize = MI->getOperand(7).getImm();
2507 DebugLoc DL = MI->getDebugLoc();
2509 const TargetRegisterClass *RC = &SystemZ::GR32BitRegClass;
2511 // Get the right opcodes for the displacement.
2512 unsigned LOpcode = TII->getOpcodeForOffset(SystemZ::L, Disp);
2513 unsigned CSOpcode = TII->getOpcodeForOffset(SystemZ::CS, Disp);
2514 assert(LOpcode && CSOpcode && "Displacement out of range");
2516 // Create virtual registers for temporary results.
2517 unsigned OrigOldVal = MRI.createVirtualRegister(RC);
2518 unsigned OldVal = MRI.createVirtualRegister(RC);
2519 unsigned CmpVal = MRI.createVirtualRegister(RC);
2520 unsigned SwapVal = MRI.createVirtualRegister(RC);
2521 unsigned StoreVal = MRI.createVirtualRegister(RC);
2522 unsigned RetryOldVal = MRI.createVirtualRegister(RC);
2523 unsigned RetryCmpVal = MRI.createVirtualRegister(RC);
2524 unsigned RetrySwapVal = MRI.createVirtualRegister(RC);
2526 // Insert 2 basic blocks for the loop.
2527 MachineBasicBlock *StartMBB = MBB;
2528 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
2529 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
2530 MachineBasicBlock *SetMBB = emitBlockAfter(LoopMBB);
2534 // %OrigOldVal = L Disp(%Base)
2535 // # fall through to LoopMMB
2537 BuildMI(MBB, DL, TII->get(LOpcode), OrigOldVal)
2538 .addOperand(Base).addImm(Disp).addReg(0);
2539 MBB->addSuccessor(LoopMBB);
2542 // %OldVal = phi [ %OrigOldVal, EntryBB ], [ %RetryOldVal, SetMBB ]
2543 // %CmpVal = phi [ %OrigCmpVal, EntryBB ], [ %RetryCmpVal, SetMBB ]
2544 // %SwapVal = phi [ %OrigSwapVal, EntryBB ], [ %RetrySwapVal, SetMBB ]
2545 // %Dest = RLL %OldVal, BitSize(%BitShift)
2546 // ^^ The low BitSize bits contain the field
2548 // %RetryCmpVal = RISBG32 %CmpVal, %Dest, 32, 63-BitSize, 0
2549 // ^^ Replace the upper 32-BitSize bits of the
2550 // comparison value with those that we loaded,
2551 // so that we can use a full word comparison.
2552 // CR %Dest, %RetryCmpVal
2554 // # Fall through to SetMBB
2556 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
2557 .addReg(OrigOldVal).addMBB(StartMBB)
2558 .addReg(RetryOldVal).addMBB(SetMBB);
2559 BuildMI(MBB, DL, TII->get(SystemZ::PHI), CmpVal)
2560 .addReg(OrigCmpVal).addMBB(StartMBB)
2561 .addReg(RetryCmpVal).addMBB(SetMBB);
2562 BuildMI(MBB, DL, TII->get(SystemZ::PHI), SwapVal)
2563 .addReg(OrigSwapVal).addMBB(StartMBB)
2564 .addReg(RetrySwapVal).addMBB(SetMBB);
2565 BuildMI(MBB, DL, TII->get(SystemZ::RLL), Dest)
2566 .addReg(OldVal).addReg(BitShift).addImm(BitSize);
2567 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetryCmpVal)
2568 .addReg(CmpVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
2569 BuildMI(MBB, DL, TII->get(SystemZ::CR))
2570 .addReg(Dest).addReg(RetryCmpVal);
2571 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2572 .addImm(SystemZ::CCMASK_ICMP)
2573 .addImm(SystemZ::CCMASK_CMP_NE).addMBB(DoneMBB);
2574 MBB->addSuccessor(DoneMBB);
2575 MBB->addSuccessor(SetMBB);
2578 // %RetrySwapVal = RISBG32 %SwapVal, %Dest, 32, 63-BitSize, 0
2579 // ^^ Replace the upper 32-BitSize bits of the new
2580 // value with those that we loaded.
2581 // %StoreVal = RLL %RetrySwapVal, -BitSize(%NegBitShift)
2582 // ^^ Rotate the new field to its proper position.
2583 // %RetryOldVal = CS %Dest, %StoreVal, Disp(%Base)
2585 // # fall through to ExitMMB
2587 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetrySwapVal)
2588 .addReg(SwapVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
2589 BuildMI(MBB, DL, TII->get(SystemZ::RLL), StoreVal)
2590 .addReg(RetrySwapVal).addReg(NegBitShift).addImm(-BitSize);
2591 BuildMI(MBB, DL, TII->get(CSOpcode), RetryOldVal)
2592 .addReg(OldVal).addReg(StoreVal).addOperand(Base).addImm(Disp);
2593 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2594 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
2595 MBB->addSuccessor(LoopMBB);
2596 MBB->addSuccessor(DoneMBB);
2598 MI->eraseFromParent();
2602 // Emit an extension from a GR32 or GR64 to a GR128. ClearEven is true
2603 // if the high register of the GR128 value must be cleared or false if
2604 // it's "don't care". SubReg is subreg_odd32 when extending a GR32
2605 // and subreg_odd when extending a GR64.
2607 SystemZTargetLowering::emitExt128(MachineInstr *MI,
2608 MachineBasicBlock *MBB,
2609 bool ClearEven, unsigned SubReg) const {
2610 const SystemZInstrInfo *TII = TM.getInstrInfo();
2611 MachineFunction &MF = *MBB->getParent();
2612 MachineRegisterInfo &MRI = MF.getRegInfo();
2613 DebugLoc DL = MI->getDebugLoc();
2615 unsigned Dest = MI->getOperand(0).getReg();
2616 unsigned Src = MI->getOperand(1).getReg();
2617 unsigned In128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
2619 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::IMPLICIT_DEF), In128);
2621 unsigned NewIn128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
2622 unsigned Zero64 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
2624 BuildMI(*MBB, MI, DL, TII->get(SystemZ::LLILL), Zero64)
2626 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), NewIn128)
2627 .addReg(In128).addReg(Zero64).addImm(SystemZ::subreg_high);
2630 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dest)
2631 .addReg(In128).addReg(Src).addImm(SubReg);
2633 MI->eraseFromParent();
2638 SystemZTargetLowering::emitMemMemWrapper(MachineInstr *MI,
2639 MachineBasicBlock *MBB,
2640 unsigned Opcode) const {
2641 const SystemZInstrInfo *TII = TM.getInstrInfo();
2642 MachineFunction &MF = *MBB->getParent();
2643 MachineRegisterInfo &MRI = MF.getRegInfo();
2644 DebugLoc DL = MI->getDebugLoc();
2646 MachineOperand DestBase = earlyUseOperand(MI->getOperand(0));
2647 uint64_t DestDisp = MI->getOperand(1).getImm();
2648 MachineOperand SrcBase = earlyUseOperand(MI->getOperand(2));
2649 uint64_t SrcDisp = MI->getOperand(3).getImm();
2650 uint64_t Length = MI->getOperand(4).getImm();
2652 // When generating more than one CLC, all but the last will need to
2653 // branch to the end when a difference is found.
2654 MachineBasicBlock *EndMBB = (Length > 256 && Opcode == SystemZ::CLC ?
2655 splitBlockAfter(MI, MBB) : 0);
2657 // Check for the loop form, in which operand 5 is the trip count.
2658 if (MI->getNumExplicitOperands() > 5) {
2659 bool HaveSingleBase = DestBase.isIdenticalTo(SrcBase);
2661 uint64_t StartCountReg = MI->getOperand(5).getReg();
2662 uint64_t StartSrcReg = forceReg(MI, SrcBase, TII);
2663 uint64_t StartDestReg = (HaveSingleBase ? StartSrcReg :
2664 forceReg(MI, DestBase, TII));
2666 const TargetRegisterClass *RC = &SystemZ::ADDR64BitRegClass;
2667 uint64_t ThisSrcReg = MRI.createVirtualRegister(RC);
2668 uint64_t ThisDestReg = (HaveSingleBase ? ThisSrcReg :
2669 MRI.createVirtualRegister(RC));
2670 uint64_t NextSrcReg = MRI.createVirtualRegister(RC);
2671 uint64_t NextDestReg = (HaveSingleBase ? NextSrcReg :
2672 MRI.createVirtualRegister(RC));
2674 RC = &SystemZ::GR64BitRegClass;
2675 uint64_t ThisCountReg = MRI.createVirtualRegister(RC);
2676 uint64_t NextCountReg = MRI.createVirtualRegister(RC);
2678 MachineBasicBlock *StartMBB = MBB;
2679 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
2680 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
2681 MachineBasicBlock *NextMBB = (EndMBB ? emitBlockAfter(LoopMBB) : LoopMBB);
2684 // # fall through to LoopMMB
2685 MBB->addSuccessor(LoopMBB);
2688 // %ThisDestReg = phi [ %StartDestReg, StartMBB ],
2689 // [ %NextDestReg, NextMBB ]
2690 // %ThisSrcReg = phi [ %StartSrcReg, StartMBB ],
2691 // [ %NextSrcReg, NextMBB ]
2692 // %ThisCountReg = phi [ %StartCountReg, StartMBB ],
2693 // [ %NextCountReg, NextMBB ]
2694 // ( PFD 2, 768+DestDisp(%ThisDestReg) )
2695 // Opcode DestDisp(256,%ThisDestReg), SrcDisp(%ThisSrcReg)
2698 // The prefetch is used only for MVC. The JLH is used only for CLC.
2701 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisDestReg)
2702 .addReg(StartDestReg).addMBB(StartMBB)
2703 .addReg(NextDestReg).addMBB(NextMBB);
2704 if (!HaveSingleBase)
2705 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisSrcReg)
2706 .addReg(StartSrcReg).addMBB(StartMBB)
2707 .addReg(NextSrcReg).addMBB(NextMBB);
2708 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisCountReg)
2709 .addReg(StartCountReg).addMBB(StartMBB)
2710 .addReg(NextCountReg).addMBB(NextMBB);
2711 if (Opcode == SystemZ::MVC)
2712 BuildMI(MBB, DL, TII->get(SystemZ::PFD))
2713 .addImm(SystemZ::PFD_WRITE)
2714 .addReg(ThisDestReg).addImm(DestDisp + 768).addReg(0);
2715 BuildMI(MBB, DL, TII->get(Opcode))
2716 .addReg(ThisDestReg).addImm(DestDisp).addImm(256)
2717 .addReg(ThisSrcReg).addImm(SrcDisp);
2719 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2720 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
2722 MBB->addSuccessor(EndMBB);
2723 MBB->addSuccessor(NextMBB);
2727 // %NextDestReg = LA 256(%ThisDestReg)
2728 // %NextSrcReg = LA 256(%ThisSrcReg)
2729 // %NextCountReg = AGHI %ThisCountReg, -1
2730 // CGHI %NextCountReg, 0
2732 // # fall through to DoneMMB
2734 // The AGHI, CGHI and JLH should be converted to BRCTG by later passes.
2737 BuildMI(MBB, DL, TII->get(SystemZ::LA), NextDestReg)
2738 .addReg(ThisDestReg).addImm(256).addReg(0);
2739 if (!HaveSingleBase)
2740 BuildMI(MBB, DL, TII->get(SystemZ::LA), NextSrcReg)
2741 .addReg(ThisSrcReg).addImm(256).addReg(0);
2742 BuildMI(MBB, DL, TII->get(SystemZ::AGHI), NextCountReg)
2743 .addReg(ThisCountReg).addImm(-1);
2744 BuildMI(MBB, DL, TII->get(SystemZ::CGHI))
2745 .addReg(NextCountReg).addImm(0);
2746 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2747 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
2749 MBB->addSuccessor(LoopMBB);
2750 MBB->addSuccessor(DoneMBB);
2752 DestBase = MachineOperand::CreateReg(NextDestReg, false);
2753 SrcBase = MachineOperand::CreateReg(NextSrcReg, false);
2757 // Handle any remaining bytes with straight-line code.
2758 while (Length > 0) {
2759 uint64_t ThisLength = std::min(Length, uint64_t(256));
2760 // The previous iteration might have created out-of-range displacements.
2761 // Apply them using LAY if so.
2762 if (!isUInt<12>(DestDisp)) {
2763 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
2764 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LAY), Reg)
2765 .addOperand(DestBase).addImm(DestDisp).addReg(0);
2766 DestBase = MachineOperand::CreateReg(Reg, false);
2769 if (!isUInt<12>(SrcDisp)) {
2770 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
2771 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LAY), Reg)
2772 .addOperand(SrcBase).addImm(SrcDisp).addReg(0);
2773 SrcBase = MachineOperand::CreateReg(Reg, false);
2776 BuildMI(*MBB, MI, DL, TII->get(Opcode))
2777 .addOperand(DestBase).addImm(DestDisp).addImm(ThisLength)
2778 .addOperand(SrcBase).addImm(SrcDisp);
2779 DestDisp += ThisLength;
2780 SrcDisp += ThisLength;
2781 Length -= ThisLength;
2782 // If there's another CLC to go, branch to the end if a difference
2784 if (EndMBB && Length > 0) {
2785 MachineBasicBlock *NextMBB = splitBlockBefore(MI, MBB);
2786 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2787 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
2789 MBB->addSuccessor(EndMBB);
2790 MBB->addSuccessor(NextMBB);
2795 MBB->addSuccessor(EndMBB);
2797 MBB->addLiveIn(SystemZ::CC);
2800 MI->eraseFromParent();
2804 // Decompose string pseudo-instruction MI into a loop that continually performs
2805 // Opcode until CC != 3.
2807 SystemZTargetLowering::emitStringWrapper(MachineInstr *MI,
2808 MachineBasicBlock *MBB,
2809 unsigned Opcode) const {
2810 const SystemZInstrInfo *TII = TM.getInstrInfo();
2811 MachineFunction &MF = *MBB->getParent();
2812 MachineRegisterInfo &MRI = MF.getRegInfo();
2813 DebugLoc DL = MI->getDebugLoc();
2815 uint64_t End1Reg = MI->getOperand(0).getReg();
2816 uint64_t Start1Reg = MI->getOperand(1).getReg();
2817 uint64_t Start2Reg = MI->getOperand(2).getReg();
2818 uint64_t CharReg = MI->getOperand(3).getReg();
2820 const TargetRegisterClass *RC = &SystemZ::GR64BitRegClass;
2821 uint64_t This1Reg = MRI.createVirtualRegister(RC);
2822 uint64_t This2Reg = MRI.createVirtualRegister(RC);
2823 uint64_t End2Reg = MRI.createVirtualRegister(RC);
2825 MachineBasicBlock *StartMBB = MBB;
2826 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
2827 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
2830 // # fall through to LoopMMB
2831 MBB->addSuccessor(LoopMBB);
2834 // %This1Reg = phi [ %Start1Reg, StartMBB ], [ %End1Reg, LoopMBB ]
2835 // %This2Reg = phi [ %Start2Reg, StartMBB ], [ %End2Reg, LoopMBB ]
2837 // %End1Reg, %End2Reg = CLST %This1Reg, %This2Reg -- uses R0W
2839 // # fall through to DoneMMB
2841 // The load of R0W can be hoisted by post-RA LICM.
2844 BuildMI(MBB, DL, TII->get(SystemZ::PHI), This1Reg)
2845 .addReg(Start1Reg).addMBB(StartMBB)
2846 .addReg(End1Reg).addMBB(LoopMBB);
2847 BuildMI(MBB, DL, TII->get(SystemZ::PHI), This2Reg)
2848 .addReg(Start2Reg).addMBB(StartMBB)
2849 .addReg(End2Reg).addMBB(LoopMBB);
2850 BuildMI(MBB, DL, TII->get(TargetOpcode::COPY), SystemZ::R0W).addReg(CharReg);
2851 BuildMI(MBB, DL, TII->get(Opcode))
2852 .addReg(End1Reg, RegState::Define).addReg(End2Reg, RegState::Define)
2853 .addReg(This1Reg).addReg(This2Reg);
2854 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2855 .addImm(SystemZ::CCMASK_ANY).addImm(SystemZ::CCMASK_3).addMBB(LoopMBB);
2856 MBB->addSuccessor(LoopMBB);
2857 MBB->addSuccessor(DoneMBB);
2859 DoneMBB->addLiveIn(SystemZ::CC);
2861 MI->eraseFromParent();
2865 MachineBasicBlock *SystemZTargetLowering::
2866 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const {
2867 switch (MI->getOpcode()) {
2868 case SystemZ::Select32:
2869 case SystemZ::SelectF32:
2870 case SystemZ::Select64:
2871 case SystemZ::SelectF64:
2872 case SystemZ::SelectF128:
2873 return emitSelect(MI, MBB);
2875 case SystemZ::CondStore8_32:
2876 return emitCondStore(MI, MBB, SystemZ::STC32, 0, false);
2877 case SystemZ::CondStore8_32Inv:
2878 return emitCondStore(MI, MBB, SystemZ::STC32, 0, true);
2879 case SystemZ::CondStore16_32:
2880 return emitCondStore(MI, MBB, SystemZ::STH32, 0, false);
2881 case SystemZ::CondStore16_32Inv:
2882 return emitCondStore(MI, MBB, SystemZ::STH32, 0, true);
2883 case SystemZ::CondStore32_32:
2884 return emitCondStore(MI, MBB, SystemZ::ST32, SystemZ::STOC32, false);
2885 case SystemZ::CondStore32_32Inv:
2886 return emitCondStore(MI, MBB, SystemZ::ST32, SystemZ::STOC32, true);
2887 case SystemZ::CondStore8:
2888 return emitCondStore(MI, MBB, SystemZ::STC, 0, false);
2889 case SystemZ::CondStore8Inv:
2890 return emitCondStore(MI, MBB, SystemZ::STC, 0, true);
2891 case SystemZ::CondStore16:
2892 return emitCondStore(MI, MBB, SystemZ::STH, 0, false);
2893 case SystemZ::CondStore16Inv:
2894 return emitCondStore(MI, MBB, SystemZ::STH, 0, true);
2895 case SystemZ::CondStore32:
2896 return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, false);
2897 case SystemZ::CondStore32Inv:
2898 return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, true);
2899 case SystemZ::CondStore64:
2900 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, false);
2901 case SystemZ::CondStore64Inv:
2902 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, true);
2903 case SystemZ::CondStoreF32:
2904 return emitCondStore(MI, MBB, SystemZ::STE, 0, false);
2905 case SystemZ::CondStoreF32Inv:
2906 return emitCondStore(MI, MBB, SystemZ::STE, 0, true);
2907 case SystemZ::CondStoreF64:
2908 return emitCondStore(MI, MBB, SystemZ::STD, 0, false);
2909 case SystemZ::CondStoreF64Inv:
2910 return emitCondStore(MI, MBB, SystemZ::STD, 0, true);
2912 case SystemZ::AEXT128_64:
2913 return emitExt128(MI, MBB, false, SystemZ::subreg_low);
2914 case SystemZ::ZEXT128_32:
2915 return emitExt128(MI, MBB, true, SystemZ::subreg_low32);
2916 case SystemZ::ZEXT128_64:
2917 return emitExt128(MI, MBB, true, SystemZ::subreg_low);
2919 case SystemZ::ATOMIC_SWAPW:
2920 return emitAtomicLoadBinary(MI, MBB, 0, 0);
2921 case SystemZ::ATOMIC_SWAP_32:
2922 return emitAtomicLoadBinary(MI, MBB, 0, 32);
2923 case SystemZ::ATOMIC_SWAP_64:
2924 return emitAtomicLoadBinary(MI, MBB, 0, 64);
2926 case SystemZ::ATOMIC_LOADW_AR:
2927 return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 0);
2928 case SystemZ::ATOMIC_LOADW_AFI:
2929 return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 0);
2930 case SystemZ::ATOMIC_LOAD_AR:
2931 return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 32);
2932 case SystemZ::ATOMIC_LOAD_AHI:
2933 return emitAtomicLoadBinary(MI, MBB, SystemZ::AHI, 32);
2934 case SystemZ::ATOMIC_LOAD_AFI:
2935 return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 32);
2936 case SystemZ::ATOMIC_LOAD_AGR:
2937 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGR, 64);
2938 case SystemZ::ATOMIC_LOAD_AGHI:
2939 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGHI, 64);
2940 case SystemZ::ATOMIC_LOAD_AGFI:
2941 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGFI, 64);
2943 case SystemZ::ATOMIC_LOADW_SR:
2944 return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 0);
2945 case SystemZ::ATOMIC_LOAD_SR:
2946 return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 32);
2947 case SystemZ::ATOMIC_LOAD_SGR:
2948 return emitAtomicLoadBinary(MI, MBB, SystemZ::SGR, 64);
2950 case SystemZ::ATOMIC_LOADW_NR:
2951 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0);
2952 case SystemZ::ATOMIC_LOADW_NILH:
2953 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH32, 0);
2954 case SystemZ::ATOMIC_LOAD_NR:
2955 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32);
2956 case SystemZ::ATOMIC_LOAD_NILL32:
2957 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL32, 32);
2958 case SystemZ::ATOMIC_LOAD_NILH32:
2959 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH32, 32);
2960 case SystemZ::ATOMIC_LOAD_NILF32:
2961 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF32, 32);
2962 case SystemZ::ATOMIC_LOAD_NGR:
2963 return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64);
2964 case SystemZ::ATOMIC_LOAD_NILL:
2965 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 64);
2966 case SystemZ::ATOMIC_LOAD_NILH:
2967 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 64);
2968 case SystemZ::ATOMIC_LOAD_NIHL:
2969 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL, 64);
2970 case SystemZ::ATOMIC_LOAD_NIHH:
2971 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH, 64);
2972 case SystemZ::ATOMIC_LOAD_NILF:
2973 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 64);
2974 case SystemZ::ATOMIC_LOAD_NIHF:
2975 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF, 64);
2977 case SystemZ::ATOMIC_LOADW_OR:
2978 return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 0);
2979 case SystemZ::ATOMIC_LOADW_OILH:
2980 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH32, 0);
2981 case SystemZ::ATOMIC_LOAD_OR:
2982 return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 32);
2983 case SystemZ::ATOMIC_LOAD_OILL32:
2984 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL32, 32);
2985 case SystemZ::ATOMIC_LOAD_OILH32:
2986 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH32, 32);
2987 case SystemZ::ATOMIC_LOAD_OILF32:
2988 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF32, 32);
2989 case SystemZ::ATOMIC_LOAD_OGR:
2990 return emitAtomicLoadBinary(MI, MBB, SystemZ::OGR, 64);
2991 case SystemZ::ATOMIC_LOAD_OILL:
2992 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL, 64);
2993 case SystemZ::ATOMIC_LOAD_OILH:
2994 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 64);
2995 case SystemZ::ATOMIC_LOAD_OIHL:
2996 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHL, 64);
2997 case SystemZ::ATOMIC_LOAD_OIHH:
2998 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHH, 64);
2999 case SystemZ::ATOMIC_LOAD_OILF:
3000 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF, 64);
3001 case SystemZ::ATOMIC_LOAD_OIHF:
3002 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHF, 64);
3004 case SystemZ::ATOMIC_LOADW_XR:
3005 return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 0);
3006 case SystemZ::ATOMIC_LOADW_XILF:
3007 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF32, 0);
3008 case SystemZ::ATOMIC_LOAD_XR:
3009 return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 32);
3010 case SystemZ::ATOMIC_LOAD_XILF32:
3011 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF32, 32);
3012 case SystemZ::ATOMIC_LOAD_XGR:
3013 return emitAtomicLoadBinary(MI, MBB, SystemZ::XGR, 64);
3014 case SystemZ::ATOMIC_LOAD_XILF:
3015 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 64);
3016 case SystemZ::ATOMIC_LOAD_XIHF:
3017 return emitAtomicLoadBinary(MI, MBB, SystemZ::XIHF, 64);
3019 case SystemZ::ATOMIC_LOADW_NRi:
3020 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0, true);
3021 case SystemZ::ATOMIC_LOADW_NILHi:
3022 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH32, 0, true);
3023 case SystemZ::ATOMIC_LOAD_NRi:
3024 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32, true);
3025 case SystemZ::ATOMIC_LOAD_NILL32i:
3026 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL32, 32, true);
3027 case SystemZ::ATOMIC_LOAD_NILH32i:
3028 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH32, 32, true);
3029 case SystemZ::ATOMIC_LOAD_NILF32i:
3030 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF32, 32, true);
3031 case SystemZ::ATOMIC_LOAD_NGRi:
3032 return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64, true);
3033 case SystemZ::ATOMIC_LOAD_NILLi:
3034 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 64, true);
3035 case SystemZ::ATOMIC_LOAD_NILHi:
3036 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 64, true);
3037 case SystemZ::ATOMIC_LOAD_NIHLi:
3038 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL, 64, true);
3039 case SystemZ::ATOMIC_LOAD_NIHHi:
3040 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH, 64, true);
3041 case SystemZ::ATOMIC_LOAD_NILFi:
3042 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 64, true);
3043 case SystemZ::ATOMIC_LOAD_NIHFi:
3044 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF, 64, true);
3046 case SystemZ::ATOMIC_LOADW_MIN:
3047 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
3048 SystemZ::CCMASK_CMP_LE, 0);
3049 case SystemZ::ATOMIC_LOAD_MIN_32:
3050 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
3051 SystemZ::CCMASK_CMP_LE, 32);
3052 case SystemZ::ATOMIC_LOAD_MIN_64:
3053 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
3054 SystemZ::CCMASK_CMP_LE, 64);
3056 case SystemZ::ATOMIC_LOADW_MAX:
3057 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
3058 SystemZ::CCMASK_CMP_GE, 0);
3059 case SystemZ::ATOMIC_LOAD_MAX_32:
3060 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
3061 SystemZ::CCMASK_CMP_GE, 32);
3062 case SystemZ::ATOMIC_LOAD_MAX_64:
3063 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
3064 SystemZ::CCMASK_CMP_GE, 64);
3066 case SystemZ::ATOMIC_LOADW_UMIN:
3067 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
3068 SystemZ::CCMASK_CMP_LE, 0);
3069 case SystemZ::ATOMIC_LOAD_UMIN_32:
3070 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
3071 SystemZ::CCMASK_CMP_LE, 32);
3072 case SystemZ::ATOMIC_LOAD_UMIN_64:
3073 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
3074 SystemZ::CCMASK_CMP_LE, 64);
3076 case SystemZ::ATOMIC_LOADW_UMAX:
3077 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
3078 SystemZ::CCMASK_CMP_GE, 0);
3079 case SystemZ::ATOMIC_LOAD_UMAX_32:
3080 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
3081 SystemZ::CCMASK_CMP_GE, 32);
3082 case SystemZ::ATOMIC_LOAD_UMAX_64:
3083 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
3084 SystemZ::CCMASK_CMP_GE, 64);
3086 case SystemZ::ATOMIC_CMP_SWAPW:
3087 return emitAtomicCmpSwapW(MI, MBB);
3088 case SystemZ::MVCSequence:
3089 case SystemZ::MVCLoop:
3090 return emitMemMemWrapper(MI, MBB, SystemZ::MVC);
3091 case SystemZ::NCSequence:
3092 case SystemZ::NCLoop:
3093 return emitMemMemWrapper(MI, MBB, SystemZ::NC);
3094 case SystemZ::OCSequence:
3095 case SystemZ::OCLoop:
3096 return emitMemMemWrapper(MI, MBB, SystemZ::OC);
3097 case SystemZ::XCSequence:
3098 case SystemZ::XCLoop:
3099 return emitMemMemWrapper(MI, MBB, SystemZ::XC);
3100 case SystemZ::CLCSequence:
3101 case SystemZ::CLCLoop:
3102 return emitMemMemWrapper(MI, MBB, SystemZ::CLC);
3103 case SystemZ::CLSTLoop:
3104 return emitStringWrapper(MI, MBB, SystemZ::CLST);
3105 case SystemZ::MVSTLoop:
3106 return emitStringWrapper(MI, MBB, SystemZ::MVST);
3107 case SystemZ::SRSTLoop:
3108 return emitStringWrapper(MI, MBB, SystemZ::SRST);
3110 llvm_unreachable("Unexpected instr type to insert");