1 //===-- SystemZISelLowering.cpp - SystemZ DAG Lowering Implementation -----==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SystemZTargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "systemz-lower"
16 #include "SystemZISelLowering.h"
18 #include "SystemZTargetMachine.h"
19 #include "SystemZSubtarget.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/PseudoSourceValue.h"
32 #include "llvm/CodeGen/SelectionDAGISel.h"
33 #include "llvm/CodeGen/ValueTypes.h"
34 #include "llvm/Target/TargetOptions.h"
35 #include "llvm/Target/TargetLoweringObjectFile.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/ADT/VectorExtras.h"
40 SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
41 TargetLowering(tm, new TargetLoweringObjectFileELF()),
42 Subtarget(*tm.getSubtargetImpl()), TM(tm) {
44 RegInfo = TM.getRegisterInfo();
46 // Set up the register classes.
47 addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass);
48 addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass);
49 addRegisterClass(MVT::v2i32,SystemZ::GR64PRegisterClass);
50 addRegisterClass(MVT::v2i64,SystemZ::GR128RegisterClass);
53 addRegisterClass(MVT::f32, SystemZ::FP32RegisterClass);
54 addRegisterClass(MVT::f64, SystemZ::FP64RegisterClass);
56 addLegalFPImmediate(APFloat(+0.0)); // lzer
57 addLegalFPImmediate(APFloat(+0.0f)); // lzdr
58 addLegalFPImmediate(APFloat(-0.0)); // lzer + lner
59 addLegalFPImmediate(APFloat(-0.0f)); // lzdr + lndr
62 // Compute derived properties from the register classes
63 computeRegisterProperties();
65 // Set shifts properties
66 setShiftAmountType(MVT::i64);
68 // Provide all sorts of operation actions
69 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
70 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
71 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
73 setLoadExtAction(ISD::SEXTLOAD, MVT::f32, Expand);
74 setLoadExtAction(ISD::ZEXTLOAD, MVT::f32, Expand);
75 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
77 setLoadExtAction(ISD::SEXTLOAD, MVT::f64, Expand);
78 setLoadExtAction(ISD::ZEXTLOAD, MVT::f64, Expand);
79 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
81 setStackPointerRegisterToSaveRestore(SystemZ::R15D);
82 setSchedulingPreference(SchedulingForLatency);
83 setBooleanContents(ZeroOrOneBooleanContent);
85 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
86 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
87 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
88 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
89 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
90 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
91 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
92 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
93 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
94 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
95 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
97 setOperationAction(ISD::SDIV, MVT::i32, Expand);
98 setOperationAction(ISD::UDIV, MVT::i32, Expand);
99 setOperationAction(ISD::SDIV, MVT::i64, Expand);
100 setOperationAction(ISD::UDIV, MVT::i64, Expand);
101 setOperationAction(ISD::SREM, MVT::i32, Expand);
102 setOperationAction(ISD::UREM, MVT::i32, Expand);
103 setOperationAction(ISD::SREM, MVT::i64, Expand);
104 setOperationAction(ISD::UREM, MVT::i64, Expand);
106 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
108 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
109 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
110 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
111 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
112 setOperationAction(ISD::CTLZ, MVT::i32, Promote);
113 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
115 // FIXME: Can we lower these 2 efficiently?
116 setOperationAction(ISD::SETCC, MVT::i32, Expand);
117 setOperationAction(ISD::SETCC, MVT::i64, Expand);
118 setOperationAction(ISD::SETCC, MVT::f32, Expand);
119 setOperationAction(ISD::SETCC, MVT::f64, Expand);
120 setOperationAction(ISD::SELECT, MVT::i32, Expand);
121 setOperationAction(ISD::SELECT, MVT::i64, Expand);
122 setOperationAction(ISD::SELECT, MVT::f32, Expand);
123 setOperationAction(ISD::SELECT, MVT::f64, Expand);
124 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
125 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
126 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
127 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
129 setOperationAction(ISD::MULHS, MVT::i64, Expand);
130 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
132 // FIXME: Can we support these natively?
133 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
134 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
135 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
136 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
138 // Lower some FP stuff
139 setOperationAction(ISD::FSIN, MVT::f32, Expand);
140 setOperationAction(ISD::FSIN, MVT::f64, Expand);
141 setOperationAction(ISD::FCOS, MVT::f32, Expand);
142 setOperationAction(ISD::FCOS, MVT::f64, Expand);
143 setOperationAction(ISD::FREM, MVT::f32, Expand);
144 setOperationAction(ISD::FREM, MVT::f64, Expand);
146 // We have only 64-bit bitconverts
147 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
148 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
150 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
151 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
152 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
153 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
155 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
158 SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
159 switch (Op.getOpcode()) {
160 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
161 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
162 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
163 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
164 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
166 llvm_unreachable("Should not custom lower this!");
171 //===----------------------------------------------------------------------===//
172 // SystemZ Inline Assembly Support
173 //===----------------------------------------------------------------------===//
175 /// getConstraintType - Given a constraint letter, return the type of
176 /// constraint it is for this target.
177 TargetLowering::ConstraintType
178 SystemZTargetLowering::getConstraintType(const std::string &Constraint) const {
179 if (Constraint.size() == 1) {
180 switch (Constraint[0]) {
182 return C_RegisterClass;
187 return TargetLowering::getConstraintType(Constraint);
190 std::pair<unsigned, const TargetRegisterClass*>
191 SystemZTargetLowering::
192 getRegForInlineAsmConstraint(const std::string &Constraint,
194 if (Constraint.size() == 1) {
195 // GCC Constraint Letters
196 switch (Constraint[0]) {
198 case 'r': // GENERAL_REGS
200 return std::make_pair(0U, SystemZ::GR32RegisterClass);
201 else if (VT == MVT::i128)
202 return std::make_pair(0U, SystemZ::GR128RegisterClass);
204 return std::make_pair(0U, SystemZ::GR64RegisterClass);
208 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
211 //===----------------------------------------------------------------------===//
212 // Calling Convention Implementation
213 //===----------------------------------------------------------------------===//
215 #include "SystemZGenCallingConv.inc"
218 SystemZTargetLowering::LowerFormalArguments(SDValue Chain,
221 const SmallVectorImpl<ISD::InputArg>
225 SmallVectorImpl<SDValue> &InVals) {
229 llvm_unreachable("Unsupported calling convention");
231 case CallingConv::Fast:
232 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
237 SystemZTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
238 unsigned CallConv, bool isVarArg,
240 const SmallVectorImpl<ISD::OutputArg> &Outs,
241 const SmallVectorImpl<ISD::InputArg> &Ins,
242 DebugLoc dl, SelectionDAG &DAG,
243 SmallVectorImpl<SDValue> &InVals) {
247 llvm_unreachable("Unsupported calling convention");
248 case CallingConv::Fast:
250 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
251 Outs, Ins, dl, DAG, InVals);
255 /// LowerCCCArguments - transform physical registers into virtual registers and
256 /// generate load operations for arguments places on the stack.
257 // FIXME: struct return stuff
260 SystemZTargetLowering::LowerCCCArguments(SDValue Chain,
263 const SmallVectorImpl<ISD::InputArg>
267 SmallVectorImpl<SDValue> &InVals) {
269 MachineFunction &MF = DAG.getMachineFunction();
270 MachineFrameInfo *MFI = MF.getFrameInfo();
271 MachineRegisterInfo &RegInfo = MF.getRegInfo();
273 // Assign locations to all of the incoming arguments.
274 SmallVector<CCValAssign, 16> ArgLocs;
275 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
276 ArgLocs, *DAG.getContext());
277 CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ);
280 llvm_report_error("Varargs not supported yet");
282 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
284 CCValAssign &VA = ArgLocs[i];
285 EVT LocVT = VA.getLocVT();
287 // Arguments passed in registers
288 TargetRegisterClass *RC;
289 switch (LocVT.getSimpleVT().SimpleTy) {
292 cerr << "LowerFormalArguments Unhandled argument type: "
293 << LocVT.getSimpleVT().SimpleTy
298 RC = SystemZ::GR64RegisterClass;
301 RC = SystemZ::FP32RegisterClass;
304 RC = SystemZ::FP64RegisterClass;
308 unsigned VReg = RegInfo.createVirtualRegister(RC);
309 RegInfo.addLiveIn(VA.getLocReg(), VReg);
310 ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, LocVT);
313 assert(VA.isMemLoc());
315 // Create the nodes corresponding to a load from this parameter slot.
316 // Create the frame index object for this incoming parameter...
317 int FI = MFI->CreateFixedObject(LocVT.getSizeInBits()/8,
318 VA.getLocMemOffset());
320 // Create the SelectionDAG nodes corresponding to a load
321 // from this parameter
322 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
323 ArgValue = DAG.getLoad(LocVT, dl, Chain, FIN,
324 PseudoSourceValue::getFixedStack(FI), 0);
327 // If this is an 8/16/32-bit value, it is really passed promoted to 64
328 // bits. Insert an assert[sz]ext to capture this, then truncate to the
330 if (VA.getLocInfo() == CCValAssign::SExt)
331 ArgValue = DAG.getNode(ISD::AssertSext, dl, LocVT, ArgValue,
332 DAG.getValueType(VA.getValVT()));
333 else if (VA.getLocInfo() == CCValAssign::ZExt)
334 ArgValue = DAG.getNode(ISD::AssertZext, dl, LocVT, ArgValue,
335 DAG.getValueType(VA.getValVT()));
337 if (VA.getLocInfo() != CCValAssign::Full)
338 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
340 InVals.push_back(ArgValue);
346 /// LowerCCCCallTo - functions arguments are copied from virtual regs to
347 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
350 SystemZTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
351 unsigned CallConv, bool isVarArg,
353 const SmallVectorImpl<ISD::OutputArg>
355 const SmallVectorImpl<ISD::InputArg> &Ins,
356 DebugLoc dl, SelectionDAG &DAG,
357 SmallVectorImpl<SDValue> &InVals) {
359 MachineFunction &MF = DAG.getMachineFunction();
361 // Offset to first argument stack slot.
362 const unsigned FirstArgOffset = 160;
364 // Analyze operands of the call, assigning locations to each operand.
365 SmallVector<CCValAssign, 16> ArgLocs;
366 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
367 ArgLocs, *DAG.getContext());
369 CCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
371 // Get a count of how many bytes are to be pushed on the stack.
372 unsigned NumBytes = CCInfo.getNextStackOffset();
374 Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
375 getPointerTy(), true));
377 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
378 SmallVector<SDValue, 12> MemOpChains;
381 // Walk the register/memloc assignments, inserting copies/loads.
382 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
383 CCValAssign &VA = ArgLocs[i];
385 SDValue Arg = Outs[i].Val;
387 // Promote the value if needed.
388 switch (VA.getLocInfo()) {
389 default: assert(0 && "Unknown loc info!");
390 case CCValAssign::Full: break;
391 case CCValAssign::SExt:
392 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
394 case CCValAssign::ZExt:
395 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
397 case CCValAssign::AExt:
398 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
402 // Arguments that can be passed on register must be kept at RegsToPass
405 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
407 assert(VA.isMemLoc());
409 if (StackPtr.getNode() == 0)
411 DAG.getCopyFromReg(Chain, dl,
412 (RegInfo->hasFP(MF) ?
413 SystemZ::R11D : SystemZ::R15D),
416 unsigned Offset = FirstArgOffset + VA.getLocMemOffset();
417 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
419 DAG.getIntPtrConstant(Offset));
421 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
422 PseudoSourceValue::getStack(), Offset));
426 // Transform all store nodes into one single node because all store nodes are
427 // independent of each other.
428 if (!MemOpChains.empty())
429 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
430 &MemOpChains[0], MemOpChains.size());
432 // Build a sequence of copy-to-reg nodes chained together with token chain and
433 // flag operands which copy the outgoing args into registers. The InFlag in
434 // necessary since all emited instructions must be stuck together.
436 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
437 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
438 RegsToPass[i].second, InFlag);
439 InFlag = Chain.getValue(1);
442 // If the callee is a GlobalAddress node (quite common, every direct call is)
443 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
444 // Likewise ExternalSymbol -> TargetExternalSymbol.
445 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
446 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
447 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
448 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy());
450 // Returns a chain & a flag for retval copy to use.
451 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
452 SmallVector<SDValue, 8> Ops;
453 Ops.push_back(Chain);
454 Ops.push_back(Callee);
456 // Add argument registers to the end of the list so that they are
457 // known live into the call.
458 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
459 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
460 RegsToPass[i].second.getValueType()));
462 if (InFlag.getNode())
463 Ops.push_back(InFlag);
465 Chain = DAG.getNode(SystemZISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
466 InFlag = Chain.getValue(1);
468 // Create the CALLSEQ_END node.
469 Chain = DAG.getCALLSEQ_END(Chain,
470 DAG.getConstant(NumBytes, getPointerTy(), true),
471 DAG.getConstant(0, getPointerTy(), true),
473 InFlag = Chain.getValue(1);
475 // Handle result values, copying them out of physregs into vregs that we
477 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
481 /// LowerCallResult - Lower the result values of a call into the
482 /// appropriate copies out of appropriate physical registers.
485 SystemZTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
486 unsigned CallConv, bool isVarArg,
487 const SmallVectorImpl<ISD::InputArg>
489 DebugLoc dl, SelectionDAG &DAG,
490 SmallVectorImpl<SDValue> &InVals) {
492 // Assign locations to each value returned by this call.
493 SmallVector<CCValAssign, 16> RVLocs;
494 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
497 CCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ);
499 // Copy all of the result registers out of their specified physreg.
500 for (unsigned i = 0; i != RVLocs.size(); ++i) {
501 CCValAssign &VA = RVLocs[i];
503 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
504 VA.getLocVT(), InFlag).getValue(1);
505 SDValue RetValue = Chain.getValue(0);
506 InFlag = Chain.getValue(2);
508 // If this is an 8/16/32-bit value, it is really passed promoted to 64
509 // bits. Insert an assert[sz]ext to capture this, then truncate to the
511 if (VA.getLocInfo() == CCValAssign::SExt)
512 RetValue = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), RetValue,
513 DAG.getValueType(VA.getValVT()));
514 else if (VA.getLocInfo() == CCValAssign::ZExt)
515 RetValue = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), RetValue,
516 DAG.getValueType(VA.getValVT()));
518 if (VA.getLocInfo() != CCValAssign::Full)
519 RetValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), RetValue);
521 InVals.push_back(RetValue);
529 SystemZTargetLowering::LowerReturn(SDValue Chain,
530 unsigned CallConv, bool isVarArg,
531 const SmallVectorImpl<ISD::OutputArg> &Outs,
532 DebugLoc dl, SelectionDAG &DAG) {
534 // CCValAssign - represent the assignment of the return value to a location
535 SmallVector<CCValAssign, 16> RVLocs;
537 // CCState - Info about the registers and stack slot.
538 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
539 RVLocs, *DAG.getContext());
541 // Analize return values.
542 CCInfo.AnalyzeReturn(Outs, RetCC_SystemZ);
544 // If this is the first return lowered for this function, add the regs to the
545 // liveout set for the function.
546 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
547 for (unsigned i = 0; i != RVLocs.size(); ++i)
548 if (RVLocs[i].isRegLoc())
549 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
554 // Copy the result values into the output registers.
555 for (unsigned i = 0; i != RVLocs.size(); ++i) {
556 CCValAssign &VA = RVLocs[i];
557 SDValue ResValue = Outs[i].Val;
558 assert(VA.isRegLoc() && "Can only return in registers!");
560 // If this is an 8/16/32-bit value, it is really should be passed promoted
562 if (VA.getLocInfo() == CCValAssign::SExt)
563 ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue);
564 else if (VA.getLocInfo() == CCValAssign::ZExt)
565 ResValue = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ResValue);
566 else if (VA.getLocInfo() == CCValAssign::AExt)
567 ResValue = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ResValue);
569 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ResValue, Flag);
571 // Guarantee that all emitted copies are stuck together,
572 // avoiding something bad.
573 Flag = Chain.getValue(1);
577 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
580 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain);
583 SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS,
584 ISD::CondCode CC, SDValue &SystemZCC,
586 // FIXME: Emit a test if RHS is zero
588 bool isUnsigned = false;
589 SystemZCC::CondCodes TCC;
592 llvm_unreachable("Invalid integer condition!");
598 TCC = SystemZCC::NLH;
614 if (LHS.getValueType().isFloatingPoint()) {
618 isUnsigned = true; // FALLTHROUGH
624 if (LHS.getValueType().isFloatingPoint()) {
628 isUnsigned = true; // FALLTHROUGH
634 if (LHS.getValueType().isFloatingPoint()) {
635 TCC = SystemZCC::NLE;
638 isUnsigned = true; // FALLTHROUGH
644 if (LHS.getValueType().isFloatingPoint()) {
645 TCC = SystemZCC::NHE;
648 isUnsigned = true; // FALLTHROUGH
655 SystemZCC = DAG.getConstant(TCC, MVT::i32);
657 DebugLoc dl = LHS.getDebugLoc();
658 return DAG.getNode((isUnsigned ? SystemZISD::UCMP : SystemZISD::CMP),
659 dl, MVT::Flag, LHS, RHS);
663 SDValue SystemZTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
664 SDValue Chain = Op.getOperand(0);
665 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
666 SDValue LHS = Op.getOperand(2);
667 SDValue RHS = Op.getOperand(3);
668 SDValue Dest = Op.getOperand(4);
669 DebugLoc dl = Op.getDebugLoc();
672 SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG);
673 return DAG.getNode(SystemZISD::BRCOND, dl, Op.getValueType(),
674 Chain, Dest, SystemZCC, Flag);
677 SDValue SystemZTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
678 SDValue LHS = Op.getOperand(0);
679 SDValue RHS = Op.getOperand(1);
680 SDValue TrueV = Op.getOperand(2);
681 SDValue FalseV = Op.getOperand(3);
682 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
683 DebugLoc dl = Op.getDebugLoc();
686 SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG);
688 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
689 SmallVector<SDValue, 4> Ops;
690 Ops.push_back(TrueV);
691 Ops.push_back(FalseV);
692 Ops.push_back(SystemZCC);
695 return DAG.getNode(SystemZISD::SELECT, dl, VTs, &Ops[0], Ops.size());
698 SDValue SystemZTargetLowering::LowerGlobalAddress(SDValue Op,
700 DebugLoc dl = Op.getDebugLoc();
701 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
702 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
704 bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_;
705 bool ExtraLoadRequired =
706 Subtarget.GVRequiresExtraLoad(GV, getTargetMachine(), false);
709 if (!IsPic && !ExtraLoadRequired) {
710 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
713 unsigned char OpFlags = 0;
714 if (ExtraLoadRequired)
715 OpFlags = SystemZII::MO_GOTENT;
717 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
720 Result = DAG.getNode(SystemZISD::PCRelativeWrapper, dl,
721 getPointerTy(), Result);
723 if (ExtraLoadRequired)
724 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
725 PseudoSourceValue::getGOT(), 0);
727 // If there was a non-zero offset that we didn't fold, create an explicit
730 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
731 DAG.getConstant(Offset, getPointerTy()));
737 SDValue SystemZTargetLowering::LowerJumpTable(SDValue Op,
739 DebugLoc dl = Op.getDebugLoc();
740 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
741 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
743 return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result);
748 // FIXME: This is just dirty hack. We need to lower cpool properly
749 SDValue SystemZTargetLowering::LowerConstantPool(SDValue Op,
751 DebugLoc dl = Op.getDebugLoc();
752 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
754 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
758 return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result);
761 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
763 case SystemZISD::RET_FLAG: return "SystemZISD::RET_FLAG";
764 case SystemZISD::CALL: return "SystemZISD::CALL";
765 case SystemZISD::BRCOND: return "SystemZISD::BRCOND";
766 case SystemZISD::CMP: return "SystemZISD::CMP";
767 case SystemZISD::UCMP: return "SystemZISD::UCMP";
768 case SystemZISD::SELECT: return "SystemZISD::SELECT";
769 case SystemZISD::PCRelativeWrapper: return "SystemZISD::PCRelativeWrapper";
770 default: return NULL;
774 //===----------------------------------------------------------------------===//
775 // Other Lowering Code
776 //===----------------------------------------------------------------------===//
779 SystemZTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
780 MachineBasicBlock *BB) const {
781 const SystemZInstrInfo &TII = *TM.getInstrInfo();
782 DebugLoc dl = MI->getDebugLoc();
783 assert((MI->getOpcode() == SystemZ::Select32 ||
784 MI->getOpcode() == SystemZ::SelectF32 ||
785 MI->getOpcode() == SystemZ::Select64 ||
786 MI->getOpcode() == SystemZ::SelectF64) &&
787 "Unexpected instr type to insert");
789 // To "insert" a SELECT instruction, we actually have to insert the diamond
790 // control-flow pattern. The incoming instruction knows the destination vreg
791 // to set, the condition code register to branch on, the true/false values to
792 // select between, and a branch opcode to use.
793 const BasicBlock *LLVM_BB = BB->getBasicBlock();
794 MachineFunction::iterator I = BB;
802 // fallthrough --> copy0MBB
803 MachineBasicBlock *thisMBB = BB;
804 MachineFunction *F = BB->getParent();
805 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
806 MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
807 SystemZCC::CondCodes CC = (SystemZCC::CondCodes)MI->getOperand(3).getImm();
808 BuildMI(BB, dl, TII.getBrCond(CC)).addMBB(copy1MBB);
809 F->insert(I, copy0MBB);
810 F->insert(I, copy1MBB);
811 // Update machine-CFG edges by transferring all successors of the current
812 // block to the new block which will contain the Phi node for the select.
813 copy1MBB->transferSuccessors(BB);
814 // Next, add the true and fallthrough blocks as its successors.
815 BB->addSuccessor(copy0MBB);
816 BB->addSuccessor(copy1MBB);
820 // # fallthrough to copy1MBB
823 // Update machine-CFG edges
824 BB->addSuccessor(copy1MBB);
827 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
830 BuildMI(BB, dl, TII.get(SystemZ::PHI),
831 MI->getOperand(0).getReg())
832 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
833 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
835 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.