1 //==-- SystemZISelLowering.h - SystemZ DAG Lowering Interface ----*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that SystemZ uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_SystemZ_ISELLOWERING_H
16 #define LLVM_TARGET_SystemZ_ISELLOWERING_H
19 #include "SystemZRegisterInfo.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
24 namespace SystemZISD {
26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
28 /// Return with a flag operand. Operand 0 is the chain operand.
31 /// CALL - These operations represent an abstract call
32 /// instruction, which includes a bunch of information.
35 /// PCRelativeWrapper - PC relative address
38 /// CMP, UCMP - Compare instruction
42 /// BRCOND - Conditional branch. Operand 0 is chain operand, operand 1 is
43 /// the block to branch if condition is true, operand 2 is condition code
44 /// and operand 3 is the flag operand produced by a CMP instruction.
47 /// SELECT - Operands 0 and 1 are selection variables, operand 2 is
48 /// condition code and operand 3 is the flag operand.
53 class SystemZSubtarget;
54 class SystemZTargetMachine;
56 class SystemZTargetLowering : public TargetLowering {
58 explicit SystemZTargetLowering(SystemZTargetMachine &TM);
60 /// LowerOperation - Provide custom lowering hooks for some operations.
61 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
63 /// getTargetNodeName - This method returns the name of a target specific
65 virtual const char *getTargetNodeName(unsigned Opcode) const;
67 /// getFunctionAlignment - Return the Log2 alignment of this function.
68 virtual unsigned getFunctionAlignment(const Function *F) const {
72 std::pair<unsigned, const TargetRegisterClass*>
73 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
74 TargetLowering::ConstraintType
75 getConstraintType(const std::string &Constraint) const;
77 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG);
78 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
79 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
80 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG);
81 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG);
83 SDValue EmitCmp(SDValue LHS, SDValue RHS,
84 ISD::CondCode CC, SDValue &SystemZCC,
88 MachineBasicBlock* EmitInstrWithCustomInserter(MachineInstr *MI,
89 MachineBasicBlock *BB,
90 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
92 /// isFPImmLegal - Returns true if the target can instruction select the
93 /// specified FP immediate natively. If false, the legalizer will
94 /// materialize the FP immediate as a load from a constant pool.
95 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
98 SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
99 CallingConv::ID CallConv, bool isVarArg,
101 const SmallVectorImpl<ISD::OutputArg> &Outs,
102 const SmallVectorImpl<ISD::InputArg> &Ins,
103 DebugLoc dl, SelectionDAG &DAG,
104 SmallVectorImpl<SDValue> &InVals);
106 SDValue LowerCCCArguments(SDValue Chain,
107 CallingConv::ID CallConv,
109 const SmallVectorImpl<ISD::InputArg> &Ins,
112 SmallVectorImpl<SDValue> &InVals);
114 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
115 CallingConv::ID CallConv, bool isVarArg,
116 const SmallVectorImpl<ISD::InputArg> &Ins,
117 DebugLoc dl, SelectionDAG &DAG,
118 SmallVectorImpl<SDValue> &InVals);
121 LowerFormalArguments(SDValue Chain,
122 CallingConv::ID CallConv, bool isVarArg,
123 const SmallVectorImpl<ISD::InputArg> &Ins,
124 DebugLoc dl, SelectionDAG &DAG,
125 SmallVectorImpl<SDValue> &InVals);
127 LowerCall(SDValue Chain, SDValue Callee,
128 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
129 const SmallVectorImpl<ISD::OutputArg> &Outs,
130 const SmallVectorImpl<ISD::InputArg> &Ins,
131 DebugLoc dl, SelectionDAG &DAG,
132 SmallVectorImpl<SDValue> &InVals);
135 LowerReturn(SDValue Chain,
136 CallingConv::ID CallConv, bool isVarArg,
137 const SmallVectorImpl<ISD::OutputArg> &Outs,
138 DebugLoc dl, SelectionDAG &DAG);
140 const SystemZSubtarget &Subtarget;
141 const SystemZTargetMachine &TM;
142 const SystemZRegisterInfo *RegInfo;
146 #endif // LLVM_TARGET_SystemZ_ISELLOWERING_H