1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that SystemZ uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_SystemZ_ISELLOWERING_H
16 #define LLVM_TARGET_SystemZ_ISELLOWERING_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
24 namespace SystemZISD {
26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
28 // Return with a flag operand. Operand 0 is the chain operand.
31 // Calls a function. Operand 0 is the chain operand and operand 1
32 // is the target address. The arguments start at operand 2.
33 // There is an optional glue operand at the end.
36 // Wraps a TargetGlobalAddress that should be loaded using PC-relative
37 // accesses (LARL). Operand 0 is the address.
40 // Signed integer and floating-point comparisons. The operands are the
41 // two values to compare.
44 // Likewise unsigned integer comparison.
47 // Branches if a condition is true. Operand 0 is the chain operand;
48 // operand 1 is the 4-bit condition-code mask, with bit N in
49 // big-endian order meaning "branch if CC=N"; operand 2 is the
50 // target block and operand 3 is the flag operand.
53 // Selects between operand 0 and operand 1. Operand 2 is the
54 // mask of condition-code values for which operand 0 should be
55 // chosen over operand 1; it has the same form as BR_CCMASK.
56 // Operand 3 is the flag operand.
59 // Evaluates to the gap between the stack pointer and the
60 // base of the dynamically-allocatable area.
63 // Extracts the value of a 32-bit access register. Operand 0 is
64 // the number of the register.
67 // Wrappers around the ISD opcodes of the same name. The output and
68 // first input operands are GR128s. The trailing numbers are the
69 // widths of the second operand in bits.
76 // Use MVC to copy bytes from one memory location to another.
77 // The first operand is the target address, the second operand is the
78 // source address, and the third operand is the constant length.
79 // This isn't a memory opcode because we'd need to attach two
80 // MachineMemOperands rather than one.
83 // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
86 // Operand 0: the address of the containing 32-bit-aligned field
87 // Operand 1: the second operand of <op>, in the high bits of an i32
88 // for everything except ATOMIC_SWAPW
89 // Operand 2: how many bits to rotate the i32 left to bring the first
90 // operand into the high bits
91 // Operand 3: the negative of operand 2, for rotating the other way
92 // Operand 4: the width of the field in bits (8 or 16)
93 ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE,
105 // A wrapper around the inner loop of an ATOMIC_CMP_SWAP.
107 // Operand 0: the address of the containing 32-bit-aligned field
108 // Operand 1: the compare value, in the low bits of an i32
109 // Operand 2: the swap value, in the low bits of an i32
110 // Operand 3: how many bits to rotate the i32 left to bring the first
111 // operand into the high bits
112 // Operand 4: the negative of operand 2, for rotating the other way
113 // Operand 5: the width of the field in bits (8 or 16)
118 class SystemZSubtarget;
119 class SystemZTargetMachine;
121 class SystemZTargetLowering : public TargetLowering {
123 explicit SystemZTargetLowering(SystemZTargetMachine &TM);
125 // Override TargetLowering.
126 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const LLVM_OVERRIDE {
129 virtual EVT getSetCCResultType(LLVMContext &, EVT) const {
132 virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const LLVM_OVERRIDE;
133 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
134 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const;
135 virtual const char *getTargetNodeName(unsigned Opcode) const LLVM_OVERRIDE;
136 virtual std::pair<unsigned, const TargetRegisterClass *>
137 getRegForInlineAsmConstraint(const std::string &Constraint,
138 MVT VT) const LLVM_OVERRIDE;
139 virtual TargetLowering::ConstraintType
140 getConstraintType(const std::string &Constraint) const LLVM_OVERRIDE;
141 virtual TargetLowering::ConstraintWeight
142 getSingleConstraintMatchWeight(AsmOperandInfo &info,
143 const char *constraint) const LLVM_OVERRIDE;
145 LowerAsmOperandForConstraint(SDValue Op,
146 std::string &Constraint,
147 std::vector<SDValue> &Ops,
148 SelectionDAG &DAG) const LLVM_OVERRIDE;
149 virtual MachineBasicBlock *
150 EmitInstrWithCustomInserter(MachineInstr *MI,
151 MachineBasicBlock *BB) const LLVM_OVERRIDE;
152 virtual SDValue LowerOperation(SDValue Op,
153 SelectionDAG &DAG) const LLVM_OVERRIDE;
155 LowerFormalArguments(SDValue Chain,
156 CallingConv::ID CallConv, bool isVarArg,
157 const SmallVectorImpl<ISD::InputArg> &Ins,
158 SDLoc DL, SelectionDAG &DAG,
159 SmallVectorImpl<SDValue> &InVals) const LLVM_OVERRIDE;
161 LowerCall(CallLoweringInfo &CLI,
162 SmallVectorImpl<SDValue> &InVals) const LLVM_OVERRIDE;
165 LowerReturn(SDValue Chain,
166 CallingConv::ID CallConv, bool IsVarArg,
167 const SmallVectorImpl<ISD::OutputArg> &Outs,
168 const SmallVectorImpl<SDValue> &OutVals,
169 SDLoc DL, SelectionDAG &DAG) const LLVM_OVERRIDE;
172 const SystemZSubtarget &Subtarget;
173 const SystemZTargetMachine &TM;
175 // Implement LowerOperation for individual opcodes.
176 SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
177 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
178 SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,
179 SelectionDAG &DAG) const;
180 SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
181 SelectionDAG &DAG) const;
182 SDValue lowerBlockAddress(BlockAddressSDNode *Node,
183 SelectionDAG &DAG) const;
184 SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
185 SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
186 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
187 SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
188 SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
189 SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
190 SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
191 SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
192 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
193 SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
194 SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG,
195 unsigned Opcode) const;
196 SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
197 SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
198 SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
200 // If the last instruction before MBBI in MBB was some form of COMPARE,
201 // try to replace it with a COMPARE AND BRANCH just before MBBI.
202 // CCMask and Target are the BRC-like operands for the branch.
203 // Return true if the change was made.
204 bool convertPrevCompareToBranch(MachineBasicBlock *MBB,
205 MachineBasicBlock::iterator MBBI,
207 MachineBasicBlock *Target) const;
209 // Implement EmitInstrWithCustomInserter for individual operation types.
210 MachineBasicBlock *emitSelect(MachineInstr *MI,
211 MachineBasicBlock *BB) const;
212 MachineBasicBlock *emitCondStore(MachineInstr *MI,
213 MachineBasicBlock *BB,
214 unsigned StoreOpcode, bool Invert) const;
215 MachineBasicBlock *emitExt128(MachineInstr *MI,
216 MachineBasicBlock *MBB,
217 bool ClearEven, unsigned SubReg) const;
218 MachineBasicBlock *emitAtomicLoadBinary(MachineInstr *MI,
219 MachineBasicBlock *BB,
220 unsigned BinOpcode, unsigned BitSize,
221 bool Invert = false) const;
222 MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr *MI,
223 MachineBasicBlock *MBB,
224 unsigned CompareOpcode,
225 unsigned KeepOldMask,
226 unsigned BitSize) const;
227 MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr *MI,
228 MachineBasicBlock *BB) const;
229 MachineBasicBlock *emitMVCWrapper(MachineInstr *MI,
230 MachineBasicBlock *BB) const;
232 } // end namespace llvm
234 #endif // LLVM_TARGET_SystemZ_ISELLOWERING_H