1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that SystemZ uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
16 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
24 namespace SystemZISD {
26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
28 // Return with a flag operand. Operand 0 is the chain operand.
31 // Calls a function. Operand 0 is the chain operand and operand 1
32 // is the target address. The arguments start at operand 2.
33 // There is an optional glue operand at the end.
37 // TLS calls. Like regular calls, except operand 1 is the TLS symbol.
38 // (The call target is implicitly __tls_get_offset.)
42 // Wraps a TargetGlobalAddress that should be loaded using PC-relative
43 // accesses (LARL). Operand 0 is the address.
46 // Used in cases where an offset is applied to a TargetGlobalAddress.
47 // Operand 0 is the full TargetGlobalAddress and operand 1 is a
48 // PCREL_WRAPPER for an anchor point. This is used so that we can
49 // cheaply refer to either the full address or the anchor point
50 // as a register base.
56 // Integer comparisons. There are three operands: the two values
57 // to compare, and an integer of type SystemZICMP.
60 // Floating-point comparisons. The two operands are the values to compare.
63 // Test under mask. The first operand is ANDed with the second operand
64 // and the condition codes are set on the result. The third operand is
65 // a boolean that is true if the condition codes need to distinguish
66 // between CCMASK_TM_MIXED_MSB_0 and CCMASK_TM_MIXED_MSB_1 (which the
67 // register forms do but the memory forms don't).
70 // Branches if a condition is true. Operand 0 is the chain operand;
71 // operand 1 is the 4-bit condition-code mask, with bit N in
72 // big-endian order meaning "branch if CC=N"; operand 2 is the
73 // target block and operand 3 is the flag operand.
76 // Selects between operand 0 and operand 1. Operand 2 is the
77 // mask of condition-code values for which operand 0 should be
78 // chosen over operand 1; it has the same form as BR_CCMASK.
79 // Operand 3 is the flag operand.
82 // Evaluates to the gap between the stack pointer and the
83 // base of the dynamically-allocatable area.
86 // Extracts the value of a 32-bit access register. Operand 0 is
87 // the number of the register.
90 // Wrappers around the ISD opcodes of the same name. The output and
91 // first input operands are GR128s. The trailing numbers are the
92 // widths of the second operand in bits.
99 // Use a series of MVCs to copy bytes from one memory location to another.
101 // - the target address
102 // - the source address
103 // - the constant length
105 // This isn't a memory opcode because we'd need to attach two
106 // MachineMemOperands rather than one.
109 // Like MVC, but implemented as a loop that handles X*256 bytes
110 // followed by straight-line code to handle the rest (if any).
111 // The value of X is passed as an additional operand.
114 // Similar to MVC and MVC_LOOP, but for logic operations (AND, OR, XOR).
122 // Use CLC to compare two blocks of memory, with the same comments
123 // as for MVC and MVC_LOOP.
127 // Use an MVST-based sequence to implement stpcpy().
130 // Use a CLST-based sequence to implement strcmp(). The two input operands
131 // are the addresses of the strings to compare.
134 // Use an SRST-based sequence to search a block of memory. The first
135 // operand is the end address, the second is the start, and the third
136 // is the character to search for. CC is set to 1 on success and 2
140 // Store the CC value in bits 29 and 28 of an integer.
143 // Perform a serialization operation. (BCR 15,0 or BCR 14,0.)
146 // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
149 // Operand 0: the address of the containing 32-bit-aligned field
150 // Operand 1: the second operand of <op>, in the high bits of an i32
151 // for everything except ATOMIC_SWAPW
152 // Operand 2: how many bits to rotate the i32 left to bring the first
153 // operand into the high bits
154 // Operand 3: the negative of operand 2, for rotating the other way
155 // Operand 4: the width of the field in bits (8 or 16)
156 ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE,
168 // A wrapper around the inner loop of an ATOMIC_CMP_SWAP.
170 // Operand 0: the address of the containing 32-bit-aligned field
171 // Operand 1: the compare value, in the low bits of an i32
172 // Operand 2: the swap value, in the low bits of an i32
173 // Operand 3: how many bits to rotate the i32 left to bring the first
174 // operand into the high bits
175 // Operand 4: the negative of operand 2, for rotating the other way
176 // Operand 5: the width of the field in bits (8 or 16)
179 // Prefetch from the second operand using the 4-bit control code in
180 // the first operand. The code is 1 for a load prefetch and 2 for
185 // Return true if OPCODE is some kind of PC-relative address.
186 inline bool isPCREL(unsigned Opcode) {
187 return Opcode == PCREL_WRAPPER || Opcode == PCREL_OFFSET;
189 } // end namespace SystemZISD
191 namespace SystemZICMP {
192 // Describes whether an integer comparison needs to be signed or unsigned,
193 // or whether either type is OK.
199 } // end namespace SystemZICMP
201 class SystemZSubtarget;
202 class SystemZTargetMachine;
204 class SystemZTargetLowering : public TargetLowering {
206 explicit SystemZTargetLowering(const TargetMachine &TM,
207 const SystemZSubtarget &STI);
209 // Override TargetLowering.
210 MVT getScalarShiftAmountTy(EVT LHSTy) const override {
213 EVT getSetCCResultType(LLVMContext &, EVT) const override;
214 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
215 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
216 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
217 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
219 bool *Fast) const override;
220 bool isTruncateFree(Type *, Type *) const override;
221 bool isTruncateFree(EVT, EVT) const override;
222 const char *getTargetNodeName(unsigned Opcode) const override;
223 std::pair<unsigned, const TargetRegisterClass *>
224 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
225 const std::string &Constraint,
226 MVT VT) const override;
227 TargetLowering::ConstraintType
228 getConstraintType(const std::string &Constraint) const override;
229 TargetLowering::ConstraintWeight
230 getSingleConstraintMatchWeight(AsmOperandInfo &info,
231 const char *constraint) const override;
232 void LowerAsmOperandForConstraint(SDValue Op,
233 std::string &Constraint,
234 std::vector<SDValue> &Ops,
235 SelectionDAG &DAG) const override;
236 MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
237 MachineBasicBlock *BB) const
239 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
240 bool allowTruncateForTailCall(Type *, Type *) const override;
241 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
242 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
244 const SmallVectorImpl<ISD::InputArg> &Ins,
245 SDLoc DL, SelectionDAG &DAG,
246 SmallVectorImpl<SDValue> &InVals) const override;
247 SDValue LowerCall(CallLoweringInfo &CLI,
248 SmallVectorImpl<SDValue> &InVals) const override;
250 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
251 const SmallVectorImpl<ISD::OutputArg> &Outs,
252 const SmallVectorImpl<SDValue> &OutVals,
253 SDLoc DL, SelectionDAG &DAG) const override;
254 SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL,
255 SelectionDAG &DAG) const override;
256 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
259 const SystemZSubtarget &Subtarget;
261 // Implement LowerOperation for individual opcodes.
262 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
263 SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
264 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
265 SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,
266 SelectionDAG &DAG) const;
267 SDValue lowerTLSGetOffset(GlobalAddressSDNode *Node,
268 SelectionDAG &DAG, unsigned Opcode,
269 SDValue GOTOffset) const;
270 SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
271 SelectionDAG &DAG) const;
272 SDValue lowerBlockAddress(BlockAddressSDNode *Node,
273 SelectionDAG &DAG) const;
274 SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
275 SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
276 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
277 SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
278 SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
279 SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
280 SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
281 SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
282 SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
283 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
284 SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
285 SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
286 SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
287 SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG,
288 unsigned Opcode) const;
289 SDValue lowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
290 SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
291 SDValue lowerLOAD_SEQUENCE_POINT(SDValue Op, SelectionDAG &DAG) const;
292 SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
293 SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
294 SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
296 // If the last instruction before MBBI in MBB was some form of COMPARE,
297 // try to replace it with a COMPARE AND BRANCH just before MBBI.
298 // CCMask and Target are the BRC-like operands for the branch.
299 // Return true if the change was made.
300 bool convertPrevCompareToBranch(MachineBasicBlock *MBB,
301 MachineBasicBlock::iterator MBBI,
303 MachineBasicBlock *Target) const;
305 // Implement EmitInstrWithCustomInserter for individual operation types.
306 MachineBasicBlock *emitSelect(MachineInstr *MI,
307 MachineBasicBlock *BB) const;
308 MachineBasicBlock *emitCondStore(MachineInstr *MI,
309 MachineBasicBlock *BB,
310 unsigned StoreOpcode, unsigned STOCOpcode,
312 MachineBasicBlock *emitExt128(MachineInstr *MI,
313 MachineBasicBlock *MBB,
314 bool ClearEven, unsigned SubReg) const;
315 MachineBasicBlock *emitAtomicLoadBinary(MachineInstr *MI,
316 MachineBasicBlock *BB,
317 unsigned BinOpcode, unsigned BitSize,
318 bool Invert = false) const;
319 MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr *MI,
320 MachineBasicBlock *MBB,
321 unsigned CompareOpcode,
322 unsigned KeepOldMask,
323 unsigned BitSize) const;
324 MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr *MI,
325 MachineBasicBlock *BB) const;
326 MachineBasicBlock *emitMemMemWrapper(MachineInstr *MI,
327 MachineBasicBlock *BB,
328 unsigned Opcode) const;
329 MachineBasicBlock *emitStringWrapper(MachineInstr *MI,
330 MachineBasicBlock *BB,
331 unsigned Opcode) const;
333 } // end namespace llvm