1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that SystemZ uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_SystemZ_ISELLOWERING_H
16 #define LLVM_TARGET_SystemZ_ISELLOWERING_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
24 namespace SystemZISD {
26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
28 // Return with a flag operand. Operand 0 is the chain operand.
31 // Calls a function. Operand 0 is the chain operand and operand 1
32 // is the target address. The arguments start at operand 2.
33 // There is an optional glue operand at the end.
37 // Wraps a TargetGlobalAddress that should be loaded using PC-relative
38 // accesses (LARL). Operand 0 is the address.
41 // Used in cases where an offset is applied to a TargetGlobalAddress.
42 // Operand 0 is the full TargetGlobalAddress and operand 1 is a
43 // PCREL_WRAPPER for an anchor point. This is used so that we can
44 // cheaply refer to either the full address or the anchor point
45 // as a register base.
48 // Integer comparisons. There are three operands: the two values
49 // to compare, and an integer of type SystemZICMP.
52 // Floating-point comparisons. The two operands are the values to compare.
55 // Test under mask. The first operand is ANDed with the second operand
56 // and the condition codes are set on the result. The third operand is
57 // a boolean that is true if the condition codes need to distinguish
58 // between CCMASK_TM_MIXED_MSB_0 and CCMASK_TM_MIXED_MSB_1 (which the
59 // register forms do but the memory forms don't).
62 // Branches if a condition is true. Operand 0 is the chain operand;
63 // operand 1 is the 4-bit condition-code mask, with bit N in
64 // big-endian order meaning "branch if CC=N"; operand 2 is the
65 // target block and operand 3 is the flag operand.
68 // Selects between operand 0 and operand 1. Operand 2 is the
69 // mask of condition-code values for which operand 0 should be
70 // chosen over operand 1; it has the same form as BR_CCMASK.
71 // Operand 3 is the flag operand.
74 // Evaluates to the gap between the stack pointer and the
75 // base of the dynamically-allocatable area.
78 // Extracts the value of a 32-bit access register. Operand 0 is
79 // the number of the register.
82 // Wrappers around the ISD opcodes of the same name. The output and
83 // first input operands are GR128s. The trailing numbers are the
84 // widths of the second operand in bits.
91 // Use a series of MVCs to copy bytes from one memory location to another.
93 // - the target address
94 // - the source address
95 // - the constant length
97 // This isn't a memory opcode because we'd need to attach two
98 // MachineMemOperands rather than one.
101 // Like MVC, but implemented as a loop that handles X*256 bytes
102 // followed by straight-line code to handle the rest (if any).
103 // The value of X is passed as an additional operand.
106 // Similar to MVC and MVC_LOOP, but for logic operations (AND, OR, XOR).
114 // Use CLC to compare two blocks of memory, with the same comments
115 // as for MVC and MVC_LOOP.
119 // Use an MVST-based sequence to implement stpcpy().
122 // Use a CLST-based sequence to implement strcmp(). The two input operands
123 // are the addresses of the strings to compare.
126 // Use an SRST-based sequence to search a block of memory. The first
127 // operand is the end address, the second is the start, and the third
128 // is the character to search for. CC is set to 1 on success and 2
132 // Store the CC value in bits 29 and 28 of an integer.
135 // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
138 // Operand 0: the address of the containing 32-bit-aligned field
139 // Operand 1: the second operand of <op>, in the high bits of an i32
140 // for everything except ATOMIC_SWAPW
141 // Operand 2: how many bits to rotate the i32 left to bring the first
142 // operand into the high bits
143 // Operand 3: the negative of operand 2, for rotating the other way
144 // Operand 4: the width of the field in bits (8 or 16)
145 ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE,
157 // A wrapper around the inner loop of an ATOMIC_CMP_SWAP.
159 // Operand 0: the address of the containing 32-bit-aligned field
160 // Operand 1: the compare value, in the low bits of an i32
161 // Operand 2: the swap value, in the low bits of an i32
162 // Operand 3: how many bits to rotate the i32 left to bring the first
163 // operand into the high bits
164 // Operand 4: the negative of operand 2, for rotating the other way
165 // Operand 5: the width of the field in bits (8 or 16)
168 // Prefetch from the second operand using the 4-bit control code in
169 // the first operand. The code is 1 for a load prefetch and 2 for
174 // Return true if OPCODE is some kind of PC-relative address.
175 inline bool isPCREL(unsigned Opcode) {
176 return Opcode == PCREL_WRAPPER || Opcode == PCREL_OFFSET;
180 namespace SystemZICMP {
181 // Describes whether an integer comparison needs to be signed or unsigned,
182 // or whether either type is OK.
190 class SystemZSubtarget;
191 class SystemZTargetMachine;
193 class SystemZTargetLowering : public TargetLowering {
195 explicit SystemZTargetLowering(SystemZTargetMachine &TM);
197 // Override TargetLowering.
198 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const LLVM_OVERRIDE {
201 virtual EVT getSetCCResultType(LLVMContext &, EVT) const LLVM_OVERRIDE {
204 virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const LLVM_OVERRIDE;
205 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const LLVM_OVERRIDE;
206 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const
208 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const
210 virtual bool isTruncateFree(Type *, Type *) const LLVM_OVERRIDE;
211 virtual bool isTruncateFree(EVT, EVT) const LLVM_OVERRIDE;
212 virtual const char *getTargetNodeName(unsigned Opcode) const LLVM_OVERRIDE;
213 virtual std::pair<unsigned, const TargetRegisterClass *>
214 getRegForInlineAsmConstraint(const std::string &Constraint,
215 MVT VT) const LLVM_OVERRIDE;
216 virtual TargetLowering::ConstraintType
217 getConstraintType(const std::string &Constraint) const LLVM_OVERRIDE;
218 virtual TargetLowering::ConstraintWeight
219 getSingleConstraintMatchWeight(AsmOperandInfo &info,
220 const char *constraint) const LLVM_OVERRIDE;
222 LowerAsmOperandForConstraint(SDValue Op,
223 std::string &Constraint,
224 std::vector<SDValue> &Ops,
225 SelectionDAG &DAG) const LLVM_OVERRIDE;
226 virtual MachineBasicBlock *
227 EmitInstrWithCustomInserter(MachineInstr *MI,
228 MachineBasicBlock *BB) const LLVM_OVERRIDE;
229 virtual SDValue LowerOperation(SDValue Op,
230 SelectionDAG &DAG) const LLVM_OVERRIDE;
231 virtual bool allowTruncateForTailCall(Type *, Type *) const LLVM_OVERRIDE;
232 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const LLVM_OVERRIDE;
234 LowerFormalArguments(SDValue Chain,
235 CallingConv::ID CallConv, bool isVarArg,
236 const SmallVectorImpl<ISD::InputArg> &Ins,
237 SDLoc DL, SelectionDAG &DAG,
238 SmallVectorImpl<SDValue> &InVals) const LLVM_OVERRIDE;
240 LowerCall(CallLoweringInfo &CLI,
241 SmallVectorImpl<SDValue> &InVals) const LLVM_OVERRIDE;
244 LowerReturn(SDValue Chain,
245 CallingConv::ID CallConv, bool IsVarArg,
246 const SmallVectorImpl<ISD::OutputArg> &Outs,
247 const SmallVectorImpl<SDValue> &OutVals,
248 SDLoc DL, SelectionDAG &DAG) const LLVM_OVERRIDE;
251 const SystemZSubtarget &Subtarget;
252 const SystemZTargetMachine &TM;
254 // Implement LowerOperation for individual opcodes.
255 SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
256 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
257 SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,
258 SelectionDAG &DAG) const;
259 SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
260 SelectionDAG &DAG) const;
261 SDValue lowerBlockAddress(BlockAddressSDNode *Node,
262 SelectionDAG &DAG) const;
263 SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
264 SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
265 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
266 SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
267 SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
268 SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
269 SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
270 SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
271 SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
272 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
273 SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
274 SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG,
275 unsigned Opcode) const;
276 SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
277 SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
278 SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
279 SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
281 // If the last instruction before MBBI in MBB was some form of COMPARE,
282 // try to replace it with a COMPARE AND BRANCH just before MBBI.
283 // CCMask and Target are the BRC-like operands for the branch.
284 // Return true if the change was made.
285 bool convertPrevCompareToBranch(MachineBasicBlock *MBB,
286 MachineBasicBlock::iterator MBBI,
288 MachineBasicBlock *Target) const;
290 // Implement EmitInstrWithCustomInserter for individual operation types.
291 MachineBasicBlock *emitSelect(MachineInstr *MI,
292 MachineBasicBlock *BB) const;
293 MachineBasicBlock *emitCondStore(MachineInstr *MI,
294 MachineBasicBlock *BB,
295 unsigned StoreOpcode, unsigned STOCOpcode,
297 MachineBasicBlock *emitExt128(MachineInstr *MI,
298 MachineBasicBlock *MBB,
299 bool ClearEven, unsigned SubReg) const;
300 MachineBasicBlock *emitAtomicLoadBinary(MachineInstr *MI,
301 MachineBasicBlock *BB,
302 unsigned BinOpcode, unsigned BitSize,
303 bool Invert = false) const;
304 MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr *MI,
305 MachineBasicBlock *MBB,
306 unsigned CompareOpcode,
307 unsigned KeepOldMask,
308 unsigned BitSize) const;
309 MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr *MI,
310 MachineBasicBlock *BB) const;
311 MachineBasicBlock *emitMemMemWrapper(MachineInstr *MI,
312 MachineBasicBlock *BB,
313 unsigned Opcode) const;
314 MachineBasicBlock *emitStringWrapper(MachineInstr *MI,
315 MachineBasicBlock *BB,
316 unsigned Opcode) const;
318 } // end namespace llvm
320 #endif // LLVM_TARGET_SystemZ_ISELLOWERING_H