1 //==- SystemZInstrFP.td - Floating-point SystemZ instructions --*- tblgen-*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Select instructions
12 //===----------------------------------------------------------------------===//
14 // C's ?: operator for floating-point operands.
15 def SelectF32 : SelectWrapper<FP32>;
16 def SelectF64 : SelectWrapper<FP64>;
17 def SelectF128 : SelectWrapper<FP128>;
19 defm CondStoreF32 : CondStores<FP32, nonvolatile_store,
20 nonvolatile_load, bdxaddr20only>;
21 defm CondStoreF64 : CondStores<FP64, nonvolatile_store,
22 nonvolatile_load, bdxaddr20only>;
24 //===----------------------------------------------------------------------===//
26 //===----------------------------------------------------------------------===//
29 let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1 in {
30 def LZER : InherentRRE<"lzer", 0xB374, FP32, (fpimm0)>;
31 def LZDR : InherentRRE<"lzdr", 0xB375, FP64, (fpimm0)>;
32 def LZXR : InherentRRE<"lzxr", 0xB376, FP128, (fpimm0)>;
35 // Moves between two floating-point registers.
36 let hasSideEffects = 0 in {
37 def LER : UnaryRR <"le", 0x38, null_frag, FP32, FP32>;
38 def LDR : UnaryRR <"ld", 0x28, null_frag, FP64, FP64>;
39 def LXR : UnaryRRE<"lx", 0xB365, null_frag, FP128, FP128>;
42 // Moves between two floating-point registers that also set the condition
44 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
45 defm LTEBR : LoadAndTestRRE<"lteb", 0xB302, FP32>;
46 defm LTDBR : LoadAndTestRRE<"ltdb", 0xB312, FP64>;
47 defm LTXBR : LoadAndTestRRE<"ltxb", 0xB342, FP128>;
49 // Note that the comparison against zero operation is not available if we
50 // have vector support, since load-and-test instructions will partially
51 // clobber the target (vector) register.
52 let Predicates = [FeatureNoVector] in {
53 defm : CompareZeroFP<LTEBRCompare, FP32>;
54 defm : CompareZeroFP<LTDBRCompare, FP64>;
55 defm : CompareZeroFP<LTXBRCompare, FP128>;
58 // Moves between 64-bit integer and floating-point registers.
59 def LGDR : UnaryRRE<"lgd", 0xB3CD, bitconvert, GR64, FP64>;
60 def LDGR : UnaryRRE<"ldg", 0xB3C1, bitconvert, FP64, GR64>;
62 // fcopysign with an FP32 result.
63 let isCodeGenOnly = 1 in {
64 def CPSDRss : BinaryRRF<"cpsd", 0xB372, fcopysign, FP32, FP32>;
65 def CPSDRsd : BinaryRRF<"cpsd", 0xB372, fcopysign, FP32, FP64>;
68 // The sign of an FP128 is in the high register.
69 def : Pat<(fcopysign FP32:$src1, FP128:$src2),
70 (CPSDRsd FP32:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>;
72 // fcopysign with an FP64 result.
73 let isCodeGenOnly = 1 in
74 def CPSDRds : BinaryRRF<"cpsd", 0xB372, fcopysign, FP64, FP32>;
75 def CPSDRdd : BinaryRRF<"cpsd", 0xB372, fcopysign, FP64, FP64>;
77 // The sign of an FP128 is in the high register.
78 def : Pat<(fcopysign FP64:$src1, FP128:$src2),
79 (CPSDRdd FP64:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>;
81 // fcopysign with an FP128 result. Use "upper" as the high half and leave
82 // the low half as-is.
83 class CopySign128<RegisterOperand cls, dag upper>
84 : Pat<(fcopysign FP128:$src1, cls:$src2),
85 (INSERT_SUBREG FP128:$src1, upper, subreg_h64)>;
87 def : CopySign128<FP32, (CPSDRds (EXTRACT_SUBREG FP128:$src1, subreg_h64),
89 def : CopySign128<FP64, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_h64),
91 def : CopySign128<FP128, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_h64),
92 (EXTRACT_SUBREG FP128:$src2, subreg_h64))>;
94 defm LoadStoreF32 : MVCLoadStore<load, f32, MVCSequence, 4>;
95 defm LoadStoreF64 : MVCLoadStore<load, f64, MVCSequence, 8>;
96 defm LoadStoreF128 : MVCLoadStore<load, f128, MVCSequence, 16>;
98 //===----------------------------------------------------------------------===//
100 //===----------------------------------------------------------------------===//
102 let canFoldAsLoad = 1, SimpleBDXLoad = 1 in {
103 defm LE : UnaryRXPair<"le", 0x78, 0xED64, load, FP32, 4>;
104 defm LD : UnaryRXPair<"ld", 0x68, 0xED65, load, FP64, 8>;
106 // For z13 we prefer LDE over LE to avoid partial register dependencies.
107 def LDE32 : UnaryRXE<"lde", 0xED24, null_frag, FP32, 4>;
109 // These instructions are split after register allocation, so we don't
110 // want a custom inserter.
111 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
112 def LX : Pseudo<(outs FP128:$dst), (ins bdxaddr20only128:$src),
113 [(set FP128:$dst, (load bdxaddr20only128:$src))]>;
117 //===----------------------------------------------------------------------===//
118 // Store instructions
119 //===----------------------------------------------------------------------===//
121 let SimpleBDXStore = 1 in {
122 defm STE : StoreRXPair<"ste", 0x70, 0xED66, store, FP32, 4>;
123 defm STD : StoreRXPair<"std", 0x60, 0xED67, store, FP64, 8>;
125 // These instructions are split after register allocation, so we don't
126 // want a custom inserter.
127 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
128 def STX : Pseudo<(outs), (ins FP128:$src, bdxaddr20only128:$dst),
129 [(store FP128:$src, bdxaddr20only128:$dst)]>;
133 //===----------------------------------------------------------------------===//
134 // Conversion instructions
135 //===----------------------------------------------------------------------===//
137 // Convert floating-point values to narrower representations, rounding
138 // according to the current mode. The destination of LEXBR and LDXBR
139 // is a 128-bit value, but only the first register of the pair is used.
140 def LEDBR : UnaryRRE<"ledb", 0xB344, fround, FP32, FP64>;
141 def LEXBR : UnaryRRE<"lexb", 0xB346, null_frag, FP128, FP128>;
142 def LDXBR : UnaryRRE<"ldxb", 0xB345, null_frag, FP128, FP128>;
144 def LEDBRA : UnaryRRF4<"ledbra", 0xB344, FP32, FP64>,
145 Requires<[FeatureFPExtension]>;
146 def LEXBRA : UnaryRRF4<"lexbra", 0xB346, FP128, FP128>,
147 Requires<[FeatureFPExtension]>;
148 def LDXBRA : UnaryRRF4<"ldxbra", 0xB345, FP128, FP128>,
149 Requires<[FeatureFPExtension]>;
151 def : Pat<(f32 (fround FP128:$src)),
152 (EXTRACT_SUBREG (LEXBR FP128:$src), subreg_hr32)>;
153 def : Pat<(f64 (fround FP128:$src)),
154 (EXTRACT_SUBREG (LDXBR FP128:$src), subreg_h64)>;
156 // Extend register floating-point values to wider representations.
157 def LDEBR : UnaryRRE<"ldeb", 0xB304, fextend, FP64, FP32>;
158 def LXEBR : UnaryRRE<"lxeb", 0xB306, fextend, FP128, FP32>;
159 def LXDBR : UnaryRRE<"lxdb", 0xB305, fextend, FP128, FP64>;
161 // Extend memory floating-point values to wider representations.
162 def LDEB : UnaryRXE<"ldeb", 0xED04, extloadf32, FP64, 4>;
163 def LXEB : UnaryRXE<"lxeb", 0xED06, extloadf32, FP128, 4>;
164 def LXDB : UnaryRXE<"lxdb", 0xED05, extloadf64, FP128, 8>;
166 // Convert a signed integer register value to a floating-point one.
167 def CEFBR : UnaryRRE<"cefb", 0xB394, sint_to_fp, FP32, GR32>;
168 def CDFBR : UnaryRRE<"cdfb", 0xB395, sint_to_fp, FP64, GR32>;
169 def CXFBR : UnaryRRE<"cxfb", 0xB396, sint_to_fp, FP128, GR32>;
171 def CEGBR : UnaryRRE<"cegb", 0xB3A4, sint_to_fp, FP32, GR64>;
172 def CDGBR : UnaryRRE<"cdgb", 0xB3A5, sint_to_fp, FP64, GR64>;
173 def CXGBR : UnaryRRE<"cxgb", 0xB3A6, sint_to_fp, FP128, GR64>;
175 // Convert am unsigned integer register value to a floating-point one.
176 let Predicates = [FeatureFPExtension] in {
177 def CELFBR : UnaryRRF4<"celfbr", 0xB390, FP32, GR32>;
178 def CDLFBR : UnaryRRF4<"cdlfbr", 0xB391, FP64, GR32>;
179 def CXLFBR : UnaryRRF4<"cxlfbr", 0xB392, FP128, GR32>;
181 def CELGBR : UnaryRRF4<"celgbr", 0xB3A0, FP32, GR64>;
182 def CDLGBR : UnaryRRF4<"cdlgbr", 0xB3A1, FP64, GR64>;
183 def CXLGBR : UnaryRRF4<"cxlgbr", 0xB3A2, FP128, GR64>;
185 def : Pat<(f32 (uint_to_fp GR32:$src)), (CELFBR 0, GR32:$src, 0)>;
186 def : Pat<(f64 (uint_to_fp GR32:$src)), (CDLFBR 0, GR32:$src, 0)>;
187 def : Pat<(f128 (uint_to_fp GR32:$src)), (CXLFBR 0, GR32:$src, 0)>;
189 def : Pat<(f32 (uint_to_fp GR64:$src)), (CELGBR 0, GR64:$src, 0)>;
190 def : Pat<(f64 (uint_to_fp GR64:$src)), (CDLGBR 0, GR64:$src, 0)>;
191 def : Pat<(f128 (uint_to_fp GR64:$src)), (CXLGBR 0, GR64:$src, 0)>;
194 // Convert a floating-point register value to a signed integer value,
195 // with the second operand (modifier M3) specifying the rounding mode.
197 def CFEBR : UnaryRRF<"cfeb", 0xB398, GR32, FP32>;
198 def CFDBR : UnaryRRF<"cfdb", 0xB399, GR32, FP64>;
199 def CFXBR : UnaryRRF<"cfxb", 0xB39A, GR32, FP128>;
201 def CGEBR : UnaryRRF<"cgeb", 0xB3A8, GR64, FP32>;
202 def CGDBR : UnaryRRF<"cgdb", 0xB3A9, GR64, FP64>;
203 def CGXBR : UnaryRRF<"cgxb", 0xB3AA, GR64, FP128>;
206 // fp_to_sint always rounds towards zero, which is modifier value 5.
207 def : Pat<(i32 (fp_to_sint FP32:$src)), (CFEBR 5, FP32:$src)>;
208 def : Pat<(i32 (fp_to_sint FP64:$src)), (CFDBR 5, FP64:$src)>;
209 def : Pat<(i32 (fp_to_sint FP128:$src)), (CFXBR 5, FP128:$src)>;
211 def : Pat<(i64 (fp_to_sint FP32:$src)), (CGEBR 5, FP32:$src)>;
212 def : Pat<(i64 (fp_to_sint FP64:$src)), (CGDBR 5, FP64:$src)>;
213 def : Pat<(i64 (fp_to_sint FP128:$src)), (CGXBR 5, FP128:$src)>;
215 // Convert a floating-point register value to an unsigned integer value.
216 let Predicates = [FeatureFPExtension] in {
218 def CLFEBR : UnaryRRF4<"clfebr", 0xB39C, GR32, FP32>;
219 def CLFDBR : UnaryRRF4<"clfdbr", 0xB39D, GR32, FP64>;
220 def CLFXBR : UnaryRRF4<"clfxbr", 0xB39E, GR32, FP128>;
222 def CLGEBR : UnaryRRF4<"clgebr", 0xB3AC, GR64, FP32>;
223 def CLGDBR : UnaryRRF4<"clgdbr", 0xB3AD, GR64, FP64>;
224 def CLGXBR : UnaryRRF4<"clgxbr", 0xB3AE, GR64, FP128>;
227 def : Pat<(i32 (fp_to_uint FP32:$src)), (CLFEBR 5, FP32:$src, 0)>;
228 def : Pat<(i32 (fp_to_uint FP64:$src)), (CLFDBR 5, FP64:$src, 0)>;
229 def : Pat<(i32 (fp_to_uint FP128:$src)), (CLFXBR 5, FP128:$src, 0)>;
231 def : Pat<(i64 (fp_to_uint FP32:$src)), (CLGEBR 5, FP32:$src, 0)>;
232 def : Pat<(i64 (fp_to_uint FP64:$src)), (CLGDBR 5, FP64:$src, 0)>;
233 def : Pat<(i64 (fp_to_uint FP128:$src)), (CLGXBR 5, FP128:$src, 0)>;
237 //===----------------------------------------------------------------------===//
239 //===----------------------------------------------------------------------===//
241 // Negation (Load Complement).
242 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
243 def LCEBR : UnaryRRE<"lceb", 0xB303, fneg, FP32, FP32>;
244 def LCDBR : UnaryRRE<"lcdb", 0xB313, fneg, FP64, FP64>;
245 def LCXBR : UnaryRRE<"lcxb", 0xB343, fneg, FP128, FP128>;
248 // Absolute value (Load Positive).
249 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
250 def LPEBR : UnaryRRE<"lpeb", 0xB300, fabs, FP32, FP32>;
251 def LPDBR : UnaryRRE<"lpdb", 0xB310, fabs, FP64, FP64>;
252 def LPXBR : UnaryRRE<"lpxb", 0xB340, fabs, FP128, FP128>;
255 // Negative absolute value (Load Negative).
256 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
257 def LNEBR : UnaryRRE<"lneb", 0xB301, fnabs, FP32, FP32>;
258 def LNDBR : UnaryRRE<"lndb", 0xB311, fnabs, FP64, FP64>;
259 def LNXBR : UnaryRRE<"lnxb", 0xB341, fnabs, FP128, FP128>;
263 def SQEBR : UnaryRRE<"sqeb", 0xB314, fsqrt, FP32, FP32>;
264 def SQDBR : UnaryRRE<"sqdb", 0xB315, fsqrt, FP64, FP64>;
265 def SQXBR : UnaryRRE<"sqxb", 0xB316, fsqrt, FP128, FP128>;
267 def SQEB : UnaryRXE<"sqeb", 0xED14, loadu<fsqrt>, FP32, 4>;
268 def SQDB : UnaryRXE<"sqdb", 0xED15, loadu<fsqrt>, FP64, 8>;
270 // Round to an integer, with the second operand (modifier M3) specifying
271 // the rounding mode. These forms always check for inexact conditions.
272 def FIEBR : UnaryRRF<"fieb", 0xB357, FP32, FP32>;
273 def FIDBR : UnaryRRF<"fidb", 0xB35F, FP64, FP64>;
274 def FIXBR : UnaryRRF<"fixb", 0xB347, FP128, FP128>;
276 // frint rounds according to the current mode (modifier 0) and detects
277 // inexact conditions.
278 def : Pat<(frint FP32:$src), (FIEBR 0, FP32:$src)>;
279 def : Pat<(frint FP64:$src), (FIDBR 0, FP64:$src)>;
280 def : Pat<(frint FP128:$src), (FIXBR 0, FP128:$src)>;
282 let Predicates = [FeatureFPExtension] in {
283 // Extended forms of the FIxBR instructions. M4 can be set to 4
284 // to suppress detection of inexact conditions.
285 def FIEBRA : UnaryRRF4<"fiebra", 0xB357, FP32, FP32>;
286 def FIDBRA : UnaryRRF4<"fidbra", 0xB35F, FP64, FP64>;
287 def FIXBRA : UnaryRRF4<"fixbra", 0xB347, FP128, FP128>;
289 // fnearbyint is like frint but does not detect inexact conditions.
290 def : Pat<(fnearbyint FP32:$src), (FIEBRA 0, FP32:$src, 4)>;
291 def : Pat<(fnearbyint FP64:$src), (FIDBRA 0, FP64:$src, 4)>;
292 def : Pat<(fnearbyint FP128:$src), (FIXBRA 0, FP128:$src, 4)>;
294 // floor is no longer allowed to raise an inexact condition,
295 // so restrict it to the cases where the condition can be suppressed.
296 // Mode 7 is round towards -inf.
297 def : Pat<(ffloor FP32:$src), (FIEBRA 7, FP32:$src, 4)>;
298 def : Pat<(ffloor FP64:$src), (FIDBRA 7, FP64:$src, 4)>;
299 def : Pat<(ffloor FP128:$src), (FIXBRA 7, FP128:$src, 4)>;
301 // Same idea for ceil, where mode 6 is round towards +inf.
302 def : Pat<(fceil FP32:$src), (FIEBRA 6, FP32:$src, 4)>;
303 def : Pat<(fceil FP64:$src), (FIDBRA 6, FP64:$src, 4)>;
304 def : Pat<(fceil FP128:$src), (FIXBRA 6, FP128:$src, 4)>;
306 // Same idea for trunc, where mode 5 is round towards zero.
307 def : Pat<(ftrunc FP32:$src), (FIEBRA 5, FP32:$src, 4)>;
308 def : Pat<(ftrunc FP64:$src), (FIDBRA 5, FP64:$src, 4)>;
309 def : Pat<(ftrunc FP128:$src), (FIXBRA 5, FP128:$src, 4)>;
311 // Same idea for round, where mode 1 is round towards nearest with
312 // ties away from zero.
313 def : Pat<(frnd FP32:$src), (FIEBRA 1, FP32:$src, 4)>;
314 def : Pat<(frnd FP64:$src), (FIDBRA 1, FP64:$src, 4)>;
315 def : Pat<(frnd FP128:$src), (FIXBRA 1, FP128:$src, 4)>;
318 //===----------------------------------------------------------------------===//
320 //===----------------------------------------------------------------------===//
323 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
324 let isCommutable = 1 in {
325 def AEBR : BinaryRRE<"aeb", 0xB30A, fadd, FP32, FP32>;
326 def ADBR : BinaryRRE<"adb", 0xB31A, fadd, FP64, FP64>;
327 def AXBR : BinaryRRE<"axb", 0xB34A, fadd, FP128, FP128>;
329 def AEB : BinaryRXE<"aeb", 0xED0A, fadd, FP32, load, 4>;
330 def ADB : BinaryRXE<"adb", 0xED1A, fadd, FP64, load, 8>;
334 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
335 def SEBR : BinaryRRE<"seb", 0xB30B, fsub, FP32, FP32>;
336 def SDBR : BinaryRRE<"sdb", 0xB31B, fsub, FP64, FP64>;
337 def SXBR : BinaryRRE<"sxb", 0xB34B, fsub, FP128, FP128>;
339 def SEB : BinaryRXE<"seb", 0xED0B, fsub, FP32, load, 4>;
340 def SDB : BinaryRXE<"sdb", 0xED1B, fsub, FP64, load, 8>;
344 let isCommutable = 1 in {
345 def MEEBR : BinaryRRE<"meeb", 0xB317, fmul, FP32, FP32>;
346 def MDBR : BinaryRRE<"mdb", 0xB31C, fmul, FP64, FP64>;
347 def MXBR : BinaryRRE<"mxb", 0xB34C, fmul, FP128, FP128>;
349 def MEEB : BinaryRXE<"meeb", 0xED17, fmul, FP32, load, 4>;
350 def MDB : BinaryRXE<"mdb", 0xED1C, fmul, FP64, load, 8>;
352 // f64 multiplication of two FP32 registers.
353 def MDEBR : BinaryRRE<"mdeb", 0xB30C, null_frag, FP64, FP32>;
354 def : Pat<(fmul (f64 (fextend FP32:$src1)), (f64 (fextend FP32:$src2))),
355 (MDEBR (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
356 FP32:$src1, subreg_r32), FP32:$src2)>;
358 // f64 multiplication of an FP32 register and an f32 memory.
359 def MDEB : BinaryRXE<"mdeb", 0xED0C, null_frag, FP64, load, 4>;
360 def : Pat<(fmul (f64 (fextend FP32:$src1)),
361 (f64 (extloadf32 bdxaddr12only:$addr))),
362 (MDEB (INSERT_SUBREG (f64 (IMPLICIT_DEF)), FP32:$src1, subreg_r32),
363 bdxaddr12only:$addr)>;
365 // f128 multiplication of two FP64 registers.
366 def MXDBR : BinaryRRE<"mxdb", 0xB307, null_frag, FP128, FP64>;
367 def : Pat<(fmul (f128 (fextend FP64:$src1)), (f128 (fextend FP64:$src2))),
368 (MXDBR (INSERT_SUBREG (f128 (IMPLICIT_DEF)),
369 FP64:$src1, subreg_h64), FP64:$src2)>;
371 // f128 multiplication of an FP64 register and an f64 memory.
372 def MXDB : BinaryRXE<"mxdb", 0xED07, null_frag, FP128, load, 8>;
373 def : Pat<(fmul (f128 (fextend FP64:$src1)),
374 (f128 (extloadf64 bdxaddr12only:$addr))),
375 (MXDB (INSERT_SUBREG (f128 (IMPLICIT_DEF)), FP64:$src1, subreg_h64),
376 bdxaddr12only:$addr)>;
378 // Fused multiply-add.
379 def MAEBR : TernaryRRD<"maeb", 0xB30E, z_fma, FP32>;
380 def MADBR : TernaryRRD<"madb", 0xB31E, z_fma, FP64>;
382 def MAEB : TernaryRXF<"maeb", 0xED0E, z_fma, FP32, load, 4>;
383 def MADB : TernaryRXF<"madb", 0xED1E, z_fma, FP64, load, 8>;
385 // Fused multiply-subtract.
386 def MSEBR : TernaryRRD<"mseb", 0xB30F, z_fms, FP32>;
387 def MSDBR : TernaryRRD<"msdb", 0xB31F, z_fms, FP64>;
389 def MSEB : TernaryRXF<"mseb", 0xED0F, z_fms, FP32, load, 4>;
390 def MSDB : TernaryRXF<"msdb", 0xED1F, z_fms, FP64, load, 8>;
393 def DEBR : BinaryRRE<"deb", 0xB30D, fdiv, FP32, FP32>;
394 def DDBR : BinaryRRE<"ddb", 0xB31D, fdiv, FP64, FP64>;
395 def DXBR : BinaryRRE<"dxb", 0xB34D, fdiv, FP128, FP128>;
397 def DEB : BinaryRXE<"deb", 0xED0D, fdiv, FP32, load, 4>;
398 def DDB : BinaryRXE<"ddb", 0xED1D, fdiv, FP64, load, 8>;
400 //===----------------------------------------------------------------------===//
402 //===----------------------------------------------------------------------===//
404 let Defs = [CC], CCValues = 0xF in {
405 def CEBR : CompareRRE<"ceb", 0xB309, z_fcmp, FP32, FP32>;
406 def CDBR : CompareRRE<"cdb", 0xB319, z_fcmp, FP64, FP64>;
407 def CXBR : CompareRRE<"cxb", 0xB349, z_fcmp, FP128, FP128>;
409 def CEB : CompareRXE<"ceb", 0xED09, z_fcmp, FP32, load, 4>;
410 def CDB : CompareRXE<"cdb", 0xED19, z_fcmp, FP64, load, 8>;
413 //===----------------------------------------------------------------------===//
415 //===----------------------------------------------------------------------===//
417 def : Pat<(f32 fpimmneg0), (LCEBR (LZER))>;
418 def : Pat<(f64 fpimmneg0), (LCDBR (LZDR))>;
419 def : Pat<(f128 fpimmneg0), (LCXBR (LZXR))>;