1 //===- SystemZInstrFP.td - SystemZ FP Instruction defs --------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the SystemZ (binary) floating point instructions in
13 //===----------------------------------------------------------------------===//
15 // FIXME: multiclassify!
17 //===----------------------------------------------------------------------===//
18 // FP Pattern fragments
20 def fpimm0 : PatLeaf<(fpimm), [{
21 return N->isExactlyValue(+0.0);
24 def fpimmneg0 : PatLeaf<(fpimm), [{
25 return N->isExactlyValue(-0.0);
28 let usesCustomDAGSchedInserter = 1 in {
29 def SelectF32 : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, i8imm:$cc),
32 (SystemZselect FP32:$src1, FP32:$src2, imm:$cc))]>;
33 def SelectF64 : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, i8imm:$cc),
36 (SystemZselect FP64:$src1, FP64:$src2, imm:$cc))]>;
39 //===----------------------------------------------------------------------===//
42 // Floating point constant loads.
43 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
44 def LD_Fp032 : Pseudo<(outs FP32:$dst), (ins),
46 [(set FP32:$dst, fpimm0)]>;
47 def LD_Fp064 : Pseudo<(outs FP64:$dst), (ins),
49 [(set FP64:$dst, fpimm0)]>;
52 let neverHasSideEffects = 1 in {
53 def FMOV32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
56 def FMOV64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
61 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
62 def FMOV32rm : Pseudo<(outs FP32:$dst), (ins rriaddr12:$src),
64 [(set FP32:$dst, (load rriaddr12:$src))]>;
65 def FMOV32rmy : Pseudo<(outs FP32:$dst), (ins rriaddr:$src),
67 [(set FP32:$dst, (load rriaddr:$src))]>;
68 def FMOV64rm : Pseudo<(outs FP64:$dst), (ins rriaddr12:$src),
70 [(set FP64:$dst, (load rriaddr12:$src))]>;
71 def FMOV64rmy : Pseudo<(outs FP64:$dst), (ins rriaddr:$src),
73 [(set FP64:$dst, (load rriaddr:$src))]>;
76 def FMOV32mr : Pseudo<(outs), (ins rriaddr12:$dst, FP32:$src),
78 [(store FP32:$src, rriaddr12:$dst)]>;
79 def FMOV32mry : Pseudo<(outs), (ins rriaddr:$dst, FP32:$src),
81 [(store FP32:$src, rriaddr:$dst)]>;
82 def FMOV64mr : Pseudo<(outs), (ins rriaddr12:$dst, FP64:$src),
84 [(store FP64:$src, rriaddr12:$dst)]>;
85 def FMOV64mry : Pseudo<(outs), (ins rriaddr:$dst, FP64:$src),
87 [(store FP64:$src, rriaddr:$dst)]>;
89 //===----------------------------------------------------------------------===//
90 // Arithmetic Instructions
94 def FNEG32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
95 "lcebr\t{$dst, $src}",
96 [(set FP32:$dst, (fneg FP32:$src)),
98 def FNEG64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
99 "lcdbr\t{$dst, $src}",
100 [(set FP64:$dst, (fneg FP64:$src)),
103 def FABS32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
104 "lpebr\t{$dst, $src}",
105 [(set FP32:$dst, (fabs FP32:$src)),
107 def FABS64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
108 "lpdbr\t{$dst, $src}",
109 [(set FP64:$dst, (fabs FP64:$src)),
112 def FNABS32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
113 "lnebr\t{$dst, $src}",
114 [(set FP32:$dst, (fneg(fabs FP32:$src))),
116 def FNABS64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
117 "lndbr\t{$dst, $src}",
118 [(set FP64:$dst, (fneg(fabs FP64:$src))),
122 let isTwoAddress = 1 in {
123 let Defs = [PSW] in {
124 let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y
125 def FADD32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
126 "aebr\t{$dst, $src2}",
127 [(set FP32:$dst, (fadd FP32:$src1, FP32:$src2)),
129 def FADD64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
130 "adbr\t{$dst, $src2}",
131 [(set FP64:$dst, (fadd FP64:$src1, FP64:$src2)),
135 def FADD32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2),
136 "aeb\t{$dst, $src2}",
137 [(set FP32:$dst, (fadd FP32:$src1, (load rriaddr:$src2))),
139 def FADD64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2),
140 "adb\t{$dst, $src2}",
141 [(set FP64:$dst, (fadd FP64:$src1, (load rriaddr:$src2))),
144 def FSUB32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
145 "sebr\t{$dst, $src2}",
146 [(set FP32:$dst, (fsub FP32:$src1, FP32:$src2)),
148 def FSUB64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
149 "sdbr\t{$dst, $src2}",
150 [(set FP64:$dst, (fsub FP64:$src1, FP64:$src2)),
153 def FSUB32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2),
154 "seb\t{$dst, $src2}",
155 [(set FP32:$dst, (fsub FP32:$src1, (load rriaddr:$src2))),
157 def FSUB64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2),
158 "sdb\t{$dst, $src2}",
159 [(set FP64:$dst, (fsub FP64:$src1, (load rriaddr:$src2))),
163 let isCommutable = 1 in { // X = MUL Y, Z == X = MUL Z, Y
164 def FMUL32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
165 "meebr\t{$dst, $src2}",
166 [(set FP32:$dst, (fmul FP32:$src1, FP32:$src2))]>;
167 def FMUL64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
168 "mdbr\t{$dst, $src2}",
169 [(set FP64:$dst, (fmul FP64:$src1, FP64:$src2))]>;
172 def FMUL32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2),
173 "meeb\t{$dst, $src2}",
174 [(set FP32:$dst, (fmul FP32:$src1, (load rriaddr:$src2)))]>;
175 def FMUL64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2),
176 "mdb\t{$dst, $src2}",
177 [(set FP64:$dst, (fmul FP64:$src1, (load rriaddr:$src2)))]>;
179 def FMADD32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, FP32:$src3),
180 "maebr\t{$dst, $src3, $src2}",
181 [(set FP32:$dst, (fadd (fmul FP32:$src2, FP32:$src3),
183 def FMADD32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2, FP32:$src3),
184 "maeb\t{$dst, $src3, $src2}",
185 [(set FP32:$dst, (fadd (fmul (load rriaddr:$src2),
189 def FMADD64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, FP64:$src3),
190 "madbr\t{$dst, $src3, $src2}",
191 [(set FP64:$dst, (fadd (fmul FP64:$src2, FP64:$src3),
193 def FMADD64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2, FP64:$src3),
194 "madb\t{$dst, $src3, $src2}",
195 [(set FP64:$dst, (fadd (fmul (load rriaddr:$src2),
199 def FMSUB32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, FP32:$src3),
200 "msebr\t{$dst, $src3, $src2}",
201 [(set FP32:$dst, (fsub (fmul FP32:$src2, FP32:$src3),
203 def FMSUB32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2, FP32:$src3),
204 "mseb\t{$dst, $src3, $src2}",
205 [(set FP32:$dst, (fsub (fmul (load rriaddr:$src2),
209 def FMSUB64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, FP64:$src3),
210 "msdbr\t{$dst, $src3, $src2}",
211 [(set FP64:$dst, (fsub (fmul FP64:$src2, FP64:$src3),
213 def FMSUB64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2, FP64:$src3),
214 "msdb\t{$dst, $src3, $src2}",
215 [(set FP64:$dst, (fsub (fmul (load rriaddr:$src2),
219 def FDIV32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
220 "debr\t{$dst, $src2}",
221 [(set FP32:$dst, (fdiv FP32:$src1, FP32:$src2))]>;
222 def FDIV64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
223 "ddbr\t{$dst, $src2}",
224 [(set FP64:$dst, (fdiv FP64:$src1, FP64:$src2))]>;
226 def FDIV32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2),
227 "deb\t{$dst, $src2}",
228 [(set FP32:$dst, (fdiv FP32:$src1, (load rriaddr:$src2)))]>;
229 def FDIV64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2),
230 "ddb\t{$dst, $src2}",
231 [(set FP64:$dst, (fdiv FP64:$src1, (load rriaddr:$src2)))]>;
233 } // isTwoAddress = 1
235 def FSQRT32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
236 "sqebr\t{$dst, $src}",
237 [(set FP32:$dst, (fsqrt FP32:$src))]>;
238 def FSQRT64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
239 "sqdbr\t{$dst, $src}",
240 [(set FP64:$dst, (fsqrt FP64:$src))]>;
242 def FSQRT32rm : Pseudo<(outs FP32:$dst), (ins rriaddr:$src),
243 "sqeb\t{$dst, $src}",
244 [(set FP32:$dst, (fsqrt (load rriaddr:$src)))]>;
245 def FSQRT64rm : Pseudo<(outs FP64:$dst), (ins rriaddr:$src),
246 "sqdb\t{$dst, $src}",
247 [(set FP64:$dst, (fsqrt (load rriaddr:$src)))]>;
249 def FROUND64r32 : Pseudo<(outs FP32:$dst), (ins FP64:$src),
250 "ledbr\t{$dst, $src}",
251 [(set FP32:$dst, (fround FP64:$src))]>;
253 def FEXT32r64 : Pseudo<(outs FP64:$dst), (ins FP32:$src),
254 "ldebr\t{$dst, $src}",
255 [(set FP64:$dst, (fextend FP32:$src))]>;
256 def FEXT32m64 : Pseudo<(outs FP64:$dst), (ins rriaddr:$src),
257 "ldeb\t{$dst, $src}",
258 [(set FP64:$dst, (fextend (load rriaddr:$src)))]>;
260 let Defs = [PSW] in {
261 def FCONVFP32 : Pseudo<(outs FP32:$dst), (ins GR32:$src),
262 "cefbr\t{$dst, $src}",
263 [(set FP32:$dst, (sint_to_fp GR32:$src)),
265 def FCONVFP32r64: Pseudo<(outs FP32:$dst), (ins GR64:$src),
266 "cegbr\t{$dst, $src}",
267 [(set FP32:$dst, (sint_to_fp GR64:$src)),
270 def FCONVFP64r32: Pseudo<(outs FP64:$dst), (ins GR32:$src),
271 "cdfbr\t{$dst, $src}",
272 [(set FP64:$dst, (sint_to_fp GR32:$src)),
274 def FCONVFP64 : Pseudo<(outs FP64:$dst), (ins GR64:$src),
275 "cdgbr\t{$dst, $src}",
276 [(set FP64:$dst, (sint_to_fp GR64:$src)),
279 def FCONVGR32 : Pseudo<(outs GR32:$dst), (ins FP32:$src),
280 "cfebr\t{$dst, $src}",
281 [(set GR32:$dst, (fp_to_sint FP32:$src)),
283 def FCONVGR32r64: Pseudo<(outs GR32:$dst), (ins FP64:$src),
284 "cgebr\t{$dst, $src}",
285 [(set GR32:$dst, (fp_to_sint FP64:$src)),
288 def FCONVGR64r32: Pseudo<(outs GR64:$dst), (ins FP32:$src),
289 "cfdbr\t{$dst, $src}",
290 [(set GR64:$dst, (fp_to_sint FP32:$src)),
292 def FCONVGR64 : Pseudo<(outs GR64:$dst), (ins FP64:$src),
293 "cgdbr\t{$dst, $src}",
294 [(set GR64:$dst, (fp_to_sint FP64:$src)),
298 //===----------------------------------------------------------------------===//
299 // Test instructions (like AND but do not produce any result)
301 // Integer comparisons
302 let Defs = [PSW] in {
303 def FCMP32rr : Pseudo<(outs), (ins FP32:$src1, FP32:$src2),
304 "cebr\t$src1, $src2",
305 [(SystemZcmp FP32:$src1, FP32:$src2), (implicit PSW)]>;
306 def FCMP64rr : Pseudo<(outs), (ins FP64:$src1, FP64:$src2),
307 "cdbr\t$src1, $src2",
308 [(SystemZcmp FP64:$src1, FP64:$src2), (implicit PSW)]>;
310 def FCMP32rm : Pseudo<(outs), (ins FP32:$src1, rriaddr:$src2),
312 [(SystemZcmp FP32:$src1, (load rriaddr:$src2)),
314 def FCMP64rm : Pseudo<(outs), (ins FP64:$src1, rriaddr:$src2),
316 [(SystemZcmp FP64:$src1, (load rriaddr:$src2)),
320 //===----------------------------------------------------------------------===//
321 // Non-Instruction Patterns
322 //===----------------------------------------------------------------------===//
324 // Floating point constant -0.0
325 def : Pat<(f32 fpimmneg0), (FNEG32rr (LD_Fp032))>;
326 def : Pat<(f64 fpimmneg0), (FNEG64rr (LD_Fp064))>;