1 //==- SystemZInstrFP.td - Floating-point SystemZ instructions --*- tblgen-*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Select instructions
12 //===----------------------------------------------------------------------===//
14 // C's ?: operator for floating-point operands.
15 def SelectF32 : SelectWrapper<FP32>;
16 def SelectF64 : SelectWrapper<FP64>;
17 def SelectF128 : SelectWrapper<FP128>;
19 defm CondStoreF32 : CondStores<FP32, nonvolatile_store,
20 nonvolatile_load, bdxaddr20only>;
21 defm CondStoreF64 : CondStores<FP64, nonvolatile_store,
22 nonvolatile_load, bdxaddr20only>;
24 //===----------------------------------------------------------------------===//
26 //===----------------------------------------------------------------------===//
29 let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
30 def LZER : InherentRRE<"lze", 0xB374, FP32, (fpimm0)>;
31 def LZDR : InherentRRE<"lzd", 0xB375, FP64, (fpimm0)>;
32 def LZXR : InherentRRE<"lzx", 0xB376, FP128, (fpimm0)>;
35 // Moves between two floating-point registers.
36 let neverHasSideEffects = 1 in {
37 def LER : UnaryRR <"le", 0x38, null_frag, FP32, FP32>;
38 def LDR : UnaryRR <"ld", 0x28, null_frag, FP64, FP64>;
39 def LXR : UnaryRRE<"lx", 0xB365, null_frag, FP128, FP128>;
42 // Moves between 64-bit integer and floating-point registers.
43 def LGDR : UnaryRRE<"lgd", 0xB3CD, bitconvert, GR64, FP64>;
44 def LDGR : UnaryRRE<"ldg", 0xB3C1, bitconvert, FP64, GR64>;
46 // fcopysign with an FP32 result.
47 let isCodeGenOnly = 1 in {
48 def CPSDRss : BinaryRRF<"cpsd", 0xB372, fcopysign, FP32, FP32>;
49 def CPSDRsd : BinaryRRF<"cpsd", 0xB372, fcopysign, FP32, FP64>;
52 // The sign of an FP128 is in the high register.
53 def : Pat<(fcopysign FP32:$src1, FP128:$src2),
54 (CPSDRsd FP32:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_high))>;
56 // fcopysign with an FP64 result.
57 let isCodeGenOnly = 1 in
58 def CPSDRds : BinaryRRF<"cpsd", 0xB372, fcopysign, FP64, FP32>;
59 def CPSDRdd : BinaryRRF<"cpsd", 0xB372, fcopysign, FP64, FP64>;
61 // The sign of an FP128 is in the high register.
62 def : Pat<(fcopysign FP64:$src1, FP128:$src2),
63 (CPSDRdd FP64:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_high))>;
65 // fcopysign with an FP128 result. Use "upper" as the high half and leave
66 // the low half as-is.
67 class CopySign128<RegisterOperand cls, dag upper>
68 : Pat<(fcopysign FP128:$src1, cls:$src2),
69 (INSERT_SUBREG FP128:$src1, upper, subreg_high)>;
71 def : CopySign128<FP32, (CPSDRds (EXTRACT_SUBREG FP128:$src1, subreg_high),
73 def : CopySign128<FP64, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_high),
75 def : CopySign128<FP128, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_high),
76 (EXTRACT_SUBREG FP128:$src2, subreg_high))>;
78 //===----------------------------------------------------------------------===//
80 //===----------------------------------------------------------------------===//
82 let canFoldAsLoad = 1, SimpleBDXLoad = 1 in {
83 defm LE : UnaryRXPair<"le", 0x78, 0xED64, load, FP32, 4>;
84 defm LD : UnaryRXPair<"ld", 0x68, 0xED65, load, FP64, 8>;
86 // These instructions are split after register allocation, so we don't
87 // want a custom inserter.
88 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
89 def LX : Pseudo<(outs FP128:$dst), (ins bdxaddr20only128:$src),
90 [(set FP128:$dst, (load bdxaddr20only128:$src))]>;
94 //===----------------------------------------------------------------------===//
96 //===----------------------------------------------------------------------===//
98 let SimpleBDXStore = 1 in {
99 defm STE : StoreRXPair<"ste", 0x70, 0xED66, store, FP32, 4>;
100 defm STD : StoreRXPair<"std", 0x60, 0xED67, store, FP64, 8>;
102 // These instructions are split after register allocation, so we don't
103 // want a custom inserter.
104 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
105 def STX : Pseudo<(outs), (ins FP128:$src, bdxaddr20only128:$dst),
106 [(store FP128:$src, bdxaddr20only128:$dst)]>;
110 //===----------------------------------------------------------------------===//
111 // Conversion instructions
112 //===----------------------------------------------------------------------===//
114 // Convert floating-point values to narrower representations, rounding
115 // according to the current mode. The destination of LEXBR and LDXBR
116 // is a 128-bit value, but only the first register of the pair is used.
117 def LEDBR : UnaryRRE<"ledb", 0xB344, fround, FP32, FP64>;
118 def LEXBR : UnaryRRE<"lexb", 0xB346, null_frag, FP128, FP128>;
119 def LDXBR : UnaryRRE<"ldxb", 0xB345, null_frag, FP128, FP128>;
121 def : Pat<(f32 (fround FP128:$src)),
122 (EXTRACT_SUBREG (LEXBR FP128:$src), subreg_32bit)>;
123 def : Pat<(f64 (fround FP128:$src)),
124 (EXTRACT_SUBREG (LDXBR FP128:$src), subreg_high)>;
126 // Extend register floating-point values to wider representations.
127 def LDEBR : UnaryRRE<"ldeb", 0xB304, fextend, FP64, FP32>;
128 def LXEBR : UnaryRRE<"lxeb", 0xB306, fextend, FP128, FP32>;
129 def LXDBR : UnaryRRE<"lxdb", 0xB305, fextend, FP128, FP64>;
131 // Extend memory floating-point values to wider representations.
132 def LDEB : UnaryRXE<"ldeb", 0xED04, extloadf32, FP64, 4>;
133 def LXEB : UnaryRXE<"lxeb", 0xED06, extloadf32, FP128, 4>;
134 def LXDB : UnaryRXE<"lxdb", 0xED05, extloadf64, FP128, 8>;
136 // Convert a signed integer register value to a floating-point one.
138 def CEFBR : UnaryRRE<"cefb", 0xB394, sint_to_fp, FP32, GR32>;
139 def CDFBR : UnaryRRE<"cdfb", 0xB395, sint_to_fp, FP64, GR32>;
140 def CXFBR : UnaryRRE<"cxfb", 0xB396, sint_to_fp, FP128, GR32>;
142 def CEGBR : UnaryRRE<"cegb", 0xB3A4, sint_to_fp, FP32, GR64>;
143 def CDGBR : UnaryRRE<"cdgb", 0xB3A5, sint_to_fp, FP64, GR64>;
144 def CXGBR : UnaryRRE<"cxgb", 0xB3A6, sint_to_fp, FP128, GR64>;
147 // Convert a floating-point register value to a signed integer value,
148 // with the second operand (modifier M3) specifying the rounding mode.
150 def CFEBR : UnaryRRF<"cfeb", 0xB398, GR32, FP32>;
151 def CFDBR : UnaryRRF<"cfdb", 0xB399, GR32, FP64>;
152 def CFXBR : UnaryRRF<"cfxb", 0xB39A, GR32, FP128>;
154 def CGEBR : UnaryRRF<"cgeb", 0xB3A8, GR64, FP32>;
155 def CGDBR : UnaryRRF<"cgdb", 0xB3A9, GR64, FP64>;
156 def CGXBR : UnaryRRF<"cgxb", 0xB3AA, GR64, FP128>;
159 // fp_to_sint always rounds towards zero, which is modifier value 5.
160 def : Pat<(i32 (fp_to_sint FP32:$src)), (CFEBR 5, FP32:$src)>;
161 def : Pat<(i32 (fp_to_sint FP64:$src)), (CFDBR 5, FP64:$src)>;
162 def : Pat<(i32 (fp_to_sint FP128:$src)), (CFXBR 5, FP128:$src)>;
164 def : Pat<(i64 (fp_to_sint FP32:$src)), (CGEBR 5, FP32:$src)>;
165 def : Pat<(i64 (fp_to_sint FP64:$src)), (CGDBR 5, FP64:$src)>;
166 def : Pat<(i64 (fp_to_sint FP128:$src)), (CGXBR 5, FP128:$src)>;
168 //===----------------------------------------------------------------------===//
170 //===----------------------------------------------------------------------===//
172 // Negation (Load Complement).
174 def LCEBR : UnaryRRE<"lceb", 0xB303, fneg, FP32, FP32>;
175 def LCDBR : UnaryRRE<"lcdb", 0xB313, fneg, FP64, FP64>;
176 def LCXBR : UnaryRRE<"lcxb", 0xB343, fneg, FP128, FP128>;
179 // Absolute value (Load Positive).
181 def LPEBR : UnaryRRE<"lpeb", 0xB300, fabs, FP32, FP32>;
182 def LPDBR : UnaryRRE<"lpdb", 0xB310, fabs, FP64, FP64>;
183 def LPXBR : UnaryRRE<"lpxb", 0xB340, fabs, FP128, FP128>;
186 // Negative absolute value (Load Negative).
188 def LNEBR : UnaryRRE<"lneb", 0xB301, fnabs, FP32, FP32>;
189 def LNDBR : UnaryRRE<"lndb", 0xB311, fnabs, FP64, FP64>;
190 def LNXBR : UnaryRRE<"lnxb", 0xB341, fnabs, FP128, FP128>;
194 def SQEBR : UnaryRRE<"sqeb", 0xB314, fsqrt, FP32, FP32>;
195 def SQDBR : UnaryRRE<"sqdb", 0xB315, fsqrt, FP64, FP64>;
196 def SQXBR : UnaryRRE<"sqxb", 0xB316, fsqrt, FP128, FP128>;
198 def SQEB : UnaryRXE<"sqeb", 0xED14, loadu<fsqrt>, FP32, 4>;
199 def SQDB : UnaryRXE<"sqdb", 0xED15, loadu<fsqrt>, FP64, 8>;
201 // Round to an integer, with the second operand (modifier M3) specifying
202 // the rounding mode.
204 // These forms always check for inexact conditions. z196 added versions
205 // that allow this to suppressed (as for fnearbyint), but we don't yet
206 // support -march=z196.
208 def FIEBR : UnaryRRF<"fieb", 0xB357, FP32, FP32>;
209 def FIDBR : UnaryRRF<"fidb", 0xB35F, FP64, FP64>;
210 def FIXBR : UnaryRRF<"fixb", 0xB347, FP128, FP128>;
213 // frint rounds according to the current mode (modifier 0) and detects
214 // inexact conditions.
215 def : Pat<(frint FP32:$src), (FIEBR 0, FP32:$src)>;
216 def : Pat<(frint FP64:$src), (FIDBR 0, FP64:$src)>;
217 def : Pat<(frint FP128:$src), (FIXBR 0, FP128:$src)>;
219 //===----------------------------------------------------------------------===//
221 //===----------------------------------------------------------------------===//
225 let isCommutable = 1 in {
226 def AEBR : BinaryRRE<"aeb", 0xB30A, fadd, FP32, FP32>;
227 def ADBR : BinaryRRE<"adb", 0xB31A, fadd, FP64, FP64>;
228 def AXBR : BinaryRRE<"axb", 0xB34A, fadd, FP128, FP128>;
230 def AEB : BinaryRXE<"aeb", 0xED0A, fadd, FP32, load, 4>;
231 def ADB : BinaryRXE<"adb", 0xED1A, fadd, FP64, load, 8>;
236 def SEBR : BinaryRRE<"seb", 0xB30B, fsub, FP32, FP32>;
237 def SDBR : BinaryRRE<"sdb", 0xB31B, fsub, FP64, FP64>;
238 def SXBR : BinaryRRE<"sxb", 0xB34B, fsub, FP128, FP128>;
240 def SEB : BinaryRXE<"seb", 0xED0B, fsub, FP32, load, 4>;
241 def SDB : BinaryRXE<"sdb", 0xED1B, fsub, FP64, load, 8>;
245 let isCommutable = 1 in {
246 def MEEBR : BinaryRRE<"meeb", 0xB317, fmul, FP32, FP32>;
247 def MDBR : BinaryRRE<"mdb", 0xB31C, fmul, FP64, FP64>;
248 def MXBR : BinaryRRE<"mxb", 0xB34C, fmul, FP128, FP128>;
250 def MEEB : BinaryRXE<"meeb", 0xED17, fmul, FP32, load, 4>;
251 def MDB : BinaryRXE<"mdb", 0xED1C, fmul, FP64, load, 8>;
253 // f64 multiplication of two FP32 registers.
254 def MDEBR : BinaryRRE<"mdeb", 0xB30C, null_frag, FP64, FP32>;
255 def : Pat<(fmul (f64 (fextend FP32:$src1)), (f64 (fextend FP32:$src2))),
256 (MDEBR (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
257 FP32:$src1, subreg_32bit), FP32:$src2)>;
259 // f64 multiplication of an FP32 register and an f32 memory.
260 def MDEB : BinaryRXE<"mdeb", 0xED0C, null_frag, FP64, load, 4>;
261 def : Pat<(fmul (f64 (fextend FP32:$src1)),
262 (f64 (extloadf32 bdxaddr12only:$addr))),
263 (MDEB (INSERT_SUBREG (f64 (IMPLICIT_DEF)), FP32:$src1, subreg_32bit),
264 bdxaddr12only:$addr)>;
266 // f128 multiplication of two FP64 registers.
267 def MXDBR : BinaryRRE<"mxdb", 0xB307, null_frag, FP128, FP64>;
268 def : Pat<(fmul (f128 (fextend FP64:$src1)), (f128 (fextend FP64:$src2))),
269 (MXDBR (INSERT_SUBREG (f128 (IMPLICIT_DEF)),
270 FP64:$src1, subreg_high), FP64:$src2)>;
272 // f128 multiplication of an FP64 register and an f64 memory.
273 def MXDB : BinaryRXE<"mxdb", 0xED07, null_frag, FP128, load, 8>;
274 def : Pat<(fmul (f128 (fextend FP64:$src1)),
275 (f128 (extloadf64 bdxaddr12only:$addr))),
276 (MXDB (INSERT_SUBREG (f128 (IMPLICIT_DEF)), FP64:$src1, subreg_high),
277 bdxaddr12only:$addr)>;
279 // Fused multiply-add.
280 def MAEBR : TernaryRRD<"maeb", 0xB30E, z_fma, FP32>;
281 def MADBR : TernaryRRD<"madb", 0xB31E, z_fma, FP64>;
283 def MAEB : TernaryRXF<"maeb", 0xED0E, z_fma, FP32, load, 4>;
284 def MADB : TernaryRXF<"madb", 0xED1E, z_fma, FP64, load, 8>;
286 // Fused multiply-subtract.
287 def MSEBR : TernaryRRD<"mseb", 0xB30F, z_fms, FP32>;
288 def MSDBR : TernaryRRD<"msdb", 0xB31F, z_fms, FP64>;
290 def MSEB : TernaryRXF<"mseb", 0xED0F, z_fms, FP32, load, 4>;
291 def MSDB : TernaryRXF<"msdb", 0xED1F, z_fms, FP64, load, 8>;
294 def DEBR : BinaryRRE<"deb", 0xB30D, fdiv, FP32, FP32>;
295 def DDBR : BinaryRRE<"ddb", 0xB31D, fdiv, FP64, FP64>;
296 def DXBR : BinaryRRE<"dxb", 0xB34D, fdiv, FP128, FP128>;
298 def DEB : BinaryRXE<"deb", 0xED0D, fdiv, FP32, load, 4>;
299 def DDB : BinaryRXE<"ddb", 0xED1D, fdiv, FP64, load, 8>;
301 //===----------------------------------------------------------------------===//
303 //===----------------------------------------------------------------------===//
306 def CEBR : CompareRRE<"ceb", 0xB309, z_cmp, FP32, FP32>;
307 def CDBR : CompareRRE<"cdb", 0xB319, z_cmp, FP64, FP64>;
308 def CXBR : CompareRRE<"cxb", 0xB349, z_cmp, FP128, FP128>;
310 def CEB : CompareRXE<"ceb", 0xED09, z_cmp, FP32, load, 4>;
311 def CDB : CompareRXE<"cdb", 0xED19, z_cmp, FP64, load, 8>;
314 //===----------------------------------------------------------------------===//
316 //===----------------------------------------------------------------------===//
318 def : Pat<(f32 fpimmneg0), (LCEBR (LZER))>;
319 def : Pat<(f64 fpimmneg0), (LCDBR (LZDR))>;
320 def : Pat<(f128 fpimmneg0), (LCXBR (LZXR))>;