1 //==- SystemZInstrFP.td - Floating-point SystemZ instructions --*- tblgen-*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Control-flow instructions
12 //===----------------------------------------------------------------------===//
14 // C's ?: operator for floating-point operands.
15 def SelectF32 : SelectWrapper<FP32>;
16 def SelectF64 : SelectWrapper<FP64>;
17 def SelectF128 : SelectWrapper<FP128>;
19 //===----------------------------------------------------------------------===//
21 //===----------------------------------------------------------------------===//
24 let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
25 def LZER : InherentRRE<"lzer", 0xB374, FP32, (fpimm0)>;
26 def LZDR : InherentRRE<"lzdr", 0xB375, FP64, (fpimm0)>;
27 def LZXR : InherentRRE<"lzxr", 0xB376, FP128, (fpimm0)>;
30 // Moves between two floating-point registers.
31 let neverHasSideEffects = 1 in {
32 def LER : UnaryRR <"ler", 0x38, null_frag, FP32, FP32>;
33 def LDR : UnaryRR <"ldr", 0x28, null_frag, FP64, FP64>;
34 def LXR : UnaryRRE<"lxr", 0xB365, null_frag, FP128, FP128>;
37 // Moves between 64-bit integer and floating-point registers.
38 def LGDR : UnaryRRE<"lgdr", 0xB3CD, bitconvert, GR64, FP64>;
39 def LDGR : UnaryRRE<"ldgr", 0xB3C1, bitconvert, FP64, GR64>;
41 // fcopysign with an FP32 result.
42 let isCodeGenOnly = 1 in {
43 def CPSDRss : BinaryRRF<"cpsdr", 0xB372, fcopysign, FP32, FP32>;
44 def CPSDRsd : BinaryRRF<"cpsdr", 0xB372, fcopysign, FP32, FP64>;
47 // The sign of an FP128 is in the high register.
48 def : Pat<(fcopysign FP32:$src1, FP128:$src2),
49 (CPSDRsd FP32:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_high))>;
51 // fcopysign with an FP64 result.
52 let isCodeGenOnly = 1 in
53 def CPSDRds : BinaryRRF<"cpsdr", 0xB372, fcopysign, FP64, FP32>;
54 def CPSDRdd : BinaryRRF<"cpsdr", 0xB372, fcopysign, FP64, FP64>;
56 // The sign of an FP128 is in the high register.
57 def : Pat<(fcopysign FP64:$src1, FP128:$src2),
58 (CPSDRdd FP64:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_high))>;
60 // fcopysign with an FP128 result. Use "upper" as the high half and leave
61 // the low half as-is.
62 class CopySign128<RegisterOperand cls, dag upper>
63 : Pat<(fcopysign FP128:$src1, cls:$src2),
64 (INSERT_SUBREG FP128:$src1, upper, subreg_high)>;
66 def : CopySign128<FP32, (CPSDRds (EXTRACT_SUBREG FP128:$src1, subreg_high),
68 def : CopySign128<FP64, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_high),
70 def : CopySign128<FP128, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_high),
71 (EXTRACT_SUBREG FP128:$src2, subreg_high))>;
73 //===----------------------------------------------------------------------===//
75 //===----------------------------------------------------------------------===//
77 let canFoldAsLoad = 1, SimpleBDXLoad = 1 in {
78 defm LE : UnaryRXPair<"le", 0x78, 0xED64, load, FP32>;
79 defm LD : UnaryRXPair<"ld", 0x68, 0xED65, load, FP64>;
81 // These instructions are split after register allocation, so we don't
82 // want a custom inserter.
83 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
84 def LX : Pseudo<(outs FP128:$dst), (ins bdxaddr20only128:$src),
85 [(set FP128:$dst, (load bdxaddr20only128:$src))]>;
89 //===----------------------------------------------------------------------===//
91 //===----------------------------------------------------------------------===//
93 let SimpleBDXStore = 1 in {
94 defm STE : StoreRXPair<"ste", 0x70, 0xED66, store, FP32>;
95 defm STD : StoreRXPair<"std", 0x60, 0xED67, store, FP64>;
97 // These instructions are split after register allocation, so we don't
98 // want a custom inserter.
99 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
100 def STX : Pseudo<(outs), (ins FP128:$src, bdxaddr20only128:$dst),
101 [(store FP128:$src, bdxaddr20only128:$dst)]>;
105 //===----------------------------------------------------------------------===//
106 // Conversion instructions
107 //===----------------------------------------------------------------------===//
109 // Convert floating-point values to narrower representations, rounding
110 // according to the current mode. The destination of LEXBR and LDXBR
111 // is a 128-bit value, but only the first register of the pair is used.
112 def LEDBR : UnaryRRE<"ledbr", 0xB344, fround, FP32, FP64>;
113 def LEXBR : UnaryRRE<"lexbr", 0xB346, null_frag, FP128, FP128>;
114 def LDXBR : UnaryRRE<"ldxbr", 0xB345, null_frag, FP128, FP128>;
116 def : Pat<(f32 (fround FP128:$src)),
117 (EXTRACT_SUBREG (LEXBR FP128:$src), subreg_32bit)>;
118 def : Pat<(f64 (fround FP128:$src)),
119 (EXTRACT_SUBREG (LDXBR FP128:$src), subreg_high)>;
121 // Extend register floating-point values to wider representations.
122 def LDEBR : UnaryRRE<"ldebr", 0xB304, fextend, FP64, FP32>;
123 def LXEBR : UnaryRRE<"lxebr", 0xB306, fextend, FP128, FP32>;
124 def LXDBR : UnaryRRE<"lxdbr", 0xB305, fextend, FP128, FP64>;
126 // Extend memory floating-point values to wider representations.
127 def LDEB : UnaryRXE<"ldeb", 0xED04, extloadf32, FP64>;
128 def LXEB : UnaryRXE<"lxeb", 0xED06, extloadf32, FP128>;
129 def LXDB : UnaryRXE<"lxdb", 0xED05, extloadf64, FP128>;
131 // Convert a signed integer register value to a floating-point one.
133 def CEFBR : UnaryRRE<"cefbr", 0xB394, sint_to_fp, FP32, GR32>;
134 def CDFBR : UnaryRRE<"cdfbr", 0xB395, sint_to_fp, FP64, GR32>;
135 def CXFBR : UnaryRRE<"cxfbr", 0xB396, sint_to_fp, FP128, GR32>;
137 def CEGBR : UnaryRRE<"cegbr", 0xB3A4, sint_to_fp, FP32, GR64>;
138 def CDGBR : UnaryRRE<"cdgbr", 0xB3A5, sint_to_fp, FP64, GR64>;
139 def CXGBR : UnaryRRE<"cxgbr", 0xB3A6, sint_to_fp, FP128, GR64>;
142 // Convert a floating-point register value to a signed integer value,
143 // with the second operand (modifier M3) specifying the rounding mode.
145 def CFEBR : UnaryRRF<"cfebr", 0xB398, GR32, FP32>;
146 def CFDBR : UnaryRRF<"cfdbr", 0xB399, GR32, FP64>;
147 def CFXBR : UnaryRRF<"cfxbr", 0xB39A, GR32, FP128>;
149 def CGEBR : UnaryRRF<"cgebr", 0xB3A8, GR64, FP32>;
150 def CGDBR : UnaryRRF<"cgdbr", 0xB3A9, GR64, FP64>;
151 def CGXBR : UnaryRRF<"cgxbr", 0xB3AA, GR64, FP128>;
154 // fp_to_sint always rounds towards zero, which is modifier value 5.
155 def : Pat<(i32 (fp_to_sint FP32:$src)), (CFEBR 5, FP32:$src)>;
156 def : Pat<(i32 (fp_to_sint FP64:$src)), (CFDBR 5, FP64:$src)>;
157 def : Pat<(i32 (fp_to_sint FP128:$src)), (CFXBR 5, FP128:$src)>;
159 def : Pat<(i64 (fp_to_sint FP32:$src)), (CGEBR 5, FP32:$src)>;
160 def : Pat<(i64 (fp_to_sint FP64:$src)), (CGDBR 5, FP64:$src)>;
161 def : Pat<(i64 (fp_to_sint FP128:$src)), (CGXBR 5, FP128:$src)>;
163 //===----------------------------------------------------------------------===//
165 //===----------------------------------------------------------------------===//
167 // Negation (Load Complement).
169 def LCEBR : UnaryRRE<"lcebr", 0xB303, fneg, FP32, FP32>;
170 def LCDBR : UnaryRRE<"lcdbr", 0xB313, fneg, FP64, FP64>;
171 def LCXBR : UnaryRRE<"lcxbr", 0xB343, fneg, FP128, FP128>;
174 // Absolute value (Load Positive).
176 def LPEBR : UnaryRRE<"lpebr", 0xB300, fabs, FP32, FP32>;
177 def LPDBR : UnaryRRE<"lpdbr", 0xB310, fabs, FP64, FP64>;
178 def LPXBR : UnaryRRE<"lpxbr", 0xB340, fabs, FP128, FP128>;
181 // Negative absolute value (Load Negative).
183 def LNEBR : UnaryRRE<"lnebr", 0xB301, fnabs, FP32, FP32>;
184 def LNDBR : UnaryRRE<"lndbr", 0xB311, fnabs, FP64, FP64>;
185 def LNXBR : UnaryRRE<"lnxbr", 0xB341, fnabs, FP128, FP128>;
189 def SQEBR : UnaryRRE<"sqebr", 0xB314, fsqrt, FP32, FP32>;
190 def SQDBR : UnaryRRE<"sqdbr", 0xB315, fsqrt, FP64, FP64>;
191 def SQXBR : UnaryRRE<"sqxbr", 0xB316, fsqrt, FP128, FP128>;
193 def SQEB : UnaryRXE<"sqeb", 0xED14, loadu<fsqrt>, FP32>;
194 def SQDB : UnaryRXE<"sqdb", 0xED15, loadu<fsqrt>, FP64>;
196 // Round to an integer, with the second operand (modifier M3) specifying
197 // the rounding mode.
199 // These forms always check for inexact conditions. z196 added versions
200 // that allow this to suppressed (as for fnearbyint), but we don't yet
201 // support -march=z196.
203 def FIEBR : UnaryRRF<"fiebr", 0xB357, FP32, FP32>;
204 def FIDBR : UnaryRRF<"fidbr", 0xB35F, FP64, FP64>;
205 def FIXBR : UnaryRRF<"fixbr", 0xB347, FP128, FP128>;
208 // frint rounds according to the current mode (modifier 0) and detects
209 // inexact conditions.
210 def : Pat<(frint FP32:$src), (FIEBR 0, FP32:$src)>;
211 def : Pat<(frint FP64:$src), (FIDBR 0, FP64:$src)>;
212 def : Pat<(frint FP128:$src), (FIXBR 0, FP128:$src)>;
214 //===----------------------------------------------------------------------===//
216 //===----------------------------------------------------------------------===//
220 let isCommutable = 1 in {
221 def AEBR : BinaryRRE<"aebr", 0xB30A, fadd, FP32, FP32>;
222 def ADBR : BinaryRRE<"adbr", 0xB31A, fadd, FP64, FP64>;
223 def AXBR : BinaryRRE<"axbr", 0xB34A, fadd, FP128, FP128>;
225 def AEB : BinaryRXE<"aeb", 0xED0A, fadd, FP32, load>;
226 def ADB : BinaryRXE<"adb", 0xED1A, fadd, FP64, load>;
231 def SEBR : BinaryRRE<"sebr", 0xB30B, fsub, FP32, FP32>;
232 def SDBR : BinaryRRE<"sdbr", 0xB31B, fsub, FP64, FP64>;
233 def SXBR : BinaryRRE<"sxbr", 0xB34B, fsub, FP128, FP128>;
235 def SEB : BinaryRXE<"seb", 0xED0B, fsub, FP32, load>;
236 def SDB : BinaryRXE<"sdb", 0xED1B, fsub, FP64, load>;
240 let isCommutable = 1 in {
241 def MEEBR : BinaryRRE<"meebr", 0xB317, fmul, FP32, FP32>;
242 def MDBR : BinaryRRE<"mdbr", 0xB31C, fmul, FP64, FP64>;
243 def MXBR : BinaryRRE<"mxbr", 0xB34C, fmul, FP128, FP128>;
245 def MEEB : BinaryRXE<"meeb", 0xED17, fmul, FP32, load>;
246 def MDB : BinaryRXE<"mdb", 0xED1C, fmul, FP64, load>;
248 // f64 multiplication of two FP32 registers.
249 def MDEBR : BinaryRRE<"mdebr", 0xB30C, null_frag, FP64, FP32>;
250 def : Pat<(fmul (f64 (fextend FP32:$src1)), (f64 (fextend FP32:$src2))),
251 (MDEBR (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
252 FP32:$src1, subreg_32bit), FP32:$src2)>;
254 // f64 multiplication of an FP32 register and an f32 memory.
255 def MDEB : BinaryRXE<"mdeb", 0xED0C, null_frag, FP64, load>;
256 def : Pat<(fmul (f64 (fextend FP32:$src1)),
257 (f64 (extloadf32 bdxaddr12only:$addr))),
258 (MDEB (INSERT_SUBREG (f64 (IMPLICIT_DEF)), FP32:$src1, subreg_32bit),
259 bdxaddr12only:$addr)>;
261 // f128 multiplication of two FP64 registers.
262 def MXDBR : BinaryRRE<"mxdbr", 0xB307, null_frag, FP128, FP64>;
263 def : Pat<(fmul (f128 (fextend FP64:$src1)), (f128 (fextend FP64:$src2))),
264 (MXDBR (INSERT_SUBREG (f128 (IMPLICIT_DEF)),
265 FP64:$src1, subreg_high), FP64:$src2)>;
267 // f128 multiplication of an FP64 register and an f64 memory.
268 def MXDB : BinaryRXE<"mxdb", 0xED07, null_frag, FP128, load>;
269 def : Pat<(fmul (f128 (fextend FP64:$src1)),
270 (f128 (extloadf64 bdxaddr12only:$addr))),
271 (MXDB (INSERT_SUBREG (f128 (IMPLICIT_DEF)), FP64:$src1, subreg_high),
272 bdxaddr12only:$addr)>;
274 // Fused multiply-add.
275 def MAEBR : TernaryRRD<"maebr", 0xB30E, z_fma, FP32>;
276 def MADBR : TernaryRRD<"madbr", 0xB31E, z_fma, FP64>;
278 def MAEB : TernaryRXF<"maeb", 0xED0E, z_fma, FP32, load>;
279 def MADB : TernaryRXF<"madb", 0xED1E, z_fma, FP64, load>;
281 // Fused multiply-subtract.
282 def MSEBR : TernaryRRD<"msebr", 0xB30F, z_fms, FP32>;
283 def MSDBR : TernaryRRD<"msdbr", 0xB31F, z_fms, FP64>;
285 def MSEB : TernaryRXF<"mseb", 0xED0F, z_fms, FP32, load>;
286 def MSDB : TernaryRXF<"msdb", 0xED1F, z_fms, FP64, load>;
289 def DEBR : BinaryRRE<"debr", 0xB30D, fdiv, FP32, FP32>;
290 def DDBR : BinaryRRE<"ddbr", 0xB31D, fdiv, FP64, FP64>;
291 def DXBR : BinaryRRE<"dxbr", 0xB34D, fdiv, FP128, FP128>;
293 def DEB : BinaryRXE<"deb", 0xED0D, fdiv, FP32, load>;
294 def DDB : BinaryRXE<"ddb", 0xED1D, fdiv, FP64, load>;
296 //===----------------------------------------------------------------------===//
298 //===----------------------------------------------------------------------===//
301 def CEBR : CompareRRE<"cebr", 0xB309, z_cmp, FP32, FP32>;
302 def CDBR : CompareRRE<"cdbr", 0xB319, z_cmp, FP64, FP64>;
303 def CXBR : CompareRRE<"cxbr", 0xB349, z_cmp, FP128, FP128>;
305 def CEB : CompareRXE<"ceb", 0xED09, z_cmp, FP32, load>;
306 def CDB : CompareRXE<"cdb", 0xED19, z_cmp, FP64, load>;
309 //===----------------------------------------------------------------------===//
311 //===----------------------------------------------------------------------===//
313 def : Pat<(f32 fpimmneg0), (LCEBR (LZER))>;
314 def : Pat<(f64 fpimmneg0), (LCDBR (LZDR))>;
315 def : Pat<(f128 fpimmneg0), (LCXBR (LZXR))>;