1 //==- SystemZInstrFP.td - Floating-point SystemZ instructions --*- tblgen-*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Select instructions
12 //===----------------------------------------------------------------------===//
14 // C's ?: operator for floating-point operands.
15 def SelectF32 : SelectWrapper<FP32>;
16 def SelectF64 : SelectWrapper<FP64>;
17 def SelectF128 : SelectWrapper<FP128>;
19 defm CondStoreF32 : CondStores<FP32, nonvolatile_store,
20 nonvolatile_load, bdxaddr20only>;
21 defm CondStoreF64 : CondStores<FP64, nonvolatile_store,
22 nonvolatile_load, bdxaddr20only>;
24 //===----------------------------------------------------------------------===//
26 //===----------------------------------------------------------------------===//
29 let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
30 def LZER : InherentRRE<"lzer", 0xB374, FP32, (fpimm0)>;
31 def LZDR : InherentRRE<"lzdr", 0xB375, FP64, (fpimm0)>;
32 def LZXR : InherentRRE<"lzxr", 0xB376, FP128, (fpimm0)>;
35 // Moves between two floating-point registers.
36 let neverHasSideEffects = 1 in {
37 def LER : UnaryRR <"le", 0x38, null_frag, FP32, FP32>;
38 def LDR : UnaryRR <"ld", 0x28, null_frag, FP64, FP64>;
39 def LXR : UnaryRRE<"lx", 0xB365, null_frag, FP128, FP128>;
42 // Moves between two floating-point registers that also set the condition
44 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
45 defm LTEBR : LoadAndTestRRE<"lteb", 0xB302, FP32>;
46 defm LTDBR : LoadAndTestRRE<"ltdb", 0xB312, FP64>;
47 defm LTXBR : LoadAndTestRRE<"ltxb", 0xB342, FP128>;
49 defm : CompareZeroFP<LTEBRCompare, FP32>;
50 defm : CompareZeroFP<LTDBRCompare, FP64>;
51 defm : CompareZeroFP<LTXBRCompare, FP128>;
53 // Moves between 64-bit integer and floating-point registers.
54 def LGDR : UnaryRRE<"lgd", 0xB3CD, bitconvert, GR64, FP64>;
55 def LDGR : UnaryRRE<"ldg", 0xB3C1, bitconvert, FP64, GR64>;
57 // fcopysign with an FP32 result.
58 let isCodeGenOnly = 1 in {
59 def CPSDRss : BinaryRRF<"cpsd", 0xB372, fcopysign, FP32, FP32>;
60 def CPSDRsd : BinaryRRF<"cpsd", 0xB372, fcopysign, FP32, FP64>;
63 // The sign of an FP128 is in the high register.
64 def : Pat<(fcopysign FP32:$src1, FP128:$src2),
65 (CPSDRsd FP32:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>;
67 // fcopysign with an FP64 result.
68 let isCodeGenOnly = 1 in
69 def CPSDRds : BinaryRRF<"cpsd", 0xB372, fcopysign, FP64, FP32>;
70 def CPSDRdd : BinaryRRF<"cpsd", 0xB372, fcopysign, FP64, FP64>;
72 // The sign of an FP128 is in the high register.
73 def : Pat<(fcopysign FP64:$src1, FP128:$src2),
74 (CPSDRdd FP64:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>;
76 // fcopysign with an FP128 result. Use "upper" as the high half and leave
77 // the low half as-is.
78 class CopySign128<RegisterOperand cls, dag upper>
79 : Pat<(fcopysign FP128:$src1, cls:$src2),
80 (INSERT_SUBREG FP128:$src1, upper, subreg_h64)>;
82 def : CopySign128<FP32, (CPSDRds (EXTRACT_SUBREG FP128:$src1, subreg_h64),
84 def : CopySign128<FP64, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_h64),
86 def : CopySign128<FP128, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_h64),
87 (EXTRACT_SUBREG FP128:$src2, subreg_h64))>;
89 defm LoadStoreF32 : MVCLoadStore<load, f32, MVCSequence, 4>;
90 defm LoadStoreF64 : MVCLoadStore<load, f64, MVCSequence, 8>;
91 defm LoadStoreF128 : MVCLoadStore<load, f128, MVCSequence, 16>;
93 //===----------------------------------------------------------------------===//
95 //===----------------------------------------------------------------------===//
97 let canFoldAsLoad = 1, SimpleBDXLoad = 1 in {
98 defm LE : UnaryRXPair<"le", 0x78, 0xED64, load, FP32, 4>;
99 defm LD : UnaryRXPair<"ld", 0x68, 0xED65, load, FP64, 8>;
101 // These instructions are split after register allocation, so we don't
102 // want a custom inserter.
103 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
104 def LX : Pseudo<(outs FP128:$dst), (ins bdxaddr20only128:$src),
105 [(set FP128:$dst, (load bdxaddr20only128:$src))]>;
109 //===----------------------------------------------------------------------===//
110 // Store instructions
111 //===----------------------------------------------------------------------===//
113 let SimpleBDXStore = 1 in {
114 defm STE : StoreRXPair<"ste", 0x70, 0xED66, store, FP32, 4>;
115 defm STD : StoreRXPair<"std", 0x60, 0xED67, store, FP64, 8>;
117 // These instructions are split after register allocation, so we don't
118 // want a custom inserter.
119 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
120 def STX : Pseudo<(outs), (ins FP128:$src, bdxaddr20only128:$dst),
121 [(store FP128:$src, bdxaddr20only128:$dst)]>;
125 //===----------------------------------------------------------------------===//
126 // Conversion instructions
127 //===----------------------------------------------------------------------===//
129 // Convert floating-point values to narrower representations, rounding
130 // according to the current mode. The destination of LEXBR and LDXBR
131 // is a 128-bit value, but only the first register of the pair is used.
132 def LEDBR : UnaryRRE<"ledb", 0xB344, fround, FP32, FP64>;
133 def LEXBR : UnaryRRE<"lexb", 0xB346, null_frag, FP128, FP128>;
134 def LDXBR : UnaryRRE<"ldxb", 0xB345, null_frag, FP128, FP128>;
136 def LEDBRA : UnaryRRF4<"ledbra", 0xB344, FP32, FP64>,
137 Requires<[FeatureFPExtension]>;
138 def LEXBRA : UnaryRRF4<"lexbra", 0xB346, FP128, FP128>,
139 Requires<[FeatureFPExtension]>;
140 def LDXBRA : UnaryRRF4<"ldxbra", 0xB345, FP128, FP128>,
141 Requires<[FeatureFPExtension]>;
143 def : Pat<(f32 (fround FP128:$src)),
144 (EXTRACT_SUBREG (LEXBR FP128:$src), subreg_hh32)>;
145 def : Pat<(f64 (fround FP128:$src)),
146 (EXTRACT_SUBREG (LDXBR FP128:$src), subreg_h64)>;
148 // Extend register floating-point values to wider representations.
149 def LDEBR : UnaryRRE<"ldeb", 0xB304, fextend, FP64, FP32>;
150 def LXEBR : UnaryRRE<"lxeb", 0xB306, fextend, FP128, FP32>;
151 def LXDBR : UnaryRRE<"lxdb", 0xB305, fextend, FP128, FP64>;
153 // Extend memory floating-point values to wider representations.
154 def LDEB : UnaryRXE<"ldeb", 0xED04, extloadf32, FP64, 4>;
155 def LXEB : UnaryRXE<"lxeb", 0xED06, extloadf32, FP128, 4>;
156 def LXDB : UnaryRXE<"lxdb", 0xED05, extloadf64, FP128, 8>;
158 // Convert a signed integer register value to a floating-point one.
159 def CEFBR : UnaryRRE<"cefb", 0xB394, sint_to_fp, FP32, GR32>;
160 def CDFBR : UnaryRRE<"cdfb", 0xB395, sint_to_fp, FP64, GR32>;
161 def CXFBR : UnaryRRE<"cxfb", 0xB396, sint_to_fp, FP128, GR32>;
163 def CEGBR : UnaryRRE<"cegb", 0xB3A4, sint_to_fp, FP32, GR64>;
164 def CDGBR : UnaryRRE<"cdgb", 0xB3A5, sint_to_fp, FP64, GR64>;
165 def CXGBR : UnaryRRE<"cxgb", 0xB3A6, sint_to_fp, FP128, GR64>;
167 // Convert am unsigned integer register value to a floating-point one.
168 let Predicates = [FeatureFPExtension] in {
169 def CELFBR : UnaryRRF4<"celfbr", 0xB390, FP32, GR32>;
170 def CDLFBR : UnaryRRF4<"cdlfbr", 0xB391, FP64, GR32>;
171 def CXLFBR : UnaryRRF4<"cxlfbr", 0xB392, FP128, GR32>;
173 def CELGBR : UnaryRRF4<"celgbr", 0xB3A0, FP32, GR64>;
174 def CDLGBR : UnaryRRF4<"cdlgbr", 0xB3A1, FP64, GR64>;
175 def CXLGBR : UnaryRRF4<"cxlgbr", 0xB3A2, FP128, GR64>;
177 def : Pat<(f32 (uint_to_fp GR32:$src)), (CELFBR 0, GR32:$src, 0)>;
178 def : Pat<(f64 (uint_to_fp GR32:$src)), (CDLFBR 0, GR32:$src, 0)>;
179 def : Pat<(f128 (uint_to_fp GR32:$src)), (CXLFBR 0, GR32:$src, 0)>;
181 def : Pat<(f32 (uint_to_fp GR64:$src)), (CELGBR 0, GR64:$src, 0)>;
182 def : Pat<(f64 (uint_to_fp GR64:$src)), (CDLGBR 0, GR64:$src, 0)>;
183 def : Pat<(f128 (uint_to_fp GR64:$src)), (CXLGBR 0, GR64:$src, 0)>;
186 // Convert a floating-point register value to a signed integer value,
187 // with the second operand (modifier M3) specifying the rounding mode.
189 def CFEBR : UnaryRRF<"cfeb", 0xB398, GR32, FP32>;
190 def CFDBR : UnaryRRF<"cfdb", 0xB399, GR32, FP64>;
191 def CFXBR : UnaryRRF<"cfxb", 0xB39A, GR32, FP128>;
193 def CGEBR : UnaryRRF<"cgeb", 0xB3A8, GR64, FP32>;
194 def CGDBR : UnaryRRF<"cgdb", 0xB3A9, GR64, FP64>;
195 def CGXBR : UnaryRRF<"cgxb", 0xB3AA, GR64, FP128>;
198 // fp_to_sint always rounds towards zero, which is modifier value 5.
199 def : Pat<(i32 (fp_to_sint FP32:$src)), (CFEBR 5, FP32:$src)>;
200 def : Pat<(i32 (fp_to_sint FP64:$src)), (CFDBR 5, FP64:$src)>;
201 def : Pat<(i32 (fp_to_sint FP128:$src)), (CFXBR 5, FP128:$src)>;
203 def : Pat<(i64 (fp_to_sint FP32:$src)), (CGEBR 5, FP32:$src)>;
204 def : Pat<(i64 (fp_to_sint FP64:$src)), (CGDBR 5, FP64:$src)>;
205 def : Pat<(i64 (fp_to_sint FP128:$src)), (CGXBR 5, FP128:$src)>;
207 // Convert a floating-point register value to an unsigned integer value.
208 let Predicates = [FeatureFPExtension] in {
210 def CLFEBR : UnaryRRF4<"clfebr", 0xB39C, GR32, FP32>;
211 def CLFDBR : UnaryRRF4<"clfdbr", 0xB39D, GR32, FP64>;
212 def CLFXBR : UnaryRRF4<"clfxbr", 0xB39E, GR32, FP128>;
214 def CLGEBR : UnaryRRF4<"clgebr", 0xB3AC, GR64, FP32>;
215 def CLGDBR : UnaryRRF4<"clgdbr", 0xB3AD, GR64, FP64>;
216 def CLGXBR : UnaryRRF4<"clgxbr", 0xB3AE, GR64, FP128>;
219 def : Pat<(i32 (fp_to_uint FP32:$src)), (CLFEBR 5, FP32:$src, 0)>;
220 def : Pat<(i32 (fp_to_uint FP64:$src)), (CLFDBR 5, FP64:$src, 0)>;
221 def : Pat<(i32 (fp_to_uint FP128:$src)), (CLFXBR 5, FP128:$src, 0)>;
223 def : Pat<(i64 (fp_to_uint FP32:$src)), (CLGEBR 5, FP32:$src, 0)>;
224 def : Pat<(i64 (fp_to_uint FP64:$src)), (CLGDBR 5, FP64:$src, 0)>;
225 def : Pat<(i64 (fp_to_uint FP128:$src)), (CLGXBR 5, FP128:$src, 0)>;
229 //===----------------------------------------------------------------------===//
231 //===----------------------------------------------------------------------===//
233 // Negation (Load Complement).
234 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
235 def LCEBR : UnaryRRE<"lceb", 0xB303, fneg, FP32, FP32>;
236 def LCDBR : UnaryRRE<"lcdb", 0xB313, fneg, FP64, FP64>;
237 def LCXBR : UnaryRRE<"lcxb", 0xB343, fneg, FP128, FP128>;
240 // Absolute value (Load Positive).
241 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
242 def LPEBR : UnaryRRE<"lpeb", 0xB300, fabs, FP32, FP32>;
243 def LPDBR : UnaryRRE<"lpdb", 0xB310, fabs, FP64, FP64>;
244 def LPXBR : UnaryRRE<"lpxb", 0xB340, fabs, FP128, FP128>;
247 // Negative absolute value (Load Negative).
248 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
249 def LNEBR : UnaryRRE<"lneb", 0xB301, fnabs, FP32, FP32>;
250 def LNDBR : UnaryRRE<"lndb", 0xB311, fnabs, FP64, FP64>;
251 def LNXBR : UnaryRRE<"lnxb", 0xB341, fnabs, FP128, FP128>;
255 def SQEBR : UnaryRRE<"sqeb", 0xB314, fsqrt, FP32, FP32>;
256 def SQDBR : UnaryRRE<"sqdb", 0xB315, fsqrt, FP64, FP64>;
257 def SQXBR : UnaryRRE<"sqxb", 0xB316, fsqrt, FP128, FP128>;
259 def SQEB : UnaryRXE<"sqeb", 0xED14, loadu<fsqrt>, FP32, 4>;
260 def SQDB : UnaryRXE<"sqdb", 0xED15, loadu<fsqrt>, FP64, 8>;
262 // Round to an integer, with the second operand (modifier M3) specifying
263 // the rounding mode. These forms always check for inexact conditions.
264 def FIEBR : UnaryRRF<"fieb", 0xB357, FP32, FP32>;
265 def FIDBR : UnaryRRF<"fidb", 0xB35F, FP64, FP64>;
266 def FIXBR : UnaryRRF<"fixb", 0xB347, FP128, FP128>;
268 // frint rounds according to the current mode (modifier 0) and detects
269 // inexact conditions.
270 def : Pat<(frint FP32:$src), (FIEBR 0, FP32:$src)>;
271 def : Pat<(frint FP64:$src), (FIDBR 0, FP64:$src)>;
272 def : Pat<(frint FP128:$src), (FIXBR 0, FP128:$src)>;
274 let Predicates = [FeatureFPExtension] in {
275 // Extended forms of the FIxBR instructions. M4 can be set to 4
276 // to suppress detection of inexact conditions.
277 def FIEBRA : UnaryRRF4<"fiebra", 0xB357, FP32, FP32>;
278 def FIDBRA : UnaryRRF4<"fidbra", 0xB35F, FP64, FP64>;
279 def FIXBRA : UnaryRRF4<"fixbra", 0xB347, FP128, FP128>;
281 // fnearbyint is like frint but does not detect inexact conditions.
282 def : Pat<(fnearbyint FP32:$src), (FIEBRA 0, FP32:$src, 4)>;
283 def : Pat<(fnearbyint FP64:$src), (FIDBRA 0, FP64:$src, 4)>;
284 def : Pat<(fnearbyint FP128:$src), (FIXBRA 0, FP128:$src, 4)>;
286 // floor is no longer allowed to raise an inexact condition,
287 // so restrict it to the cases where the condition can be suppressed.
288 // Mode 7 is round towards -inf.
289 def : Pat<(ffloor FP32:$src), (FIEBRA 7, FP32:$src, 4)>;
290 def : Pat<(ffloor FP64:$src), (FIDBRA 7, FP64:$src, 4)>;
291 def : Pat<(ffloor FP128:$src), (FIXBRA 7, FP128:$src, 4)>;
293 // Same idea for ceil, where mode 6 is round towards +inf.
294 def : Pat<(fceil FP32:$src), (FIEBRA 6, FP32:$src, 4)>;
295 def : Pat<(fceil FP64:$src), (FIDBRA 6, FP64:$src, 4)>;
296 def : Pat<(fceil FP128:$src), (FIXBRA 6, FP128:$src, 4)>;
298 // Same idea for trunc, where mode 5 is round towards zero.
299 def : Pat<(ftrunc FP32:$src), (FIEBRA 5, FP32:$src, 4)>;
300 def : Pat<(ftrunc FP64:$src), (FIDBRA 5, FP64:$src, 4)>;
301 def : Pat<(ftrunc FP128:$src), (FIXBRA 5, FP128:$src, 4)>;
303 // Same idea for round, where mode 1 is round towards nearest with
304 // ties away from zero.
305 def : Pat<(frnd FP32:$src), (FIEBRA 1, FP32:$src, 4)>;
306 def : Pat<(frnd FP64:$src), (FIDBRA 1, FP64:$src, 4)>;
307 def : Pat<(frnd FP128:$src), (FIXBRA 1, FP128:$src, 4)>;
310 //===----------------------------------------------------------------------===//
312 //===----------------------------------------------------------------------===//
315 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
316 let isCommutable = 1 in {
317 def AEBR : BinaryRRE<"aeb", 0xB30A, fadd, FP32, FP32>;
318 def ADBR : BinaryRRE<"adb", 0xB31A, fadd, FP64, FP64>;
319 def AXBR : BinaryRRE<"axb", 0xB34A, fadd, FP128, FP128>;
321 def AEB : BinaryRXE<"aeb", 0xED0A, fadd, FP32, load, 4>;
322 def ADB : BinaryRXE<"adb", 0xED1A, fadd, FP64, load, 8>;
326 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
327 def SEBR : BinaryRRE<"seb", 0xB30B, fsub, FP32, FP32>;
328 def SDBR : BinaryRRE<"sdb", 0xB31B, fsub, FP64, FP64>;
329 def SXBR : BinaryRRE<"sxb", 0xB34B, fsub, FP128, FP128>;
331 def SEB : BinaryRXE<"seb", 0xED0B, fsub, FP32, load, 4>;
332 def SDB : BinaryRXE<"sdb", 0xED1B, fsub, FP64, load, 8>;
336 let isCommutable = 1 in {
337 def MEEBR : BinaryRRE<"meeb", 0xB317, fmul, FP32, FP32>;
338 def MDBR : BinaryRRE<"mdb", 0xB31C, fmul, FP64, FP64>;
339 def MXBR : BinaryRRE<"mxb", 0xB34C, fmul, FP128, FP128>;
341 def MEEB : BinaryRXE<"meeb", 0xED17, fmul, FP32, load, 4>;
342 def MDB : BinaryRXE<"mdb", 0xED1C, fmul, FP64, load, 8>;
344 // f64 multiplication of two FP32 registers.
345 def MDEBR : BinaryRRE<"mdeb", 0xB30C, null_frag, FP64, FP32>;
346 def : Pat<(fmul (f64 (fextend FP32:$src1)), (f64 (fextend FP32:$src2))),
347 (MDEBR (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
348 FP32:$src1, subreg_h32), FP32:$src2)>;
350 // f64 multiplication of an FP32 register and an f32 memory.
351 def MDEB : BinaryRXE<"mdeb", 0xED0C, null_frag, FP64, load, 4>;
352 def : Pat<(fmul (f64 (fextend FP32:$src1)),
353 (f64 (extloadf32 bdxaddr12only:$addr))),
354 (MDEB (INSERT_SUBREG (f64 (IMPLICIT_DEF)), FP32:$src1, subreg_h32),
355 bdxaddr12only:$addr)>;
357 // f128 multiplication of two FP64 registers.
358 def MXDBR : BinaryRRE<"mxdb", 0xB307, null_frag, FP128, FP64>;
359 def : Pat<(fmul (f128 (fextend FP64:$src1)), (f128 (fextend FP64:$src2))),
360 (MXDBR (INSERT_SUBREG (f128 (IMPLICIT_DEF)),
361 FP64:$src1, subreg_h64), FP64:$src2)>;
363 // f128 multiplication of an FP64 register and an f64 memory.
364 def MXDB : BinaryRXE<"mxdb", 0xED07, null_frag, FP128, load, 8>;
365 def : Pat<(fmul (f128 (fextend FP64:$src1)),
366 (f128 (extloadf64 bdxaddr12only:$addr))),
367 (MXDB (INSERT_SUBREG (f128 (IMPLICIT_DEF)), FP64:$src1, subreg_h64),
368 bdxaddr12only:$addr)>;
370 // Fused multiply-add.
371 def MAEBR : TernaryRRD<"maeb", 0xB30E, z_fma, FP32>;
372 def MADBR : TernaryRRD<"madb", 0xB31E, z_fma, FP64>;
374 def MAEB : TernaryRXF<"maeb", 0xED0E, z_fma, FP32, load, 4>;
375 def MADB : TernaryRXF<"madb", 0xED1E, z_fma, FP64, load, 8>;
377 // Fused multiply-subtract.
378 def MSEBR : TernaryRRD<"mseb", 0xB30F, z_fms, FP32>;
379 def MSDBR : TernaryRRD<"msdb", 0xB31F, z_fms, FP64>;
381 def MSEB : TernaryRXF<"mseb", 0xED0F, z_fms, FP32, load, 4>;
382 def MSDB : TernaryRXF<"msdb", 0xED1F, z_fms, FP64, load, 8>;
385 def DEBR : BinaryRRE<"deb", 0xB30D, fdiv, FP32, FP32>;
386 def DDBR : BinaryRRE<"ddb", 0xB31D, fdiv, FP64, FP64>;
387 def DXBR : BinaryRRE<"dxb", 0xB34D, fdiv, FP128, FP128>;
389 def DEB : BinaryRXE<"deb", 0xED0D, fdiv, FP32, load, 4>;
390 def DDB : BinaryRXE<"ddb", 0xED1D, fdiv, FP64, load, 8>;
392 //===----------------------------------------------------------------------===//
394 //===----------------------------------------------------------------------===//
396 let Defs = [CC], CCValues = 0xF in {
397 def CEBR : CompareRRE<"ceb", 0xB309, z_fcmp, FP32, FP32>;
398 def CDBR : CompareRRE<"cdb", 0xB319, z_fcmp, FP64, FP64>;
399 def CXBR : CompareRRE<"cxb", 0xB349, z_fcmp, FP128, FP128>;
401 def CEB : CompareRXE<"ceb", 0xED09, z_fcmp, FP32, load, 4>;
402 def CDB : CompareRXE<"cdb", 0xED19, z_fcmp, FP64, load, 8>;
405 //===----------------------------------------------------------------------===//
407 //===----------------------------------------------------------------------===//
409 def : Pat<(f32 fpimmneg0), (LCEBR (LZER))>;
410 def : Pat<(f64 fpimmneg0), (LCDBR (LZDR))>;
411 def : Pat<(f128 fpimmneg0), (LCXBR (LZXR))>;