1 //===- SystemZInstrFP.td - SystemZ FP Instruction defs --------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the SystemZ (binary) floating point instructions in
13 //===----------------------------------------------------------------------===//
15 // FIXME: multiclassify!
17 let usesCustomDAGSchedInserter = 1 in {
18 def SelectF32 : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, i8imm:$cc),
21 (SystemZselect FP32:$src1, FP32:$src2, imm:$cc))]>;
22 def SelectF64 : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, i8imm:$cc),
25 (SystemZselect FP64:$src1, FP64:$src2, imm:$cc))]>;
28 //===----------------------------------------------------------------------===//
31 let neverHasSideEffects = 1 in {
32 def FMOV32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
35 def FMOV64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
40 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
41 def FMOV32rm : Pseudo<(outs FP32:$dst), (ins rriaddr12:$src),
43 [(set FP32:$dst, (load rriaddr12:$src))]>;
44 def FMOV32rmy : Pseudo<(outs FP32:$dst), (ins rriaddr:$src),
46 [(set FP32:$dst, (load rriaddr:$src))]>;
47 def FMOV64rm : Pseudo<(outs FP64:$dst), (ins rriaddr12:$src),
49 [(set FP64:$dst, (load rriaddr12:$src))]>;
50 def FMOV64rmy : Pseudo<(outs FP64:$dst), (ins rriaddr:$src),
52 [(set FP64:$dst, (load rriaddr:$src))]>;
55 def FMOV32mr : Pseudo<(outs), (ins rriaddr12:$dst, FP32:$src),
57 [(store FP32:$src, rriaddr12:$dst)]>;
58 def FMOV32mry : Pseudo<(outs), (ins rriaddr:$dst, FP32:$src),
60 [(store FP32:$src, rriaddr:$dst)]>;
61 def FMOV64mr : Pseudo<(outs), (ins rriaddr12:$dst, FP64:$src),
63 [(store FP64:$src, rriaddr12:$dst)]>;
64 def FMOV64mry : Pseudo<(outs), (ins rriaddr:$dst, FP64:$src),
66 [(store FP64:$src, rriaddr:$dst)]>;
68 //===----------------------------------------------------------------------===//
69 // Arithmetic Instructions
73 def FNEG32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
74 "lcebr\t{$dst, $src}",
75 [(set FP32:$dst, (fneg FP32:$src)),
77 def FNEG64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
78 "lcdbr\t{$dst, $src}",
79 [(set FP64:$dst, (fneg FP64:$src)),
83 let isTwoAddress = 1 in {
85 // FIXME: Add peephole for fneg(fabs) => load negative
87 def FABS32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
89 [(set FP32:$dst, (fabs FP32:$src)),
91 def FABS64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
93 [(set FP64:$dst, (fabs FP64:$src)),
96 let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y
97 def FADD32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
98 "aebr\t{$dst, $src2}",
99 [(set FP32:$dst, (fadd FP32:$src1, FP32:$src2)),
101 def FADD64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
102 "adbr\t{$dst, $src2}",
103 [(set FP64:$dst, (fadd FP64:$src1, FP64:$src2)),
107 def FADD32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2),
108 "aeb\t{$dst, $src2}",
109 [(set FP32:$dst, (fadd FP32:$src1, (load rriaddr:$src2))),
111 def FADD64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2),
112 "adb\t{$dst, $src2}",
113 [(set FP64:$dst, (fadd FP64:$src1, (load rriaddr:$src2))),
116 def FSUB32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
117 "sebr\t{$dst, $src2}",
118 [(set FP32:$dst, (fsub FP32:$src1, FP32:$src2)),
120 def FSUB64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
121 "sdbr\t{$dst, $src2}",
122 [(set FP64:$dst, (fsub FP64:$src1, FP64:$src2)),
125 def FSUB32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2),
126 "seb\t{$dst, $src2}",
127 [(set FP32:$dst, (fsub FP32:$src1, (load rriaddr:$src2))),
129 def FSUB64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2),
130 "sdb\t{$dst, $src2}",
131 [(set FP64:$dst, (fsub FP64:$src1, (load rriaddr:$src2))),
135 let isCommutable = 1 in { // X = MUL Y, Z == X = MUL Z, Y
136 def FMUL32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
137 "meebr\t{$dst, $src2}",
138 [(set FP32:$dst, (fmul FP32:$src1, FP32:$src2))]>;
139 def FMUL64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
140 "mdbr\t{$dst, $src2}",
141 [(set FP64:$dst, (fmul FP64:$src1, FP64:$src2))]>;
144 def FMUL32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2),
145 "meeb\t{$dst, $src2}",
146 [(set FP32:$dst, (fmul FP32:$src1, (load rriaddr:$src2)))]>;
147 def FMUL64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2),
148 "mdb\t{$dst, $src2}",
149 [(set FP64:$dst, (fmul FP64:$src1, (load rriaddr:$src2)))]>;
151 def FMADD32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, FP32:$src3),
152 "maebr\t{$dst, $src3, $src2}",
153 [(set FP32:$dst, (fadd (fmul FP32:$src2, FP32:$src3),
155 def FMADD32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2, FP32:$src3),
156 "maeb\t{$dst, $src3, $src2}",
157 [(set FP32:$dst, (fadd (fmul (load rriaddr:$src2),
161 def FMADD64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, FP64:$src3),
162 "madbr\t{$dst, $src3, $src2}",
163 [(set FP64:$dst, (fadd (fmul FP64:$src2, FP64:$src3),
165 def FMADD64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2, FP64:$src3),
166 "madb\t{$dst, $src3, $src2}",
167 [(set FP64:$dst, (fadd (fmul (load rriaddr:$src2),
171 def FMSUB32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, FP32:$src3),
172 "msebr\t{$dst, $src3, $src2}",
173 [(set FP32:$dst, (fsub (fmul FP32:$src2, FP32:$src3),
175 def FMSUB32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2, FP32:$src3),
176 "mseb\t{$dst, $src3, $src2}",
177 [(set FP32:$dst, (fsub (fmul (load rriaddr:$src2),
181 def FMSUB64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, FP64:$src3),
182 "msdbr\t{$dst, $src3, $src2}",
183 [(set FP64:$dst, (fsub (fmul FP64:$src2, FP64:$src3),
185 def FMSUB64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2, FP64:$src3),
186 "msdb\t{$dst, $src3, $src2}",
187 [(set FP64:$dst, (fsub (fmul (load rriaddr:$src2),
191 def FDIV32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
192 "debr\t{$dst, $src2}",
193 [(set FP32:$dst, (fdiv FP32:$src1, FP32:$src2))]>;
194 def FDIV64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
195 "ddbr\t{$dst, $src2}",
196 [(set FP64:$dst, (fdiv FP64:$src1, FP64:$src2))]>;
198 def FDIV32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2),
199 "deb\t{$dst, $src2}",
200 [(set FP32:$dst, (fdiv FP32:$src1, (load rriaddr:$src2)))]>;
201 def FDIV64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2),
202 "ddb\t{$dst, $src2}",
203 [(set FP64:$dst, (fdiv FP64:$src1, (load rriaddr:$src2)))]>;
205 } // isTwoAddress = 1
207 def FROUND64r32 : Pseudo<(outs FP32:$dst), (ins FP64:$src),
208 "ledbr\t{$dst, $src}",
209 [(set FP32:$dst, (fround FP64:$src))]>;
211 def FEXT32r64 : Pseudo<(outs FP64:$dst), (ins FP32:$src),
212 "ldebr\t{$dst, $src}",
213 [(set FP64:$dst, (fextend FP32:$src))]>;
214 def FEXT32m64 : Pseudo<(outs FP64:$dst), (ins rriaddr:$src),
215 "ldeb\t{$dst, $src}",
216 [(set FP64:$dst, (fextend (load rriaddr:$src)))]>;
218 let Defs = [PSW] in {
219 def FCONVFP32 : Pseudo<(outs FP32:$dst), (ins GR32:$src),
220 "cefbr\t{$dst, $src}",
221 [(set FP32:$dst, (sint_to_fp GR32:$src)),
223 def FCONVFP32r64: Pseudo<(outs FP32:$dst), (ins GR64:$src),
224 "cegbr\t{$dst, $src}",
225 [(set FP32:$dst, (sint_to_fp GR64:$src)),
228 def FCONVFP64r32: Pseudo<(outs FP64:$dst), (ins GR32:$src),
229 "cdfbr\t{$dst, $src}",
230 [(set FP64:$dst, (sint_to_fp GR32:$src)),
232 def FCONVFP64 : Pseudo<(outs FP64:$dst), (ins GR64:$src),
233 "cdgbr\t{$dst, $src}",
234 [(set FP64:$dst, (sint_to_fp GR64:$src)),
237 def FCONVGR32 : Pseudo<(outs GR32:$dst), (ins FP32:$src),
238 "cfebr\t{$dst, $src}",
239 [(set GR32:$dst, (fp_to_sint FP32:$src)),
241 def FCONVGR32r64: Pseudo<(outs GR32:$dst), (ins FP64:$src),
242 "cgebr\t{$dst, $src}",
243 [(set GR32:$dst, (fp_to_sint FP64:$src)),
246 def FCONVGR64r32: Pseudo<(outs GR64:$dst), (ins FP32:$src),
247 "cfdbr\t{$dst, $src}",
248 [(set GR64:$dst, (fp_to_sint FP32:$src)),
250 def FCONVGR64 : Pseudo<(outs GR64:$dst), (ins FP64:$src),
251 "cgdbr\t{$dst, $src}",
252 [(set GR64:$dst, (fp_to_sint FP64:$src)),
256 //===----------------------------------------------------------------------===//
257 // Test instructions (like AND but do not produce any result)
259 // Integer comparisons
260 let Defs = [PSW] in {
261 def FCMP32rr : Pseudo<(outs), (ins FP32:$src1, FP32:$src2),
262 "cebr\t$src1, $src2",
263 [(SystemZcmp FP32:$src1, FP32:$src2), (implicit PSW)]>;
264 def FCMP64rr : Pseudo<(outs), (ins FP64:$src1, FP64:$src2),
265 "cdbr\t$src1, $src2",
266 [(SystemZcmp FP64:$src1, FP64:$src2), (implicit PSW)]>;
268 def FCMP32rm : Pseudo<(outs), (ins FP32:$src1, rriaddr:$src2),
270 [(SystemZcmp FP32:$src1, (load rriaddr:$src2)),
272 def FCMP64rm : Pseudo<(outs), (ins FP64:$src1, rriaddr:$src2),
274 [(SystemZcmp FP64:$src1, (load rriaddr:$src2)),