lib/Target/SystemZ/SystemZInstrFP.td

   1 //===- SystemZInstrFP.td - SystemZ FP Instruction defs --------*- tblgen-*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes the SystemZ (binary) floating point instructions in
  11 // TableGen format.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // FIXME: multiclassify!
  16
  17 let usesCustomDAGSchedInserter = 1 in {
  18   def SelectF32 : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, i8imm:$cc),
  19                         "# SelectF32 PSEUDO",
  20                         [(set FP32:$dst,
  21                               (SystemZselect FP32:$src1, FP32:$src2, imm:$cc))]>;
  22   def SelectF64 : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, i8imm:$cc),
  23                         "# SelectF64 PSEUDO",
  24                         [(set FP64:$dst,
  25                               (SystemZselect FP64:$src1, FP64:$src2, imm:$cc))]>;
  26 }
  27
  28 //===----------------------------------------------------------------------===//
  29 // Move Instructions
  30
  31 let neverHasSideEffects = 1 in {
  32 def FMOV32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
  33                       "ler\t{$dst, $src}",
  34                       []>;
  35 def FMOV64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
  36                       "ldr\t{$dst, $src}",
  37                       []>;
  38 }
  39
  40 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
  41 def FMOV32rm  : Pseudo<(outs FP32:$dst), (ins rriaddr12:$src),
  42                       "le\t{$dst, $src}",
  43                       [(set FP32:$dst, (load rriaddr12:$src))]>;
  44 def FMOV32rmy : Pseudo<(outs FP32:$dst), (ins rriaddr:$src),
  45                       "ley\t{$dst, $src}",
  46                       [(set FP32:$dst, (load rriaddr:$src))]>;
  47 def FMOV64rm  : Pseudo<(outs FP64:$dst), (ins rriaddr12:$src),
  48                       "ld\t{$dst, $src}",
  49                       [(set FP64:$dst, (load rriaddr12:$src))]>;
  50 def FMOV64rmy : Pseudo<(outs FP64:$dst), (ins rriaddr:$src),
  51                       "ldy\t{$dst, $src}",
  52                       [(set FP64:$dst, (load rriaddr:$src))]>;
  53 }
  54
  55 def FMOV32mr  : Pseudo<(outs), (ins rriaddr12:$dst, FP32:$src),
  56                        "ste\t{$src, $dst}",
  57                        [(store FP32:$src, rriaddr12:$dst)]>;
  58 def FMOV32mry : Pseudo<(outs), (ins rriaddr:$dst, FP32:$src),
  59                        "stey\t{$src, $dst}",
  60                        [(store FP32:$src, rriaddr:$dst)]>;
  61 def FMOV64mr  : Pseudo<(outs), (ins rriaddr12:$dst, FP64:$src),
  62                        "std\t{$src, $dst}",
  63                        [(store FP64:$src, rriaddr12:$dst)]>;
  64 def FMOV64mry : Pseudo<(outs), (ins rriaddr:$dst, FP64:$src),
  65                        "stdy\t{$src, $dst}",
  66                        [(store FP64:$src, rriaddr:$dst)]>;
  67
  68 //===----------------------------------------------------------------------===//
  69 // Arithmetic Instructions
  70
  71
  72 let isTwoAddress = 1 in {
  73 let Defs = [PSW] in {
  74
  75 def FNEG32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
  76                        "lcebr\t{$dst}",
  77                        [(set FP32:$dst, (fneg FP32:$src)),
  78                         (implicit PSW)]>;
  79 def FNEG64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
  80                        "lcdbr\t{$dst}",
  81                        [(set FP64:$dst, (fneg FP64:$src)),
  82                         (implicit PSW)]>;
  83
  84 // FIXME: Add peephole for fneg(fabs) => load negative
  85
  86 def FABS32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
  87                        "lpebr\t{$dst}",
  88                        [(set FP32:$dst, (fabs FP32:$src)),
  89                         (implicit PSW)]>;
  90 def FABS64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
  91                        "lpdbr\t{$dst}",
  92                        [(set FP64:$dst, (fabs FP64:$src)),
  93                         (implicit PSW)]>;
  94
  95 let isCommutable = 1 in { // X = ADD Y, Z  == X = ADD Z, Y
  96 def FADD32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
  97                        "aebr\t{$dst, $src2}",
  98                        [(set FP32:$dst, (fadd FP32:$src1, FP32:$src2)),
  99                         (implicit PSW)]>;
 100 def FADD64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
 101                        "adbr\t{$dst, $src2}",
 102                        [(set FP64:$dst, (fadd FP64:$src1, FP64:$src2)),
 103                         (implicit PSW)]>;
 104 }
 105
 106 def FADD32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2),
 107                        "aeb\t{$dst, $src2}",
 108                        [(set FP32:$dst, (fadd FP32:$src1, (load rriaddr:$src2))),
 109                         (implicit PSW)]>;
 110 def FADD64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2),
 111                        "adb\t{$dst, $src2}",
 112                        [(set FP64:$dst, (fadd FP64:$src1, (load rriaddr:$src2))),
 113                         (implicit PSW)]>;
 114
 115 def FSUB32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
 116                        "sebr\t{$dst, $src2}",
 117                        [(set FP32:$dst, (fsub FP32:$src1, FP32:$src2)),
 118                         (implicit PSW)]>;
 119 def FSUB64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
 120                        "sdbr\t{$dst, $src2}",
 121                        [(set FP64:$dst, (fsub FP64:$src1, FP64:$src2)),
 122                         (implicit PSW)]>;
 123
 124 def FSUB32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2),
 125                        "seb\t{$dst, $src2}",
 126                        [(set FP32:$dst, (fsub FP32:$src1, (load rriaddr:$src2))),
 127                         (implicit PSW)]>;
 128 def FSUB64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2),
 129                        "sdb\t{$dst, $src2}",
 130                        [(set FP64:$dst, (fsub FP64:$src1, (load rriaddr:$src2))),
 131                         (implicit PSW)]>;
 132 } // Defs = [PSW]
 133
 134 let isCommutable = 1 in { // X = MUL Y, Z  == X = MUL Z, Y
 135 def FMUL32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
 136                        "meebr\t{$dst, $src2}",
 137                        [(set FP32:$dst, (fmul FP32:$src1, FP32:$src2))]>;
 138 def FMUL64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
 139                        "mdbr\t{$dst, $src2}",
 140                        [(set FP64:$dst, (fmul FP64:$src1, FP64:$src2))]>;
 141 }
 142
 143 def FMUL32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2),
 144                        "meeb\t{$dst, $src2}",
 145                        [(set FP32:$dst, (fmul FP32:$src1, (load rriaddr:$src2)))]>;
 146 def FMUL64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2),
 147                        "mdb\t{$dst, $src2}",
 148                        [(set FP64:$dst, (fmul FP64:$src1, (load rriaddr:$src2)))]>;
 149
 150 def FMADD32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, FP32:$src3),
 151                        "maebr\t{$dst, $src3, $src2}",
 152                        [(set FP32:$dst, (fadd (fmul FP32:$src2, FP32:$src3),
 153                                               FP32:$src1))]>;
 154 def FMADD32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2, FP32:$src3),
 155                        "maeb\t{$dst, $src3, $src2}",
 156                        [(set FP32:$dst, (fadd (fmul (load rriaddr:$src2),
 157                                                      FP32:$src3),
 158                                               FP32:$src1))]>;
 159
 160 def FMADD64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, FP64:$src3),
 161                        "madbr\t{$dst, $src3, $src2}",
 162                        [(set FP64:$dst, (fadd (fmul FP64:$src2, FP64:$src3),
 163                                               FP64:$src1))]>;
 164 def FMADD64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2, FP64:$src3),
 165                        "madb\t{$dst, $src3, $src2}",
 166                        [(set FP64:$dst, (fadd (fmul (load rriaddr:$src2),
 167                                                      FP64:$src3),
 168                                               FP64:$src1))]>;
 169
 170 def FMSUB32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, FP32:$src3),
 171                        "msebr\t{$dst, $src3, $src2}",
 172                        [(set FP32:$dst, (fsub (fmul FP32:$src2, FP32:$src3),
 173                                               FP32:$src1))]>;
 174 def FMSUB32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2, FP32:$src3),
 175                        "mseb\t{$dst, $src3, $src2}",
 176                        [(set FP32:$dst, (fsub (fmul (load rriaddr:$src2),
 177                                                      FP32:$src3),
 178                                               FP32:$src1))]>;
 179
 180 def FMSUB64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, FP64:$src3),
 181                        "msdbr\t{$dst, $src3, $src2}",
 182                        [(set FP64:$dst, (fsub (fmul FP64:$src2, FP64:$src3),
 183                                               FP64:$src1))]>;
 184 def FMSUB64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2, FP64:$src3),
 185                        "msdb\t{$dst, $src3, $src2}",
 186                        [(set FP64:$dst, (fsub (fmul (load rriaddr:$src2),
 187                                                      FP64:$src3),
 188                                               FP64:$src1))]>;
 189
 190 def FDIV32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
 191                        "debr\t{$dst, $src2}",
 192                        [(set FP32:$dst, (fdiv FP32:$src1, FP32:$src2))]>;
 193 def FDIV64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
 194                        "ddbr\t{$dst, $src2}",
 195                        [(set FP64:$dst, (fdiv FP64:$src1, FP64:$src2))]>;
 196
 197 def FDIV32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2),
 198                        "deb\t{$dst, $src2}",
 199                        [(set FP32:$dst, (fdiv FP32:$src1, (load rriaddr:$src2)))]>;
 200 def FDIV64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2),
 201                        "ddb\t{$dst, $src2}",
 202                        [(set FP64:$dst, (fdiv FP64:$src1, (load rriaddr:$src2)))]>;
 203
 204 } // isTwoAddress = 1
 205
 206 def FROUND64r32 : Pseudo<(outs FP32:$dst), (ins FP64:$src),
 207                          "ledbr\t{$dst, $src}",
 208                          [(set FP32:$dst, (fround FP64:$src))]>;
 209
 210 def FEXT32r64   : Pseudo<(outs FP64:$dst), (ins FP32:$src),
 211                          "ldebr\t{$dst, $src}",
 212                          [(set FP64:$dst, (fextend FP32:$src))]>;
 213 def FEXT32m64   : Pseudo<(outs FP64:$dst), (ins rriaddr:$src),
 214                          "ldeb\t{$dst, $src}",
 215                          [(set FP64:$dst, (fextend (load rriaddr:$src)))]>;
 216
 217 let Defs = [PSW] in {
 218 def FCONVFP32   : Pseudo<(outs FP32:$dst), (ins GR32:$src),
 219                          "cefbr\t{$dst, $src}",
 220                          [(set FP32:$dst, (sint_to_fp GR32:$src)),
 221                           (implicit PSW)]>;
 222 def FCONVFP32r64: Pseudo<(outs FP32:$dst), (ins GR64:$src),
 223                          "cegbr\t{$dst, $src}",
 224                          [(set FP32:$dst, (sint_to_fp GR64:$src)),
 225                           (implicit PSW)]>;
 226
 227 def FCONVFP64r32: Pseudo<(outs FP64:$dst), (ins GR32:$src),
 228                          "cdfbr\t{$dst, $src}",
 229                          [(set FP64:$dst, (sint_to_fp GR32:$src)),
 230                           (implicit PSW)]>;
 231 def FCONVFP64   : Pseudo<(outs FP64:$dst), (ins GR64:$src),
 232                          "cdgbr\t{$dst, $src}",
 233                          [(set FP64:$dst, (sint_to_fp GR64:$src)),
 234                           (implicit PSW)]>;
 235
 236 def FCONVGR32   : Pseudo<(outs GR32:$dst), (ins FP32:$src),
 237                          "cfebr\t{$dst, $src}",
 238                          [(set GR32:$dst, (fp_to_sint FP32:$src)),
 239                           (implicit PSW)]>;
 240 def FCONVGR32r64: Pseudo<(outs GR32:$dst), (ins FP64:$src),
 241                          "cgebr\t{$dst, $src}",
 242                          [(set GR32:$dst, (fp_to_sint FP64:$src)),
 243                           (implicit PSW)]>;
 244
 245 def FCONVGR64r32: Pseudo<(outs GR64:$dst), (ins FP32:$src),
 246                          "cfdbr\t{$dst, $src}",
 247                          [(set GR64:$dst, (fp_to_sint FP32:$src)),
 248                           (implicit PSW)]>;
 249 def FCONVGR64   : Pseudo<(outs GR64:$dst), (ins FP64:$src),
 250                          "cgdbr\t{$dst, $src}",
 251                          [(set GR64:$dst, (fp_to_sint FP64:$src)),
 252                           (implicit PSW)]>;
 253 } // Defs = [PSW]
 254
 255 //===----------------------------------------------------------------------===//
 256 // Test instructions (like AND but do not produce any result)
 257
 258 // Integer comparisons
 259 let Defs = [PSW] in {
 260 def FCMP32rr : Pseudo<(outs), (ins FP32:$src1, FP32:$src2),
 261                       "cebr\t$src1, $src2",
 262                       [(SystemZcmp FP32:$src1, FP32:$src2), (implicit PSW)]>;
 263 def FCMP64rr : Pseudo<(outs), (ins FP64:$src1, FP64:$src2),
 264                       "cdbr\t$src1, $src2",
 265                       [(SystemZcmp FP64:$src1, FP64:$src2), (implicit PSW)]>;
 266
 267 def FCMP32rm : Pseudo<(outs), (ins FP32:$src1, rriaddr:$src2),
 268                       "ceb\t$src1, $src2",
 269                       [(SystemZcmp FP32:$src1, (load rriaddr:$src2)),
 270                        (implicit PSW)]>;
 271 def FCMP64rm : Pseudo<(outs), (ins FP64:$src1, rriaddr:$src2),
 272                       "cdb\t$src1, $src2",
 273                       [(SystemZcmp FP64:$src1, (load rriaddr:$src2)),
 274                        (implicit PSW)]>;
 275 } // Defs = [PSW]