1 //==- SystemZInstrFormats.td - SystemZ Instruction Formats --*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Basic SystemZ instruction definition
12 //===----------------------------------------------------------------------===//
14 class InstSystemZ<int size, dag outs, dag ins, string asmstr,
15 list<dag> pattern> : Instruction {
16 let Namespace = "SystemZ";
18 dag OutOperandList = outs;
19 dag InOperandList = ins;
21 let Pattern = pattern;
22 let AsmString = asmstr;
24 // Used to identify a group of related instructions, such as ST and STY.
27 // "12" for an instruction that has a ...Y equivalent, "20" for that
29 string PairType = "none";
31 // True if this instruction is a simple D(X,B) load of a register
32 // (with no sign or zero extension).
33 bit SimpleBDXLoad = 0;
35 // True if this instruction is a simple D(X,B) store of a register
36 // (with no truncation).
37 bit SimpleBDXStore = 0;
39 // True if this instruction has a 20-bit displacement field.
40 bit Has20BitOffset = 0;
42 // True if addresses in this instruction have an index register.
45 // True if this is a 128-bit pseudo instruction that combines two 64-bit
49 let TSFlags{0} = SimpleBDXLoad;
50 let TSFlags{1} = SimpleBDXStore;
51 let TSFlags{2} = Has20BitOffset;
52 let TSFlags{3} = HasIndex;
53 let TSFlags{4} = Is128Bit;
56 //===----------------------------------------------------------------------===//
57 // Mappings between instructions
58 //===----------------------------------------------------------------------===//
60 // Return the version of an instruction that has an unsigned 12-bit
62 def getDisp12Opcode : InstrMapping {
63 let FilterClass = "InstSystemZ";
64 let RowFields = ["Function"];
65 let ColFields = ["PairType"];
67 let ValueCols = [["12"]];
70 // Return the version of an instruction that has a signed 20-bit displacement.
71 def getDisp20Opcode : InstrMapping {
72 let FilterClass = "InstSystemZ";
73 let RowFields = ["Function"];
74 let ColFields = ["PairType"];
76 let ValueCols = [["20"]];
79 //===----------------------------------------------------------------------===//
80 // Instruction formats
81 //===----------------------------------------------------------------------===//
83 // Formats are specified using operand field declarations of the form:
85 // bits<4> Rn : register input or output for operand n
86 // bits<m> In : immediate value of width m for operand n
87 // bits<4> BDn : address operand n, which has a base and a displacement
88 // bits<m> XBDn : address operand n, which has an index, a base and a
90 // bits<4> Xn : index register for address operand n
91 // bits<4> Mn : mode value for operand n
93 // The operand numbers ("n" in the list above) follow the architecture manual.
94 // Assembly operands sometimes have a different order; in particular, R3 often
95 // is often written between operands 1 and 2.
97 //===----------------------------------------------------------------------===//
99 class InstRI<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
100 : InstSystemZ<4, outs, ins, asmstr, pattern> {
102 field bits<32> SoftFail = 0;
107 let Inst{31-24} = op{11-4};
108 let Inst{23-20} = R1;
109 let Inst{19-16} = op{3-0};
113 class InstRIEb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
114 : InstSystemZ<6, outs, ins, asmstr, pattern> {
116 field bits<48> SoftFail = 0;
123 let Inst{47-40} = op{15-8};
124 let Inst{39-36} = R1;
125 let Inst{35-32} = R2;
126 let Inst{31-16} = RI4;
127 let Inst{15-12} = M3;
129 let Inst{7-0} = op{7-0};
132 class InstRIEc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
133 : InstSystemZ<6, outs, ins, asmstr, pattern> {
135 field bits<48> SoftFail = 0;
142 let Inst{47-40} = op{15-8};
143 let Inst{39-36} = R1;
144 let Inst{35-32} = M3;
145 let Inst{31-16} = RI4;
147 let Inst{7-0} = op{7-0};
150 class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
151 : InstSystemZ<6, outs, ins, asmstr, pattern> {
153 field bits<48> SoftFail = 0;
161 let Inst{47-40} = op{15-8};
162 let Inst{39-36} = R1;
163 let Inst{35-32} = R2;
164 let Inst{31-24} = I3;
165 let Inst{23-16} = I4;
167 let Inst{7-0} = op{7-0};
170 class InstRIL<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
171 : InstSystemZ<6, outs, ins, asmstr, pattern> {
173 field bits<48> SoftFail = 0;
178 let Inst{47-40} = op{11-4};
179 let Inst{39-36} = R1;
180 let Inst{35-32} = op{3-0};
184 class InstRR<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
185 : InstSystemZ<2, outs, ins, asmstr, pattern> {
187 field bits<16> SoftFail = 0;
197 class InstRRD<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
198 : InstSystemZ<4, outs, ins, asmstr, pattern> {
200 field bits<32> SoftFail = 0;
206 let Inst{31-16} = op;
207 let Inst{15-12} = R1;
213 class InstRRE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
214 : InstSystemZ<4, outs, ins, asmstr, pattern> {
216 field bits<32> SoftFail = 0;
221 let Inst{31-16} = op;
227 class InstRRF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
228 : InstSystemZ<4, outs, ins, asmstr, pattern> {
230 field bits<32> SoftFail = 0;
236 let Inst{31-16} = op;
237 let Inst{15-12} = R3;
243 class InstRX<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
244 : InstSystemZ<4, outs, ins, asmstr, pattern> {
246 field bits<32> SoftFail = 0;
251 let Inst{31-24} = op;
252 let Inst{23-20} = R1;
253 let Inst{19-0} = XBD2;
258 class InstRXE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
259 : InstSystemZ<6, outs, ins, asmstr, pattern> {
261 field bits<48> SoftFail = 0;
266 let Inst{47-40} = op{15-8};
267 let Inst{39-36} = R1;
268 let Inst{35-16} = XBD2;
270 let Inst{7-0} = op{7-0};
275 class InstRXF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
276 : InstSystemZ<6, outs, ins, asmstr, pattern> {
278 field bits<48> SoftFail = 0;
284 let Inst{47-40} = op{15-8};
285 let Inst{39-36} = R3;
286 let Inst{35-16} = XBD2;
287 let Inst{15-12} = R1;
289 let Inst{7-0} = op{7-0};
294 class InstRXY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
295 : InstSystemZ<6, outs, ins, asmstr, pattern> {
297 field bits<48> SoftFail = 0;
302 let Inst{47-40} = op{15-8};
303 let Inst{39-36} = R1;
304 let Inst{35-8} = XBD2;
305 let Inst{7-0} = op{7-0};
307 let Has20BitOffset = 1;
311 class InstRS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
312 : InstSystemZ<4, outs, ins, asmstr, pattern> {
314 field bits<32> SoftFail = 0;
320 let Inst{31-24} = op;
321 let Inst{23-20} = R1;
322 let Inst{19-16} = R3;
323 let Inst{15-0} = BD2;
326 class InstRSY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
327 : InstSystemZ<6, outs, ins, asmstr, pattern> {
329 field bits<48> SoftFail = 0;
335 let Inst{47-40} = op{15-8};
336 let Inst{39-36} = R1;
337 let Inst{35-32} = R3;
338 let Inst{31-8} = BD2;
339 let Inst{7-0} = op{7-0};
341 let Has20BitOffset = 1;
344 class InstSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
345 : InstSystemZ<4, outs, ins, asmstr, pattern> {
347 field bits<32> SoftFail = 0;
352 let Inst{31-24} = op;
353 let Inst{23-16} = I2;
354 let Inst{15-0} = BD1;
357 class InstSIL<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
358 : InstSystemZ<6, outs, ins, asmstr, pattern> {
360 field bits<48> SoftFail = 0;
365 let Inst{47-32} = op;
366 let Inst{31-16} = BD1;
370 class InstSIY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
371 : InstSystemZ<6, outs, ins, asmstr, pattern> {
373 field bits<48> SoftFail = 0;
378 let Inst{47-40} = op{15-8};
379 let Inst{39-32} = I2;
380 let Inst{31-8} = BD1;
381 let Inst{7-0} = op{7-0};
383 let Has20BitOffset = 1;
386 //===----------------------------------------------------------------------===//
387 // Instruction definitions with semantics
388 //===----------------------------------------------------------------------===//
390 // These classes have the form <Category><Format>, where <Format> is one
391 // of the formats defined above and where <Category> describes the inputs
392 // and outputs. <Category> can be one of:
395 // One register output operand and no input operands.
398 // One register or immediate input operand and one address input operand.
399 // The instruction stores the first operand to the address.
401 // This category is used for both pure and truncating stores.
404 // One address input operand and two explicit output operands.
405 // The instruction loads a range of registers from the address,
406 // with the explicit operands giving the first and last register
407 // to load. Other loaded registers are added as implicit definitions.
410 // Two explicit input register operands and an address operand.
411 // The instruction stores a range of registers to the address,
412 // with the explicit operands giving the first and last register
413 // to store. Other stored registers are added as implicit uses.
416 // One register output operand and one input operand. The input
417 // operand may be a register, immediate or memory.
420 // One register output operand and two input operands. The first
421 // input operand is always a register and he second may be a register,
422 // immediate or memory.
425 // One register output operand and two input operands. The first
426 // input operand is a register and the second has the same form as
427 // an address (although it isn't actually used to address memory).
430 // Two input operands. The first operand is always a register,
431 // the second may be a register, immediate or memory.
434 // One register output operand and three register input operands.
437 // One output operand and three input operands. The first two
438 // operands are registers and the third is an address. The instruction
439 // both reads from and writes to the address.
442 // One output operand and five input operands. The first two operands
443 // are registers and the other three are immediates.
445 // The format determines which input operands are tied to output operands,
446 // and also determines the shape of any address operand.
448 // Multiclasses of the form <Category><Format>Pair define two instructions,
449 // one with <Category><Format> and one with <Category><Format>Y. The name
450 // of the first instruction has no suffix, the name of the second has
453 //===----------------------------------------------------------------------===//
455 class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
457 : InstRRE<opcode, (outs cls:$R1), (ins),
459 [(set cls:$R1, src)]> {
463 class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
464 : InstRSY<opcode, (outs cls:$R1, cls:$R3), (ins bdaddr20only:$BD2),
465 mnemonic#"\t$R1, $R3, $BD2", []> {
469 class StoreRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
471 : InstRIL<opcode, (outs), (ins cls:$R1, pcrel32:$I2),
472 mnemonic#"\t$R1, $I2",
473 [(operator cls:$R1, pcrel32:$I2)]> {
475 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
476 // However, BDXs have two extra operands and are therefore 6 units more
478 let AddedComplexity = 7;
481 class StoreRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
482 RegisterOperand cls, AddressingMode mode = bdxaddr12only>
483 : InstRX<opcode, (outs), (ins cls:$R1, mode:$XBD2),
484 mnemonic#"\t$R1, $XBD2",
485 [(operator cls:$R1, mode:$XBD2)]> {
489 class StoreRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
490 RegisterOperand cls, AddressingMode mode = bdxaddr20only>
491 : InstRXY<opcode, (outs), (ins cls:$R1, mode:$XBD2),
492 mnemonic#"\t$R1, $XBD2",
493 [(operator cls:$R1, mode:$XBD2)]> {
497 multiclass StoreRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
498 SDPatternOperator operator, RegisterOperand cls> {
499 let Function = mnemonic ## #cls in {
500 let PairType = "12" in
501 def "" : StoreRX<mnemonic, rxOpcode, operator, cls, bdxaddr12pair>;
502 let PairType = "20" in
503 def Y : StoreRXY<mnemonic#"y", rxyOpcode, operator, cls, bdxaddr20pair>;
507 class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
508 : InstRSY<opcode, (outs), (ins cls:$R1, cls:$R3, bdaddr20only:$BD2),
509 mnemonic#"\t$R1, $R3, $BD2", []> {
513 class StoreSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
514 Immediate imm, AddressingMode mode = bdaddr12only>
515 : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
516 mnemonic#"\t$BD1, $I2",
517 [(operator imm:$I2, mode:$BD1)]> {
521 class StoreSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
522 Immediate imm, AddressingMode mode = bdaddr20only>
523 : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
524 mnemonic#"\t$BD1, $I2",
525 [(operator imm:$I2, mode:$BD1)]> {
529 class StoreSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
531 : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
532 mnemonic#"\t$BD1, $I2",
533 [(operator imm:$I2, bdaddr12only:$BD1)]> {
537 multiclass StoreSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
538 SDPatternOperator operator, Immediate imm> {
539 let Function = mnemonic in {
540 let PairType = "12" in
541 def "" : StoreSI<mnemonic, siOpcode, operator, imm, bdaddr12pair>;
542 let PairType = "20" in
543 def Y : StoreSIY<mnemonic#"y", siyOpcode, operator, imm, bdaddr20pair>;
547 class UnaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
548 RegisterOperand cls1, RegisterOperand cls2>
549 : InstRR<opcode, (outs cls1:$R1), (ins cls2:$R2),
550 mnemonic#"\t$R1, $R2",
551 [(set cls1:$R1, (operator cls2:$R2))]>;
553 class UnaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
554 RegisterOperand cls1, RegisterOperand cls2>
555 : InstRRE<opcode, (outs cls1:$R1), (ins cls2:$R2),
556 mnemonic#"\t$R1, $R2",
557 [(set cls1:$R1, (operator cls2:$R2))]>;
559 class UnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
560 RegisterOperand cls2>
561 : InstRRF<opcode, (outs cls1:$R1), (ins uimm8zx4:$R3, cls2:$R2),
562 mnemonic#"\t$R1, $R3, $R2", []>;
564 class UnaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
565 RegisterOperand cls, Immediate imm>
566 : InstRI<opcode, (outs cls:$R1), (ins imm:$I2),
567 mnemonic#"\t$R1, $I2",
568 [(set cls:$R1, (operator imm:$I2))]>;
570 class UnaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
571 RegisterOperand cls, Immediate imm>
572 : InstRIL<opcode, (outs cls:$R1), (ins imm:$I2),
573 mnemonic#"\t$R1, $I2",
574 [(set cls:$R1, (operator imm:$I2))]>;
576 class UnaryRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
578 : InstRIL<opcode, (outs cls:$R1), (ins pcrel32:$I2),
579 mnemonic#"\t$R1, $I2",
580 [(set cls:$R1, (operator pcrel32:$I2))]> {
582 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
583 // However, BDXs have two extra operands and are therefore 6 units more
585 let AddedComplexity = 7;
588 class UnaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
589 RegisterOperand cls, AddressingMode mode = bdxaddr12only>
590 : InstRX<opcode, (outs cls:$R1), (ins mode:$XBD2),
591 mnemonic#"\t$R1, $XBD2",
592 [(set cls:$R1, (operator mode:$XBD2))]> {
596 class UnaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
598 : InstRXE<opcode, (outs cls:$R1), (ins bdxaddr12only:$XBD2),
599 mnemonic#"\t$R1, $XBD2",
600 [(set cls:$R1, (operator bdxaddr12only:$XBD2))]> {
604 class UnaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
605 RegisterOperand cls, AddressingMode mode = bdxaddr20only>
606 : InstRXY<opcode, (outs cls:$R1), (ins mode:$XBD2),
607 mnemonic#"\t$R1, $XBD2",
608 [(set cls:$R1, (operator mode:$XBD2))]> {
612 multiclass UnaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
613 SDPatternOperator operator, RegisterOperand cls> {
614 let Function = mnemonic ## #cls in {
615 let PairType = "12" in
616 def "" : UnaryRX<mnemonic, rxOpcode, operator, cls, bdxaddr12pair>;
617 let PairType = "20" in
618 def Y : UnaryRXY<mnemonic#"y", rxyOpcode, operator, cls, bdxaddr20pair>;
622 class BinaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
623 RegisterOperand cls1, RegisterOperand cls2>
624 : InstRR<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
625 mnemonic#"\t$R1, $R2",
626 [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
627 let Constraints = "$R1 = $R1src";
628 let DisableEncoding = "$R1src";
631 class BinaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
632 RegisterOperand cls1, RegisterOperand cls2>
633 : InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
634 mnemonic#"\t$R1, $R2",
635 [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
636 let Constraints = "$R1 = $R1src";
637 let DisableEncoding = "$R1src";
640 class BinaryRRF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
641 RegisterOperand cls1, RegisterOperand cls2>
642 : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R3, cls2:$R2),
643 mnemonic#"\t$R1, $R3, $R2",
644 [(set cls1:$R1, (operator cls1:$R3, cls2:$R2))]>;
646 class BinaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
647 RegisterOperand cls, Immediate imm>
648 : InstRI<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
649 mnemonic#"\t$R1, $I2",
650 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
651 let Constraints = "$R1 = $R1src";
652 let DisableEncoding = "$R1src";
655 class BinaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
656 RegisterOperand cls, Immediate imm>
657 : InstRIL<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
658 mnemonic#"\t$R1, $I2",
659 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
660 let Constraints = "$R1 = $R1src";
661 let DisableEncoding = "$R1src";
664 class BinaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
665 RegisterOperand cls, SDPatternOperator load,
666 AddressingMode mode = bdxaddr12only>
667 : InstRX<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
668 mnemonic#"\t$R1, $XBD2",
669 [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
670 let Constraints = "$R1 = $R1src";
671 let DisableEncoding = "$R1src";
675 class BinaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
676 RegisterOperand cls, SDPatternOperator load>
677 : InstRXE<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr12only:$XBD2),
678 mnemonic#"\t$R1, $XBD2",
679 [(set cls:$R1, (operator cls:$R1src,
680 (load bdxaddr12only:$XBD2)))]> {
681 let Constraints = "$R1 = $R1src";
682 let DisableEncoding = "$R1src";
686 class BinaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
687 RegisterOperand cls, SDPatternOperator load,
688 AddressingMode mode = bdxaddr20only>
689 : InstRXY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
690 mnemonic#"\t$R1, $XBD2",
691 [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
692 let Constraints = "$R1 = $R1src";
693 let DisableEncoding = "$R1src";
697 multiclass BinaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
698 SDPatternOperator operator, RegisterOperand cls,
699 SDPatternOperator load> {
700 let Function = mnemonic ## #cls in {
701 let PairType = "12" in
702 def "" : BinaryRX<mnemonic, rxOpcode, operator, cls, load, bdxaddr12pair>;
703 let PairType = "20" in
704 def Y : BinaryRXY<mnemonic#"y", rxyOpcode, operator, cls, load,
709 class BinarySI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
710 Operand imm, AddressingMode mode = bdaddr12only>
711 : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
712 mnemonic#"\t$BD1, $I2",
713 [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
718 class BinarySIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
719 Operand imm, AddressingMode mode = bdaddr20only>
720 : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
721 mnemonic#"\t$BD1, $I2",
722 [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
727 multiclass BinarySIPair<string mnemonic, bits<8> siOpcode,
728 bits<16> siyOpcode, SDPatternOperator operator,
730 let Function = mnemonic ## #cls in {
731 let PairType = "12" in
732 def "" : BinarySI<mnemonic, siOpcode, operator, imm, bdaddr12pair>;
733 let PairType = "20" in
734 def Y : BinarySIY<mnemonic#"y", siyOpcode, operator, imm, bdaddr20pair>;
738 class ShiftRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
739 RegisterOperand cls, AddressingMode mode>
740 : InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2),
741 mnemonic#"\t$R1, $BD2",
742 [(set cls:$R1, (operator cls:$R1src, mode:$BD2))]> {
744 let Constraints = "$R1 = $R1src";
745 let DisableEncoding = "$R1src";
748 class ShiftRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
749 RegisterOperand cls, AddressingMode mode>
750 : InstRSY<opcode, (outs cls:$R1), (ins cls:$R3, mode:$BD2),
751 mnemonic#"\t$R1, $R3, $BD2",
752 [(set cls:$R1, (operator cls:$R3, mode:$BD2))]>;
754 class CompareRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
755 RegisterOperand cls1, RegisterOperand cls2>
756 : InstRR<opcode, (outs), (ins cls1:$R1, cls2:$R2),
757 mnemonic#"\t$R1, $R2",
758 [(operator cls1:$R1, cls2:$R2)]>;
760 class CompareRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
761 RegisterOperand cls1, RegisterOperand cls2>
762 : InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2),
763 mnemonic#"\t$R1, $R2",
764 [(operator cls1:$R1, cls2:$R2)]>;
766 class CompareRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
767 RegisterOperand cls, Immediate imm>
768 : InstRI<opcode, (outs), (ins cls:$R1, imm:$I2),
769 mnemonic#"\t$R1, $I2",
770 [(operator cls:$R1, imm:$I2)]>;
772 class CompareRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
773 RegisterOperand cls, Immediate imm>
774 : InstRIL<opcode, (outs), (ins cls:$R1, imm:$I2),
775 mnemonic#"\t$R1, $I2",
776 [(operator cls:$R1, imm:$I2)]>;
778 class CompareRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
779 RegisterOperand cls, SDPatternOperator load>
780 : InstRIL<opcode, (outs), (ins cls:$R1, pcrel32:$I2),
781 mnemonic#"\t$R1, $I2",
782 [(operator cls:$R1, (load pcrel32:$I2))]> {
784 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
785 // However, BDXs have two extra operands and are therefore 6 units more
787 let AddedComplexity = 7;
790 class CompareRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
791 RegisterOperand cls, SDPatternOperator load,
792 AddressingMode mode = bdxaddr12only>
793 : InstRX<opcode, (outs), (ins cls:$R1, mode:$XBD2),
794 mnemonic#"\t$R1, $XBD2",
795 [(operator cls:$R1, (load mode:$XBD2))]> {
799 class CompareRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
800 RegisterOperand cls, SDPatternOperator load>
801 : InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
802 mnemonic#"\t$R1, $XBD2",
803 [(operator cls:$R1, (load bdxaddr12only:$XBD2))]> {
807 class CompareRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
808 RegisterOperand cls, SDPatternOperator load,
809 AddressingMode mode = bdxaddr20only>
810 : InstRXY<opcode, (outs), (ins cls:$R1, mode:$XBD2),
811 mnemonic#"\t$R1, $XBD2",
812 [(operator cls:$R1, (load mode:$XBD2))]> {
816 multiclass CompareRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
817 SDPatternOperator operator, RegisterOperand cls,
818 SDPatternOperator load> {
819 let Function = mnemonic ## #cls in {
820 let PairType = "12" in
821 def "" : CompareRX<mnemonic, rxOpcode, operator, cls,
822 load, bdxaddr12pair>;
823 let PairType = "20" in
824 def Y : CompareRXY<mnemonic#"y", rxyOpcode, operator, cls,
825 load, bdxaddr20pair>;
829 class CompareSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
830 SDPatternOperator load, Immediate imm,
831 AddressingMode mode = bdaddr12only>
832 : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
833 mnemonic#"\t$BD1, $I2",
834 [(operator (load mode:$BD1), imm:$I2)]> {
838 class CompareSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
839 SDPatternOperator load, Immediate imm>
840 : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
841 mnemonic#"\t$BD1, $I2",
842 [(operator (load bdaddr12only:$BD1), imm:$I2)]> {
846 class CompareSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
847 SDPatternOperator load, Immediate imm,
848 AddressingMode mode = bdaddr20only>
849 : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
850 mnemonic#"\t$BD1, $I2",
851 [(operator (load mode:$BD1), imm:$I2)]> {
855 multiclass CompareSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
856 SDPatternOperator operator, SDPatternOperator load,
858 let Function = mnemonic in {
859 let PairType = "12" in
860 def "" : CompareSI<mnemonic, siOpcode, operator, load, imm, bdaddr12pair>;
861 let PairType = "20" in
862 def Y : CompareSIY<mnemonic#"y", siyOpcode, operator, load, imm,
867 class TernaryRRD<string mnemonic, bits<16> opcode,
868 SDPatternOperator operator, RegisterOperand cls>
869 : InstRRD<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, cls:$R2),
870 mnemonic#"\t$R1, $R3, $R2",
871 [(set cls:$R1, (operator cls:$R1src, cls:$R3, cls:$R2))]> {
872 let Constraints = "$R1 = $R1src";
873 let DisableEncoding = "$R1src";
876 class TernaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
877 RegisterOperand cls, SDPatternOperator load>
878 : InstRXF<opcode, (outs cls:$R1),
879 (ins cls:$R1src, cls:$R3, bdxaddr12only:$XBD2),
880 mnemonic#"\t$R1, $R3, $XBD2",
881 [(set cls:$R1, (operator cls:$R1src, cls:$R3,
882 (load bdxaddr12only:$XBD2)))]> {
883 let Constraints = "$R1 = $R1src";
884 let DisableEncoding = "$R1src";
888 class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
889 RegisterOperand cls, AddressingMode mode = bdaddr12only>
890 : InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
891 mnemonic#"\t$R1, $R3, $BD2",
892 [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
893 let Constraints = "$R1 = $R1src";
894 let DisableEncoding = "$R1src";
899 class CmpSwapRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
900 RegisterOperand cls, AddressingMode mode = bdaddr20only>
901 : InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
902 mnemonic#"\t$R1, $R3, $BD2",
903 [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
904 let Constraints = "$R1 = $R1src";
905 let DisableEncoding = "$R1src";
910 multiclass CmpSwapRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
911 SDPatternOperator operator, RegisterOperand cls> {
912 let Function = mnemonic ## #cls in {
913 let PairType = "12" in
914 def "" : CmpSwapRS<mnemonic, rsOpcode, operator, cls, bdaddr12pair>;
915 let PairType = "20" in
916 def Y : CmpSwapRSY<mnemonic#"y", rsyOpcode, operator, cls, bdaddr20pair>;
920 class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
921 RegisterOperand cls2>
922 : InstRIEf<opcode, (outs cls1:$R1),
923 (ins cls1:$R1src, cls2:$R2,
924 uimm8zx6:$I3, uimm8zx6:$I4, uimm8zx6:$I5),
925 mnemonic#"\t$R1, $R2, $I3, $I4, $I5", []> {
926 let Constraints = "$R1 = $R1src";
927 let DisableEncoding = "$R1src";
930 //===----------------------------------------------------------------------===//
931 // Pseudo instructions
932 //===----------------------------------------------------------------------===//
934 // Convenience instructions that get lowered to real instructions
935 // by either SystemZTargetLowering::EmitInstrWithCustomInserter()
936 // or SystemZInstrInfo::expandPostRAPseudo().
938 //===----------------------------------------------------------------------===//
940 class Pseudo<dag outs, dag ins, list<dag> pattern>
941 : InstSystemZ<0, outs, ins, "", pattern> {
943 let isCodeGenOnly = 1;
946 // Implements "$dst = $cc & (8 >> CC) ? $src1 : $src2", where CC is
947 // the value of the PSW's 2-bit condition code field.
948 class SelectWrapper<RegisterOperand cls>
949 : Pseudo<(outs cls:$dst), (ins cls:$src1, cls:$src2, i8imm:$cc),
950 [(set cls:$dst, (z_select_ccmask cls:$src1, cls:$src2, imm:$cc))]> {
951 let usesCustomInserter = 1;
952 // Although the instructions used by these nodes do not in themselves
953 // change CC, the insertion requires new blocks, and CC cannot be live
959 // OPERATOR is ATOMIC_SWAP or an ATOMIC_LOAD_* operation. PAT and OPERAND
960 // describe the second (non-memory) operand.
961 class AtomicLoadBinary<SDPatternOperator operator, RegisterOperand cls,
962 dag pat, DAGOperand operand>
963 : Pseudo<(outs cls:$dst), (ins bdaddr20only:$ptr, operand:$src2),
964 [(set cls:$dst, (operator bdaddr20only:$ptr, pat))]> {
966 let Has20BitOffset = 1;
969 let usesCustomInserter = 1;
972 // Specializations of AtomicLoadWBinary.
973 class AtomicLoadBinaryReg32<SDPatternOperator operator>
974 : AtomicLoadBinary<operator, GR32, (i32 GR32:$src2), GR32>;
975 class AtomicLoadBinaryImm32<SDPatternOperator operator, Immediate imm>
976 : AtomicLoadBinary<operator, GR32, (i32 imm:$src2), imm>;
977 class AtomicLoadBinaryReg64<SDPatternOperator operator>
978 : AtomicLoadBinary<operator, GR64, (i64 GR64:$src2), GR64>;
979 class AtomicLoadBinaryImm64<SDPatternOperator operator, Immediate imm>
980 : AtomicLoadBinary<operator, GR64, (i64 imm:$src2), imm>;
982 // OPERATOR is ATOMIC_SWAPW or an ATOMIC_LOADW_* operation. PAT and OPERAND
983 // describe the second (non-memory) operand.
984 class AtomicLoadWBinary<SDPatternOperator operator, dag pat,
986 : Pseudo<(outs GR32:$dst),
987 (ins bdaddr20only:$ptr, operand:$src2, ADDR32:$bitshift,
988 ADDR32:$negbitshift, uimm32:$bitsize),
989 [(set GR32:$dst, (operator bdaddr20only:$ptr, pat, ADDR32:$bitshift,
990 ADDR32:$negbitshift, uimm32:$bitsize))]> {
992 let Has20BitOffset = 1;
995 let usesCustomInserter = 1;
998 // Specializations of AtomicLoadWBinary.
999 class AtomicLoadWBinaryReg<SDPatternOperator operator>
1000 : AtomicLoadWBinary<operator, (i32 GR32:$src2), GR32>;
1001 class AtomicLoadWBinaryImm<SDPatternOperator operator, Immediate imm>
1002 : AtomicLoadWBinary<operator, (i32 imm:$src2), imm>;