1 //==- SystemZInstrFormats.td - SystemZ Instruction Formats --*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Basic SystemZ instruction definition
12 //===----------------------------------------------------------------------===//
14 class InstSystemZ<int size, dag outs, dag ins, string asmstr,
15 list<dag> pattern> : Instruction {
16 let Namespace = "SystemZ";
18 dag OutOperandList = outs;
19 dag InOperandList = ins;
21 let Pattern = pattern;
22 let AsmString = asmstr;
24 // Some instructions come in pairs, one having a 12-bit displacement
25 // and the other having a 20-bit displacement. Both instructions in
26 // the pair have the same DispKey and their DispSizes are "12" and "20"
29 string DispSize = "none";
31 // Many register-based <INSN>R instructions have a memory-based <INSN>
32 // counterpart. OpKey uniquely identifies <INSN>, while OpType is
33 // "reg" for <INSN>R and "mem" for <INSN>.
35 string OpType = "none";
37 // Many distinct-operands instructions have older 2-operand equivalents.
38 // NumOpsKey uniquely identifies one of these 2-operand and 3-operand pairs,
39 // with NumOpsValue being "2" or "3" as appropriate.
40 string NumOpsKey = "";
41 string NumOpsValue = "none";
43 // True if this instruction is a simple D(X,B) load of a register
44 // (with no sign or zero extension).
45 bit SimpleBDXLoad = 0;
47 // True if this instruction is a simple D(X,B) store of a register
48 // (with no truncation).
49 bit SimpleBDXStore = 0;
51 // True if this instruction has a 20-bit displacement field.
52 bit Has20BitOffset = 0;
54 // True if addresses in this instruction have an index register.
57 // True if this is a 128-bit pseudo instruction that combines two 64-bit
61 // The access size of all memory operands in bytes, or 0 if not known.
62 bits<5> AccessBytes = 0;
64 // If the instruction sets CC to a useful value, this gives the mask
65 // of all possible CC results. The mask has the same form as
69 // The subset of CCValues that have the same meaning as they would after
70 // a comparison of the first operand against zero.
71 bits<4> CompareZeroCCMask = 0;
73 // True if the instruction is conditional and if the CC mask operand
74 // comes first (as for BRC, etc.).
77 // Similar, but true if the CC mask operand comes last (as for LOC, etc.).
80 // True if the instruction is the "logical" rather than "arithmetic" form,
81 // in cases where a distinction exists.
84 let TSFlags{0} = SimpleBDXLoad;
85 let TSFlags{1} = SimpleBDXStore;
86 let TSFlags{2} = Has20BitOffset;
87 let TSFlags{3} = HasIndex;
88 let TSFlags{4} = Is128Bit;
89 let TSFlags{9-5} = AccessBytes;
90 let TSFlags{13-10} = CCValues;
91 let TSFlags{17-14} = CompareZeroCCMask;
92 let TSFlags{18} = CCMaskFirst;
93 let TSFlags{19} = CCMaskLast;
94 let TSFlags{20} = IsLogical;
97 //===----------------------------------------------------------------------===//
98 // Mappings between instructions
99 //===----------------------------------------------------------------------===//
101 // Return the version of an instruction that has an unsigned 12-bit
103 def getDisp12Opcode : InstrMapping {
104 let FilterClass = "InstSystemZ";
105 let RowFields = ["DispKey"];
106 let ColFields = ["DispSize"];
108 let ValueCols = [["12"]];
111 // Return the version of an instruction that has a signed 20-bit displacement.
112 def getDisp20Opcode : InstrMapping {
113 let FilterClass = "InstSystemZ";
114 let RowFields = ["DispKey"];
115 let ColFields = ["DispSize"];
117 let ValueCols = [["20"]];
120 // Return the memory form of a register instruction.
121 def getMemOpcode : InstrMapping {
122 let FilterClass = "InstSystemZ";
123 let RowFields = ["OpKey"];
124 let ColFields = ["OpType"];
125 let KeyCol = ["reg"];
126 let ValueCols = [["mem"]];
129 // Return the 3-operand form of a 2-operand instruction.
130 def getThreeOperandOpcode : InstrMapping {
131 let FilterClass = "InstSystemZ";
132 let RowFields = ["NumOpsKey"];
133 let ColFields = ["NumOpsValue"];
135 let ValueCols = [["3"]];
138 //===----------------------------------------------------------------------===//
139 // Instruction formats
140 //===----------------------------------------------------------------------===//
142 // Formats are specified using operand field declarations of the form:
144 // bits<4> Rn : register input or output for operand n
145 // bits<m> In : immediate value of width m for operand n
146 // bits<4> BDn : address operand n, which has a base and a displacement
147 // bits<m> XBDn : address operand n, which has an index, a base and a
149 // bits<4> Xn : index register for address operand n
150 // bits<4> Mn : mode value for operand n
152 // The operand numbers ("n" in the list above) follow the architecture manual.
153 // Assembly operands sometimes have a different order; in particular, R3 often
154 // is often written between operands 1 and 2.
156 //===----------------------------------------------------------------------===//
158 class InstRI<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
159 : InstSystemZ<4, outs, ins, asmstr, pattern> {
161 field bits<32> SoftFail = 0;
166 let Inst{31-24} = op{11-4};
167 let Inst{23-20} = R1;
168 let Inst{19-16} = op{3-0};
172 class InstRIEb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
173 : InstSystemZ<6, outs, ins, asmstr, pattern> {
175 field bits<48> SoftFail = 0;
182 let Inst{47-40} = op{15-8};
183 let Inst{39-36} = R1;
184 let Inst{35-32} = R2;
185 let Inst{31-16} = RI4;
186 let Inst{15-12} = M3;
188 let Inst{7-0} = op{7-0};
191 class InstRIEc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
192 : InstSystemZ<6, outs, ins, asmstr, pattern> {
194 field bits<48> SoftFail = 0;
201 let Inst{47-40} = op{15-8};
202 let Inst{39-36} = R1;
203 let Inst{35-32} = M3;
204 let Inst{31-16} = RI4;
206 let Inst{7-0} = op{7-0};
209 class InstRIEd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
210 : InstSystemZ<6, outs, ins, asmstr, pattern> {
212 field bits<48> SoftFail = 0;
218 let Inst{47-40} = op{15-8};
219 let Inst{39-36} = R1;
220 let Inst{35-32} = R3;
221 let Inst{31-16} = I2;
223 let Inst{7-0} = op{7-0};
226 class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
227 : InstSystemZ<6, outs, ins, asmstr, pattern> {
229 field bits<48> SoftFail = 0;
237 let Inst{47-40} = op{15-8};
238 let Inst{39-36} = R1;
239 let Inst{35-32} = R2;
240 let Inst{31-24} = I3;
241 let Inst{23-16} = I4;
243 let Inst{7-0} = op{7-0};
246 class InstRIL<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
247 : InstSystemZ<6, outs, ins, asmstr, pattern> {
249 field bits<48> SoftFail = 0;
254 let Inst{47-40} = op{11-4};
255 let Inst{39-36} = R1;
256 let Inst{35-32} = op{3-0};
260 class InstRR<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
261 : InstSystemZ<2, outs, ins, asmstr, pattern> {
263 field bits<16> SoftFail = 0;
273 class InstRRD<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
274 : InstSystemZ<4, outs, ins, asmstr, pattern> {
276 field bits<32> SoftFail = 0;
282 let Inst{31-16} = op;
283 let Inst{15-12} = R1;
289 class InstRRE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
290 : InstSystemZ<4, outs, ins, asmstr, pattern> {
292 field bits<32> SoftFail = 0;
297 let Inst{31-16} = op;
303 class InstRRF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
304 : InstSystemZ<4, outs, ins, asmstr, pattern> {
306 field bits<32> SoftFail = 0;
313 let Inst{31-16} = op;
314 let Inst{15-12} = R3;
320 class InstRX<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
321 : InstSystemZ<4, outs, ins, asmstr, pattern> {
323 field bits<32> SoftFail = 0;
328 let Inst{31-24} = op;
329 let Inst{23-20} = R1;
330 let Inst{19-0} = XBD2;
335 class InstRXE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
336 : InstSystemZ<6, outs, ins, asmstr, pattern> {
338 field bits<48> SoftFail = 0;
343 let Inst{47-40} = op{15-8};
344 let Inst{39-36} = R1;
345 let Inst{35-16} = XBD2;
347 let Inst{7-0} = op{7-0};
352 class InstRXF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
353 : InstSystemZ<6, outs, ins, asmstr, pattern> {
355 field bits<48> SoftFail = 0;
361 let Inst{47-40} = op{15-8};
362 let Inst{39-36} = R3;
363 let Inst{35-16} = XBD2;
364 let Inst{15-12} = R1;
366 let Inst{7-0} = op{7-0};
371 class InstRXY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
372 : InstSystemZ<6, outs, ins, asmstr, pattern> {
374 field bits<48> SoftFail = 0;
379 let Inst{47-40} = op{15-8};
380 let Inst{39-36} = R1;
381 let Inst{35-8} = XBD2;
382 let Inst{7-0} = op{7-0};
384 let Has20BitOffset = 1;
388 class InstRS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
389 : InstSystemZ<4, outs, ins, asmstr, pattern> {
391 field bits<32> SoftFail = 0;
397 let Inst{31-24} = op;
398 let Inst{23-20} = R1;
399 let Inst{19-16} = R3;
400 let Inst{15-0} = BD2;
403 class InstRSY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
404 : InstSystemZ<6, outs, ins, asmstr, pattern> {
406 field bits<48> SoftFail = 0;
412 let Inst{47-40} = op{15-8};
413 let Inst{39-36} = R1;
414 let Inst{35-32} = R3;
415 let Inst{31-8} = BD2;
416 let Inst{7-0} = op{7-0};
418 let Has20BitOffset = 1;
421 class InstSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
422 : InstSystemZ<4, outs, ins, asmstr, pattern> {
424 field bits<32> SoftFail = 0;
429 let Inst{31-24} = op;
430 let Inst{23-16} = I2;
431 let Inst{15-0} = BD1;
434 class InstSIL<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
435 : InstSystemZ<6, outs, ins, asmstr, pattern> {
437 field bits<48> SoftFail = 0;
442 let Inst{47-32} = op;
443 let Inst{31-16} = BD1;
447 class InstSIY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
448 : InstSystemZ<6, outs, ins, asmstr, pattern> {
450 field bits<48> SoftFail = 0;
455 let Inst{47-40} = op{15-8};
456 let Inst{39-32} = I2;
457 let Inst{31-8} = BD1;
458 let Inst{7-0} = op{7-0};
460 let Has20BitOffset = 1;
463 class InstSS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
464 : InstSystemZ<6, outs, ins, asmstr, pattern> {
466 field bits<48> SoftFail = 0;
471 let Inst{47-40} = op;
472 let Inst{39-16} = BDL1;
473 let Inst{15-0} = BD2;
476 //===----------------------------------------------------------------------===//
477 // Instruction definitions with semantics
478 //===----------------------------------------------------------------------===//
480 // These classes have the form [Cond]<Category><Format>, where <Format> is one
481 // of the formats defined above and where <Category> describes the inputs
482 // and outputs. "Cond" is used if the instruction is conditional,
483 // in which case the 4-bit condition-code mask is added as a final operand.
484 // <Category> can be one of:
487 // One register output operand and no input operands.
490 // One register output operand, one register input operand and
491 // one branch displacement. The instructions stores a modified
492 // form of the source register in the destination register and
493 // branches on the result.
496 // One register or immediate input operand and one address input operand.
497 // The instruction stores the first operand to the address.
499 // This category is used for both pure and truncating stores.
502 // One address input operand and two explicit output operands.
503 // The instruction loads a range of registers from the address,
504 // with the explicit operands giving the first and last register
505 // to load. Other loaded registers are added as implicit definitions.
508 // Two explicit input register operands and an address operand.
509 // The instruction stores a range of registers to the address,
510 // with the explicit operands giving the first and last register
511 // to store. Other stored registers are added as implicit uses.
514 // One register output operand and one input operand. The input
515 // operand may be a register, immediate or memory.
518 // One register output operand and two input operands. The first
519 // input operand is always a register and the second may be a register,
520 // immediate or memory.
523 // One register output operand and two input operands. The first
524 // input operand is a register and the second has the same form as
525 // an address (although it isn't actually used to address memory).
528 // Two input operands. The first operand is always a register,
529 // the second may be a register, immediate or memory.
532 // One register output operand and three register input operands.
535 // One output operand and two input operands. The first input operand
536 // is a register and the second is an address.
539 // One output operand and three input operands. The first two
540 // operands are registers and the third is an address. The instruction
541 // both reads from and writes to the address.
544 // One output operand and five input operands. The first two operands
545 // are registers and the other three are immediates.
548 // One 4-bit immediate operand and one address operand. The immediate
549 // operand is 1 for a load prefetch and 2 for a store prefetch.
551 // The format determines which input operands are tied to output operands,
552 // and also determines the shape of any address operand.
554 // Multiclasses of the form <Category><Format>Pair define two instructions,
555 // one with <Category><Format> and one with <Category><Format>Y. The name
556 // of the first instruction has no suffix, the name of the second has
559 //===----------------------------------------------------------------------===//
561 class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
563 : InstRRE<opcode, (outs cls:$R1), (ins),
565 [(set cls:$R1, src)]> {
569 class BranchUnaryRI<string mnemonic, bits<12> opcode, RegisterOperand cls>
570 : InstRI<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget16:$I2),
571 mnemonic##"\t$R1, $I2", []> {
573 let isTerminator = 1;
574 let Constraints = "$R1 = $R1src";
575 let DisableEncoding = "$R1src";
578 class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
579 : InstRSY<opcode, (outs cls:$R1, cls:$R3), (ins bdaddr20only:$BD2),
580 mnemonic#"\t$R1, $R3, $BD2", []> {
584 class StoreRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
586 : InstRIL<opcode, (outs), (ins cls:$R1, pcrel32:$I2),
587 mnemonic#"\t$R1, $I2",
588 [(operator cls:$R1, pcrel32:$I2)]> {
590 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
591 // However, BDXs have two extra operands and are therefore 6 units more
593 let AddedComplexity = 7;
596 class StoreRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
597 RegisterOperand cls, bits<5> bytes,
598 AddressingMode mode = bdxaddr12only>
599 : InstRX<opcode, (outs), (ins cls:$R1, mode:$XBD2),
600 mnemonic#"\t$R1, $XBD2",
601 [(operator cls:$R1, mode:$XBD2)]> {
602 let OpKey = mnemonic ## cls;
605 let AccessBytes = bytes;
608 class StoreRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
609 RegisterOperand cls, bits<5> bytes,
610 AddressingMode mode = bdxaddr20only>
611 : InstRXY<opcode, (outs), (ins cls:$R1, mode:$XBD2),
612 mnemonic#"\t$R1, $XBD2",
613 [(operator cls:$R1, mode:$XBD2)]> {
614 let OpKey = mnemonic ## cls;
617 let AccessBytes = bytes;
620 multiclass StoreRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
621 SDPatternOperator operator, RegisterOperand cls,
623 let DispKey = mnemonic ## #cls in {
624 let DispSize = "12" in
625 def "" : StoreRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>;
626 let DispSize = "20" in
627 def Y : StoreRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes,
632 class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
633 : InstRSY<opcode, (outs), (ins cls:$R1, cls:$R3, bdaddr20only:$BD2),
634 mnemonic#"\t$R1, $R3, $BD2", []> {
638 // StoreSI* instructions are used to store an integer to memory, but the
639 // addresses are more restricted than for normal stores. If we are in the
640 // situation of having to force either the address into a register or the
641 // constant into a register, it's usually better to do the latter.
642 // We therefore match the address in the same way as a normal store and
643 // only use the StoreSI* instruction if the matched address is suitable.
644 class StoreSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
646 : InstSI<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2),
647 mnemonic#"\t$BD1, $I2",
648 [(operator imm:$I2, mviaddr12pair:$BD1)]> {
652 class StoreSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
654 : InstSIY<opcode, (outs), (ins mviaddr20pair:$BD1, imm:$I2),
655 mnemonic#"\t$BD1, $I2",
656 [(operator imm:$I2, mviaddr20pair:$BD1)]> {
660 class StoreSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
662 : InstSIL<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2),
663 mnemonic#"\t$BD1, $I2",
664 [(operator imm:$I2, mviaddr12pair:$BD1)]> {
668 multiclass StoreSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
669 SDPatternOperator operator, Immediate imm> {
670 let DispKey = mnemonic in {
671 let DispSize = "12" in
672 def "" : StoreSI<mnemonic, siOpcode, operator, imm>;
673 let DispSize = "20" in
674 def Y : StoreSIY<mnemonic#"y", siyOpcode, operator, imm>;
678 class CondStoreRSY<string mnemonic, bits<16> opcode,
679 RegisterOperand cls, bits<5> bytes,
680 AddressingMode mode = bdaddr20only>
681 : InstRSY<opcode, (outs), (ins cls:$R1, mode:$BD2, cond4:$valid, cond4:$R3),
682 mnemonic#"$R3\t$R1, $BD2", []>,
683 Requires<[FeatureLoadStoreOnCond]> {
685 let AccessBytes = bytes;
689 // Like CondStoreRSY, but used for the raw assembly form. The condition-code
690 // mask is the third operand rather than being part of the mnemonic.
691 class AsmCondStoreRSY<string mnemonic, bits<16> opcode,
692 RegisterOperand cls, bits<5> bytes,
693 AddressingMode mode = bdaddr20only>
694 : InstRSY<opcode, (outs), (ins cls:$R1, mode:$BD2, uimm8zx4:$R3),
695 mnemonic#"\t$R1, $BD2, $R3", []>,
696 Requires<[FeatureLoadStoreOnCond]> {
698 let AccessBytes = bytes;
701 // Like CondStoreRSY, but with a fixed CC mask.
702 class FixedCondStoreRSY<string mnemonic, bits<16> opcode,
703 RegisterOperand cls, bits<4> ccmask, bits<5> bytes,
704 AddressingMode mode = bdaddr20only>
705 : InstRSY<opcode, (outs), (ins cls:$R1, mode:$BD2),
706 mnemonic#"\t$R1, $BD2", []>,
707 Requires<[FeatureLoadStoreOnCond]> {
709 let AccessBytes = bytes;
713 class UnaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
714 RegisterOperand cls1, RegisterOperand cls2>
715 : InstRR<opcode, (outs cls1:$R1), (ins cls2:$R2),
716 mnemonic#"r\t$R1, $R2",
717 [(set cls1:$R1, (operator cls2:$R2))]> {
718 let OpKey = mnemonic ## cls1;
722 class UnaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
723 RegisterOperand cls1, RegisterOperand cls2>
724 : InstRRE<opcode, (outs cls1:$R1), (ins cls2:$R2),
725 mnemonic#"r\t$R1, $R2",
726 [(set cls1:$R1, (operator cls2:$R2))]> {
727 let OpKey = mnemonic ## cls1;
731 class UnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
732 RegisterOperand cls2>
733 : InstRRF<opcode, (outs cls1:$R1), (ins uimm8zx4:$R3, cls2:$R2),
734 mnemonic#"r\t$R1, $R3, $R2", []> {
735 let OpKey = mnemonic ## cls1;
740 class UnaryRRF4<string mnemonic, bits<16> opcode, RegisterOperand cls1,
741 RegisterOperand cls2>
742 : InstRRF<opcode, (outs cls1:$R1), (ins uimm8zx4:$R3, cls2:$R2, uimm8zx4:$R4),
743 mnemonic#"\t$R1, $R3, $R2, $R4", []>;
745 // These instructions are generated by if conversion. The old value of R1
746 // is added as an implicit use.
747 class CondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
748 RegisterOperand cls2>
749 : InstRRF<opcode, (outs cls1:$R1), (ins cls2:$R2, cond4:$valid, cond4:$R3),
750 mnemonic#"r$R3\t$R1, $R2", []>,
751 Requires<[FeatureLoadStoreOnCond]> {
756 // Like CondUnaryRRF, but used for the raw assembly form. The condition-code
757 // mask is the third operand rather than being part of the mnemonic.
758 class AsmCondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
759 RegisterOperand cls2>
760 : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2, uimm8zx4:$R3),
761 mnemonic#"r\t$R1, $R2, $R3", []>,
762 Requires<[FeatureLoadStoreOnCond]> {
763 let Constraints = "$R1 = $R1src";
764 let DisableEncoding = "$R1src";
768 // Like CondUnaryRRF, but with a fixed CC mask.
769 class FixedCondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
770 RegisterOperand cls2, bits<4> ccmask>
771 : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
772 mnemonic#"\t$R1, $R2", []>,
773 Requires<[FeatureLoadStoreOnCond]> {
774 let Constraints = "$R1 = $R1src";
775 let DisableEncoding = "$R1src";
780 class UnaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
781 RegisterOperand cls, Immediate imm>
782 : InstRI<opcode, (outs cls:$R1), (ins imm:$I2),
783 mnemonic#"\t$R1, $I2",
784 [(set cls:$R1, (operator imm:$I2))]>;
786 class UnaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
787 RegisterOperand cls, Immediate imm>
788 : InstRIL<opcode, (outs cls:$R1), (ins imm:$I2),
789 mnemonic#"\t$R1, $I2",
790 [(set cls:$R1, (operator imm:$I2))]>;
792 class UnaryRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
794 : InstRIL<opcode, (outs cls:$R1), (ins pcrel32:$I2),
795 mnemonic#"\t$R1, $I2",
796 [(set cls:$R1, (operator pcrel32:$I2))]> {
798 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
799 // However, BDXs have two extra operands and are therefore 6 units more
801 let AddedComplexity = 7;
804 class CondUnaryRSY<string mnemonic, bits<16> opcode,
805 SDPatternOperator operator, RegisterOperand cls,
806 bits<5> bytes, AddressingMode mode = bdaddr20only>
807 : InstRSY<opcode, (outs cls:$R1),
808 (ins cls:$R1src, mode:$BD2, cond4:$valid, cond4:$R3),
809 mnemonic#"$R3\t$R1, $BD2",
811 (z_select_ccmask (load bdaddr20only:$BD2), cls:$R1src,
812 cond4:$valid, cond4:$R3))]>,
813 Requires<[FeatureLoadStoreOnCond]> {
814 let Constraints = "$R1 = $R1src";
815 let DisableEncoding = "$R1src";
817 let AccessBytes = bytes;
821 // Like CondUnaryRSY, but used for the raw assembly form. The condition-code
822 // mask is the third operand rather than being part of the mnemonic.
823 class AsmCondUnaryRSY<string mnemonic, bits<16> opcode,
824 RegisterOperand cls, bits<5> bytes,
825 AddressingMode mode = bdaddr20only>
826 : InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2, uimm8zx4:$R3),
827 mnemonic#"\t$R1, $BD2, $R3", []>,
828 Requires<[FeatureLoadStoreOnCond]> {
830 let AccessBytes = bytes;
831 let Constraints = "$R1 = $R1src";
832 let DisableEncoding = "$R1src";
835 // Like CondUnaryRSY, but with a fixed CC mask.
836 class FixedCondUnaryRSY<string mnemonic, bits<16> opcode,
837 RegisterOperand cls, bits<4> ccmask, bits<5> bytes,
838 AddressingMode mode = bdaddr20only>
839 : InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2),
840 mnemonic#"\t$R1, $BD2", []>,
841 Requires<[FeatureLoadStoreOnCond]> {
842 let Constraints = "$R1 = $R1src";
843 let DisableEncoding = "$R1src";
846 let AccessBytes = bytes;
849 class UnaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
850 RegisterOperand cls, bits<5> bytes,
851 AddressingMode mode = bdxaddr12only>
852 : InstRX<opcode, (outs cls:$R1), (ins mode:$XBD2),
853 mnemonic#"\t$R1, $XBD2",
854 [(set cls:$R1, (operator mode:$XBD2))]> {
855 let OpKey = mnemonic ## cls;
858 let AccessBytes = bytes;
861 class UnaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
862 RegisterOperand cls, bits<5> bytes>
863 : InstRXE<opcode, (outs cls:$R1), (ins bdxaddr12only:$XBD2),
864 mnemonic#"\t$R1, $XBD2",
865 [(set cls:$R1, (operator bdxaddr12only:$XBD2))]> {
866 let OpKey = mnemonic ## cls;
869 let AccessBytes = bytes;
872 class UnaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
873 RegisterOperand cls, bits<5> bytes,
874 AddressingMode mode = bdxaddr20only>
875 : InstRXY<opcode, (outs cls:$R1), (ins mode:$XBD2),
876 mnemonic#"\t$R1, $XBD2",
877 [(set cls:$R1, (operator mode:$XBD2))]> {
878 let OpKey = mnemonic ## cls;
881 let AccessBytes = bytes;
884 multiclass UnaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
885 SDPatternOperator operator, RegisterOperand cls,
887 let DispKey = mnemonic ## #cls in {
888 let DispSize = "12" in
889 def "" : UnaryRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>;
890 let DispSize = "20" in
891 def Y : UnaryRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes,
896 class BinaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
897 RegisterOperand cls1, RegisterOperand cls2>
898 : InstRR<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
899 mnemonic#"r\t$R1, $R2",
900 [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
901 let OpKey = mnemonic ## cls1;
903 let Constraints = "$R1 = $R1src";
904 let DisableEncoding = "$R1src";
907 class BinaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
908 RegisterOperand cls1, RegisterOperand cls2>
909 : InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
910 mnemonic#"r\t$R1, $R2",
911 [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
912 let OpKey = mnemonic ## cls1;
914 let Constraints = "$R1 = $R1src";
915 let DisableEncoding = "$R1src";
918 class BinaryRRF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
919 RegisterOperand cls1, RegisterOperand cls2>
920 : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R3, cls2:$R2),
921 mnemonic#"r\t$R1, $R3, $R2",
922 [(set cls1:$R1, (operator cls1:$R3, cls2:$R2))]> {
923 let OpKey = mnemonic ## cls1;
928 class BinaryRRFK<string mnemonic, bits<16> opcode, SDPatternOperator operator,
929 RegisterOperand cls1, RegisterOperand cls2>
930 : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R2, cls2:$R3),
931 mnemonic#"rk\t$R1, $R2, $R3",
932 [(set cls1:$R1, (operator cls1:$R2, cls2:$R3))]> {
936 multiclass BinaryRRAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
937 SDPatternOperator operator, RegisterOperand cls1,
938 RegisterOperand cls2> {
939 let NumOpsKey = mnemonic in {
940 let NumOpsValue = "3" in
941 def K : BinaryRRFK<mnemonic, opcode2, null_frag, cls1, cls2>,
942 Requires<[FeatureDistinctOps]>;
943 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
944 def "" : BinaryRR<mnemonic, opcode1, operator, cls1, cls2>;
948 multiclass BinaryRREAndK<string mnemonic, bits<16> opcode1, bits<16> opcode2,
949 SDPatternOperator operator, RegisterOperand cls1,
950 RegisterOperand cls2> {
951 let NumOpsKey = mnemonic in {
952 let NumOpsValue = "3" in
953 def K : BinaryRRFK<mnemonic, opcode2, null_frag, cls1, cls2>,
954 Requires<[FeatureDistinctOps]>;
955 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
956 def "" : BinaryRRE<mnemonic, opcode1, operator, cls1, cls2>;
960 class BinaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
961 RegisterOperand cls, Immediate imm>
962 : InstRI<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
963 mnemonic#"\t$R1, $I2",
964 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
965 let Constraints = "$R1 = $R1src";
966 let DisableEncoding = "$R1src";
969 class BinaryRIE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
970 RegisterOperand cls, Immediate imm>
971 : InstRIEd<opcode, (outs cls:$R1), (ins cls:$R3, imm:$I2),
972 mnemonic#"\t$R1, $R3, $I2",
973 [(set cls:$R1, (operator cls:$R3, imm:$I2))]>;
975 multiclass BinaryRIAndK<string mnemonic, bits<12> opcode1, bits<16> opcode2,
976 SDPatternOperator operator, RegisterOperand cls,
978 let NumOpsKey = mnemonic in {
979 let NumOpsValue = "3" in
980 def K : BinaryRIE<mnemonic##"k", opcode2, null_frag, cls, imm>,
981 Requires<[FeatureDistinctOps]>;
982 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
983 def "" : BinaryRI<mnemonic, opcode1, operator, cls, imm>;
987 class BinaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
988 RegisterOperand cls, Immediate imm>
989 : InstRIL<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
990 mnemonic#"\t$R1, $I2",
991 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
992 let Constraints = "$R1 = $R1src";
993 let DisableEncoding = "$R1src";
996 class BinaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
997 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
998 AddressingMode mode = bdxaddr12only>
999 : InstRX<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
1000 mnemonic#"\t$R1, $XBD2",
1001 [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
1002 let OpKey = mnemonic ## cls;
1004 let Constraints = "$R1 = $R1src";
1005 let DisableEncoding = "$R1src";
1007 let AccessBytes = bytes;
1010 class BinaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1011 RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
1012 : InstRXE<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr12only:$XBD2),
1013 mnemonic#"\t$R1, $XBD2",
1014 [(set cls:$R1, (operator cls:$R1src,
1015 (load bdxaddr12only:$XBD2)))]> {
1016 let OpKey = mnemonic ## cls;
1018 let Constraints = "$R1 = $R1src";
1019 let DisableEncoding = "$R1src";
1021 let AccessBytes = bytes;
1024 class BinaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1025 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
1026 AddressingMode mode = bdxaddr20only>
1027 : InstRXY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
1028 mnemonic#"\t$R1, $XBD2",
1029 [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
1030 let OpKey = mnemonic ## cls;
1032 let Constraints = "$R1 = $R1src";
1033 let DisableEncoding = "$R1src";
1035 let AccessBytes = bytes;
1038 multiclass BinaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
1039 SDPatternOperator operator, RegisterOperand cls,
1040 SDPatternOperator load, bits<5> bytes> {
1041 let DispKey = mnemonic ## #cls in {
1042 let DispSize = "12" in
1043 def "" : BinaryRX<mnemonic, rxOpcode, operator, cls, load, bytes,
1045 let DispSize = "20" in
1046 def Y : BinaryRXY<mnemonic#"y", rxyOpcode, operator, cls, load, bytes,
1051 class BinarySI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1052 Operand imm, AddressingMode mode = bdaddr12only>
1053 : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
1054 mnemonic#"\t$BD1, $I2",
1055 [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
1060 class BinarySIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1061 Operand imm, AddressingMode mode = bdaddr20only>
1062 : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
1063 mnemonic#"\t$BD1, $I2",
1064 [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
1069 multiclass BinarySIPair<string mnemonic, bits<8> siOpcode,
1070 bits<16> siyOpcode, SDPatternOperator operator,
1072 let DispKey = mnemonic ## #cls in {
1073 let DispSize = "12" in
1074 def "" : BinarySI<mnemonic, siOpcode, operator, imm, bdaddr12pair>;
1075 let DispSize = "20" in
1076 def Y : BinarySIY<mnemonic#"y", siyOpcode, operator, imm, bdaddr20pair>;
1080 class ShiftRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1081 RegisterOperand cls>
1082 : InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, shift12only:$BD2),
1083 mnemonic#"\t$R1, $BD2",
1084 [(set cls:$R1, (operator cls:$R1src, shift12only:$BD2))]> {
1086 let Constraints = "$R1 = $R1src";
1087 let DisableEncoding = "$R1src";
1090 class ShiftRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1091 RegisterOperand cls>
1092 : InstRSY<opcode, (outs cls:$R1), (ins cls:$R3, shift20only:$BD2),
1093 mnemonic#"\t$R1, $R3, $BD2",
1094 [(set cls:$R1, (operator cls:$R3, shift20only:$BD2))]>;
1096 multiclass ShiftRSAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
1097 SDPatternOperator operator, RegisterOperand cls> {
1098 let NumOpsKey = mnemonic in {
1099 let NumOpsValue = "3" in
1100 def K : ShiftRSY<mnemonic##"k", opcode2, null_frag, cls>,
1101 Requires<[FeatureDistinctOps]>;
1102 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
1103 def "" : ShiftRS<mnemonic, opcode1, operator, cls>;
1107 class CompareRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1108 RegisterOperand cls1, RegisterOperand cls2>
1109 : InstRR<opcode, (outs), (ins cls1:$R1, cls2:$R2),
1110 mnemonic#"r\t$R1, $R2",
1111 [(operator cls1:$R1, cls2:$R2)]> {
1112 let OpKey = mnemonic ## cls1;
1117 class CompareRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1118 RegisterOperand cls1, RegisterOperand cls2>
1119 : InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2),
1120 mnemonic#"r\t$R1, $R2",
1121 [(operator cls1:$R1, cls2:$R2)]> {
1122 let OpKey = mnemonic ## cls1;
1127 class CompareRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1128 RegisterOperand cls, Immediate imm>
1129 : InstRI<opcode, (outs), (ins cls:$R1, imm:$I2),
1130 mnemonic#"\t$R1, $I2",
1131 [(operator cls:$R1, imm:$I2)]> {
1135 class CompareRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1136 RegisterOperand cls, Immediate imm>
1137 : InstRIL<opcode, (outs), (ins cls:$R1, imm:$I2),
1138 mnemonic#"\t$R1, $I2",
1139 [(operator cls:$R1, imm:$I2)]> {
1143 class CompareRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1144 RegisterOperand cls, SDPatternOperator load>
1145 : InstRIL<opcode, (outs), (ins cls:$R1, pcrel32:$I2),
1146 mnemonic#"\t$R1, $I2",
1147 [(operator cls:$R1, (load pcrel32:$I2))]> {
1150 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
1151 // However, BDXs have two extra operands and are therefore 6 units more
1153 let AddedComplexity = 7;
1156 class CompareRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1157 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
1158 AddressingMode mode = bdxaddr12only>
1159 : InstRX<opcode, (outs), (ins cls:$R1, mode:$XBD2),
1160 mnemonic#"\t$R1, $XBD2",
1161 [(operator cls:$R1, (load mode:$XBD2))]> {
1162 let OpKey = mnemonic ## cls;
1166 let AccessBytes = bytes;
1169 class CompareRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1170 RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
1171 : InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
1172 mnemonic#"\t$R1, $XBD2",
1173 [(operator cls:$R1, (load bdxaddr12only:$XBD2))]> {
1174 let OpKey = mnemonic ## cls;
1178 let AccessBytes = bytes;
1181 class CompareRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1182 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
1183 AddressingMode mode = bdxaddr20only>
1184 : InstRXY<opcode, (outs), (ins cls:$R1, mode:$XBD2),
1185 mnemonic#"\t$R1, $XBD2",
1186 [(operator cls:$R1, (load mode:$XBD2))]> {
1187 let OpKey = mnemonic ## cls;
1191 let AccessBytes = bytes;
1194 multiclass CompareRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
1195 SDPatternOperator operator, RegisterOperand cls,
1196 SDPatternOperator load, bits<5> bytes> {
1197 let DispKey = mnemonic ## #cls in {
1198 let DispSize = "12" in
1199 def "" : CompareRX<mnemonic, rxOpcode, operator, cls,
1200 load, bytes, bdxaddr12pair>;
1201 let DispSize = "20" in
1202 def Y : CompareRXY<mnemonic#"y", rxyOpcode, operator, cls,
1203 load, bytes, bdxaddr20pair>;
1207 class CompareSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1208 SDPatternOperator load, Immediate imm,
1209 AddressingMode mode = bdaddr12only>
1210 : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
1211 mnemonic#"\t$BD1, $I2",
1212 [(operator (load mode:$BD1), imm:$I2)]> {
1217 class CompareSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1218 SDPatternOperator load, Immediate imm>
1219 : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
1220 mnemonic#"\t$BD1, $I2",
1221 [(operator (load bdaddr12only:$BD1), imm:$I2)]> {
1226 class CompareSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1227 SDPatternOperator load, Immediate imm,
1228 AddressingMode mode = bdaddr20only>
1229 : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
1230 mnemonic#"\t$BD1, $I2",
1231 [(operator (load mode:$BD1), imm:$I2)]> {
1236 multiclass CompareSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
1237 SDPatternOperator operator, SDPatternOperator load,
1239 let DispKey = mnemonic in {
1240 let DispSize = "12" in
1241 def "" : CompareSI<mnemonic, siOpcode, operator, load, imm, bdaddr12pair>;
1242 let DispSize = "20" in
1243 def Y : CompareSIY<mnemonic#"y", siyOpcode, operator, load, imm,
1248 class TernaryRRD<string mnemonic, bits<16> opcode,
1249 SDPatternOperator operator, RegisterOperand cls>
1250 : InstRRD<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, cls:$R2),
1251 mnemonic#"r\t$R1, $R3, $R2",
1252 [(set cls:$R1, (operator cls:$R1src, cls:$R3, cls:$R2))]> {
1253 let OpKey = mnemonic ## cls;
1255 let Constraints = "$R1 = $R1src";
1256 let DisableEncoding = "$R1src";
1259 class TernaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1260 RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
1261 : InstRXF<opcode, (outs cls:$R1),
1262 (ins cls:$R1src, cls:$R3, bdxaddr12only:$XBD2),
1263 mnemonic#"\t$R1, $R3, $XBD2",
1264 [(set cls:$R1, (operator cls:$R1src, cls:$R3,
1265 (load bdxaddr12only:$XBD2)))]> {
1266 let OpKey = mnemonic ## cls;
1268 let Constraints = "$R1 = $R1src";
1269 let DisableEncoding = "$R1src";
1271 let AccessBytes = bytes;
1274 class LoadAndOpRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1275 RegisterOperand cls, AddressingMode mode = bdaddr20only>
1276 : InstRSY<opcode, (outs cls:$R1), (ins cls:$R3, mode:$BD2),
1277 mnemonic#"\t$R1, $R3, $BD2",
1278 [(set cls:$R1, (operator mode:$BD2, cls:$R3))]> {
1283 class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1284 RegisterOperand cls, AddressingMode mode = bdaddr12only>
1285 : InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
1286 mnemonic#"\t$R1, $R3, $BD2",
1287 [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
1288 let Constraints = "$R1 = $R1src";
1289 let DisableEncoding = "$R1src";
1294 class CmpSwapRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1295 RegisterOperand cls, AddressingMode mode = bdaddr20only>
1296 : InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
1297 mnemonic#"\t$R1, $R3, $BD2",
1298 [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
1299 let Constraints = "$R1 = $R1src";
1300 let DisableEncoding = "$R1src";
1305 multiclass CmpSwapRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
1306 SDPatternOperator operator, RegisterOperand cls> {
1307 let DispKey = mnemonic ## #cls in {
1308 let DispSize = "12" in
1309 def "" : CmpSwapRS<mnemonic, rsOpcode, operator, cls, bdaddr12pair>;
1310 let DispSize = "20" in
1311 def Y : CmpSwapRSY<mnemonic#"y", rsyOpcode, operator, cls, bdaddr20pair>;
1315 class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
1316 RegisterOperand cls2>
1317 : InstRIEf<opcode, (outs cls1:$R1),
1318 (ins cls1:$R1src, cls2:$R2, uimm8:$I3, uimm8:$I4, uimm8zx6:$I5),
1319 mnemonic#"\t$R1, $R2, $I3, $I4, $I5", []> {
1320 let Constraints = "$R1 = $R1src";
1321 let DisableEncoding = "$R1src";
1324 class PrefetchRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator>
1325 : InstRXY<opcode, (outs), (ins uimm8zx4:$R1, bdxaddr20only:$XBD2),
1326 mnemonic##"\t$R1, $XBD2",
1327 [(operator uimm8zx4:$R1, bdxaddr20only:$XBD2)]>;
1329 class PrefetchRILPC<string mnemonic, bits<12> opcode,
1330 SDPatternOperator operator>
1331 : InstRIL<opcode, (outs), (ins uimm8zx4:$R1, pcrel32:$I2),
1332 mnemonic##"\t$R1, $I2",
1333 [(operator uimm8zx4:$R1, pcrel32:$I2)]> {
1334 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
1335 // However, BDXs have two extra operands and are therefore 6 units more
1337 let AddedComplexity = 7;
1340 // A floating-point load-and test operation. Create both a normal unary
1341 // operation and one that acts as a comparison against zero.
1342 multiclass LoadAndTestRRE<string mnemonic, bits<16> opcode,
1343 RegisterOperand cls> {
1344 def "" : UnaryRRE<mnemonic, opcode, null_frag, cls, cls>;
1345 let isCodeGenOnly = 1 in
1346 def Compare : CompareRRE<mnemonic, opcode, null_frag, cls, cls>;
1349 //===----------------------------------------------------------------------===//
1350 // Pseudo instructions
1351 //===----------------------------------------------------------------------===//
1353 // Convenience instructions that get lowered to real instructions
1354 // by either SystemZTargetLowering::EmitInstrWithCustomInserter()
1355 // or SystemZInstrInfo::expandPostRAPseudo().
1357 //===----------------------------------------------------------------------===//
1359 class Pseudo<dag outs, dag ins, list<dag> pattern>
1360 : InstSystemZ<0, outs, ins, "", pattern> {
1362 let isCodeGenOnly = 1;
1365 // Like UnaryRI, but expanded after RA depending on the choice of register.
1366 class UnaryRIPseudo<SDPatternOperator operator, RegisterOperand cls,
1368 : Pseudo<(outs cls:$R1), (ins imm:$I2),
1369 [(set cls:$R1, (operator imm:$I2))]>;
1371 // Like UnaryRXY, but expanded after RA depending on the choice of register.
1372 class UnaryRXYPseudo<string key, SDPatternOperator operator,
1373 RegisterOperand cls, bits<5> bytes,
1374 AddressingMode mode = bdxaddr20only>
1375 : Pseudo<(outs cls:$R1), (ins mode:$XBD2),
1376 [(set cls:$R1, (operator mode:$XBD2))]> {
1377 let OpKey = key ## cls;
1380 let Has20BitOffset = 1;
1382 let AccessBytes = bytes;
1385 // Like UnaryRR, but expanded after RA depending on the choice of registers.
1386 class UnaryRRPseudo<string key, SDPatternOperator operator,
1387 RegisterOperand cls1, RegisterOperand cls2>
1388 : Pseudo<(outs cls1:$R1), (ins cls2:$R2),
1389 [(set cls1:$R1, (operator cls2:$R2))]> {
1390 let OpKey = key ## cls1;
1394 // Like BinaryRI, but expanded after RA depending on the choice of register.
1395 class BinaryRIPseudo<SDPatternOperator operator, RegisterOperand cls,
1397 : Pseudo<(outs cls:$R1), (ins cls:$R1src, imm:$I2),
1398 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
1399 let Constraints = "$R1 = $R1src";
1402 // Like BinaryRIE, but expanded after RA depending on the choice of register.
1403 class BinaryRIEPseudo<SDPatternOperator operator, RegisterOperand cls,
1405 : Pseudo<(outs cls:$R1), (ins cls:$R3, imm:$I2),
1406 [(set cls:$R1, (operator cls:$R3, imm:$I2))]>;
1408 // Like BinaryRIAndK, but expanded after RA depending on the choice of register.
1409 multiclass BinaryRIAndKPseudo<string key, SDPatternOperator operator,
1410 RegisterOperand cls, Immediate imm> {
1411 let NumOpsKey = key in {
1412 let NumOpsValue = "3" in
1413 def K : BinaryRIEPseudo<null_frag, cls, imm>,
1414 Requires<[FeatureHighWord, FeatureDistinctOps]>;
1415 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
1416 def "" : BinaryRIPseudo<operator, cls, imm>,
1417 Requires<[FeatureHighWord]>;
1421 // Like CompareRI, but expanded after RA depending on the choice of register.
1422 class CompareRIPseudo<SDPatternOperator operator, RegisterOperand cls,
1424 : Pseudo<(outs), (ins cls:$R1, imm:$I2), [(operator cls:$R1, imm:$I2)]>;
1426 // Like CompareRXY, but expanded after RA depending on the choice of register.
1427 class CompareRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
1428 SDPatternOperator load, bits<5> bytes,
1429 AddressingMode mode = bdxaddr20only>
1430 : Pseudo<(outs), (ins cls:$R1, mode:$XBD2),
1431 [(operator cls:$R1, (load mode:$XBD2))]> {
1433 let Has20BitOffset = 1;
1435 let AccessBytes = bytes;
1438 // Like StoreRXY, but expanded after RA depending on the choice of register.
1439 class StoreRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
1440 bits<5> bytes, AddressingMode mode = bdxaddr20only>
1441 : Pseudo<(outs), (ins cls:$R1, mode:$XBD2),
1442 [(operator cls:$R1, mode:$XBD2)]> {
1444 let Has20BitOffset = 1;
1446 let AccessBytes = bytes;
1449 // Like RotateSelectRIEf, but expanded after RA depending on the choice
1451 class RotateSelectRIEfPseudo<RegisterOperand cls1, RegisterOperand cls2>
1452 : Pseudo<(outs cls1:$R1),
1453 (ins cls1:$R1src, cls2:$R2, uimm8:$I3, uimm8:$I4, uimm8zx6:$I5),
1455 let Constraints = "$R1 = $R1src";
1456 let DisableEncoding = "$R1src";
1459 // Implements "$dst = $cc & (8 >> CC) ? $src1 : $src2", where CC is
1460 // the value of the PSW's 2-bit condition code field.
1461 class SelectWrapper<RegisterOperand cls>
1462 : Pseudo<(outs cls:$dst),
1463 (ins cls:$src1, cls:$src2, uimm8zx4:$valid, uimm8zx4:$cc),
1464 [(set cls:$dst, (z_select_ccmask cls:$src1, cls:$src2,
1465 uimm8zx4:$valid, uimm8zx4:$cc))]> {
1466 let usesCustomInserter = 1;
1467 // Although the instructions used by these nodes do not in themselves
1468 // change CC, the insertion requires new blocks, and CC cannot be live
1474 // Stores $new to $addr if $cc is true ("" case) or false (Inv case).
1475 multiclass CondStores<RegisterOperand cls, SDPatternOperator store,
1476 SDPatternOperator load, AddressingMode mode> {
1477 let Defs = [CC], Uses = [CC], usesCustomInserter = 1 in {
1478 def "" : Pseudo<(outs),
1479 (ins cls:$new, mode:$addr, uimm8zx4:$valid, uimm8zx4:$cc),
1480 [(store (z_select_ccmask cls:$new, (load mode:$addr),
1481 uimm8zx4:$valid, uimm8zx4:$cc),
1483 def Inv : Pseudo<(outs),
1484 (ins cls:$new, mode:$addr, uimm8zx4:$valid, uimm8zx4:$cc),
1485 [(store (z_select_ccmask (load mode:$addr), cls:$new,
1486 uimm8zx4:$valid, uimm8zx4:$cc),
1491 // OPERATOR is ATOMIC_SWAP or an ATOMIC_LOAD_* operation. PAT and OPERAND
1492 // describe the second (non-memory) operand.
1493 class AtomicLoadBinary<SDPatternOperator operator, RegisterOperand cls,
1494 dag pat, DAGOperand operand>
1495 : Pseudo<(outs cls:$dst), (ins bdaddr20only:$ptr, operand:$src2),
1496 [(set cls:$dst, (operator bdaddr20only:$ptr, pat))]> {
1498 let Has20BitOffset = 1;
1501 let usesCustomInserter = 1;
1504 // Specializations of AtomicLoadWBinary.
1505 class AtomicLoadBinaryReg32<SDPatternOperator operator>
1506 : AtomicLoadBinary<operator, GR32, (i32 GR32:$src2), GR32>;
1507 class AtomicLoadBinaryImm32<SDPatternOperator operator, Immediate imm>
1508 : AtomicLoadBinary<operator, GR32, (i32 imm:$src2), imm>;
1509 class AtomicLoadBinaryReg64<SDPatternOperator operator>
1510 : AtomicLoadBinary<operator, GR64, (i64 GR64:$src2), GR64>;
1511 class AtomicLoadBinaryImm64<SDPatternOperator operator, Immediate imm>
1512 : AtomicLoadBinary<operator, GR64, (i64 imm:$src2), imm>;
1514 // OPERATOR is ATOMIC_SWAPW or an ATOMIC_LOADW_* operation. PAT and OPERAND
1515 // describe the second (non-memory) operand.
1516 class AtomicLoadWBinary<SDPatternOperator operator, dag pat,
1518 : Pseudo<(outs GR32:$dst),
1519 (ins bdaddr20only:$ptr, operand:$src2, ADDR32:$bitshift,
1520 ADDR32:$negbitshift, uimm32:$bitsize),
1521 [(set GR32:$dst, (operator bdaddr20only:$ptr, pat, ADDR32:$bitshift,
1522 ADDR32:$negbitshift, uimm32:$bitsize))]> {
1524 let Has20BitOffset = 1;
1527 let usesCustomInserter = 1;
1530 // Specializations of AtomicLoadWBinary.
1531 class AtomicLoadWBinaryReg<SDPatternOperator operator>
1532 : AtomicLoadWBinary<operator, (i32 GR32:$src2), GR32>;
1533 class AtomicLoadWBinaryImm<SDPatternOperator operator, Immediate imm>
1534 : AtomicLoadWBinary<operator, (i32 imm:$src2), imm>;
1536 // Define an instruction that operates on two fixed-length blocks of memory,
1537 // and associated pseudo instructions for operating on blocks of any size.
1538 // The Sequence form uses a straight-line sequence of instructions and
1539 // the Loop form uses a loop of length-256 instructions followed by
1540 // another instruction to handle the excess.
1541 multiclass MemorySS<string mnemonic, bits<8> opcode,
1542 SDPatternOperator sequence, SDPatternOperator loop> {
1543 def "" : InstSS<opcode, (outs), (ins bdladdr12onlylen8:$BDL1,
1545 mnemonic##"\t$BDL1, $BD2", []>;
1546 let usesCustomInserter = 1 in {
1547 def Sequence : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
1549 [(sequence bdaddr12only:$dest, bdaddr12only:$src,
1551 def Loop : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
1552 imm64:$length, GR64:$count256),
1553 [(loop bdaddr12only:$dest, bdaddr12only:$src,
1554 imm64:$length, GR64:$count256)]>;
1558 // Define an instruction that operates on two strings, both terminated
1559 // by the character in R0. The instruction processes a CPU-determinated
1560 // number of bytes at a time and sets CC to 3 if the instruction needs
1561 // to be repeated. Also define a pseudo instruction that represents
1562 // the full loop (the main instruction plus the branch on CC==3).
1563 multiclass StringRRE<string mnemonic, bits<16> opcode,
1564 SDPatternOperator operator> {
1565 def "" : InstRRE<opcode, (outs GR64:$R1, GR64:$R2),
1566 (ins GR64:$R1src, GR64:$R2src),
1567 mnemonic#"\t$R1, $R2", []> {
1568 let Constraints = "$R1 = $R1src, $R2 = $R2src";
1569 let DisableEncoding = "$R1src, $R2src";
1571 let usesCustomInserter = 1 in
1572 def Loop : Pseudo<(outs GR64:$end),
1573 (ins GR64:$start1, GR64:$start2, GR32:$char),
1574 [(set GR64:$end, (operator GR64:$start1, GR64:$start2,
1578 // A pseudo instruction that is a direct alias of a real instruction.
1579 // These aliases are used in cases where a particular register operand is
1580 // fixed or where the same instruction is used with different register sizes.
1581 // The size parameter is the size in bytes of the associated real instruction.
1582 class Alias<int size, dag outs, dag ins, list<dag> pattern>
1583 : InstSystemZ<size, outs, ins, "", pattern> {
1585 let isCodeGenOnly = 1;
1588 // An alias of a BinaryRI, but with different register sizes.
1589 class BinaryAliasRI<SDPatternOperator operator, RegisterOperand cls,
1591 : Alias<4, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
1592 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
1593 let Constraints = "$R1 = $R1src";
1596 // An alias of a BinaryRIL, but with different register sizes.
1597 class BinaryAliasRIL<SDPatternOperator operator, RegisterOperand cls,
1599 : Alias<6, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
1600 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
1601 let Constraints = "$R1 = $R1src";
1604 // An alias of a CompareRI, but with different register sizes.
1605 class CompareAliasRI<SDPatternOperator operator, RegisterOperand cls,
1607 : Alias<4, (outs), (ins cls:$R1, imm:$I2), [(operator cls:$R1, imm:$I2)]> {
1611 // An alias of a RotateSelectRIEf, but with different register sizes.
1612 class RotateSelectAliasRIEf<RegisterOperand cls1, RegisterOperand cls2>
1613 : Alias<6, (outs cls1:$R1),
1614 (ins cls1:$R1src, cls2:$R2, uimm8:$I3, uimm8:$I4, uimm8zx6:$I5), []> {
1615 let Constraints = "$R1 = $R1src";