1 //==- SystemZInstrFormats.td - SystemZ Instruction Formats --*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Basic SystemZ instruction definition
12 //===----------------------------------------------------------------------===//
14 class InstSystemZ<int size, dag outs, dag ins, string asmstr,
15 list<dag> pattern> : Instruction {
16 let Namespace = "SystemZ";
18 dag OutOperandList = outs;
19 dag InOperandList = ins;
21 let Pattern = pattern;
22 let AsmString = asmstr;
24 // Some instructions come in pairs, one having a 12-bit displacement
25 // and the other having a 20-bit displacement. Both instructions in
26 // the pair have the same DispKey and their DispSizes are "12" and "20"
29 string DispSize = "none";
31 // Many register-based <INSN>R instructions have a memory-based <INSN>
32 // counterpart. OpKey uniquely identifies <INSN>, while OpType is
33 // "reg" for <INSN>R and "mem" for <INSN>.
35 string OpType = "none";
37 // True if this instruction is a simple D(X,B) load of a register
38 // (with no sign or zero extension).
39 bit SimpleBDXLoad = 0;
41 // True if this instruction is a simple D(X,B) store of a register
42 // (with no truncation).
43 bit SimpleBDXStore = 0;
45 // True if this instruction has a 20-bit displacement field.
46 bit Has20BitOffset = 0;
48 // True if addresses in this instruction have an index register.
51 // True if this is a 128-bit pseudo instruction that combines two 64-bit
55 // The access size of all memory operands in bytes, or 0 if not known.
56 bits<5> AccessBytes = 0;
58 let TSFlags{0} = SimpleBDXLoad;
59 let TSFlags{1} = SimpleBDXStore;
60 let TSFlags{2} = Has20BitOffset;
61 let TSFlags{3} = HasIndex;
62 let TSFlags{4} = Is128Bit;
63 let TSFlags{9-5} = AccessBytes;
66 //===----------------------------------------------------------------------===//
67 // Mappings between instructions
68 //===----------------------------------------------------------------------===//
70 // Return the version of an instruction that has an unsigned 12-bit
72 def getDisp12Opcode : InstrMapping {
73 let FilterClass = "InstSystemZ";
74 let RowFields = ["DispKey"];
75 let ColFields = ["DispSize"];
77 let ValueCols = [["12"]];
80 // Return the version of an instruction that has a signed 20-bit displacement.
81 def getDisp20Opcode : InstrMapping {
82 let FilterClass = "InstSystemZ";
83 let RowFields = ["DispKey"];
84 let ColFields = ["DispSize"];
86 let ValueCols = [["20"]];
89 def getMemOpcode : InstrMapping {
90 let FilterClass = "InstSystemZ";
91 let RowFields = ["OpKey"];
92 let ColFields = ["OpType"];
94 let ValueCols = [["mem"]];
97 //===----------------------------------------------------------------------===//
98 // Instruction formats
99 //===----------------------------------------------------------------------===//
101 // Formats are specified using operand field declarations of the form:
103 // bits<4> Rn : register input or output for operand n
104 // bits<m> In : immediate value of width m for operand n
105 // bits<4> BDn : address operand n, which has a base and a displacement
106 // bits<m> XBDn : address operand n, which has an index, a base and a
108 // bits<4> Xn : index register for address operand n
109 // bits<4> Mn : mode value for operand n
111 // The operand numbers ("n" in the list above) follow the architecture manual.
112 // Assembly operands sometimes have a different order; in particular, R3 often
113 // is often written between operands 1 and 2.
115 //===----------------------------------------------------------------------===//
117 class InstRI<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
118 : InstSystemZ<4, outs, ins, asmstr, pattern> {
120 field bits<32> SoftFail = 0;
125 let Inst{31-24} = op{11-4};
126 let Inst{23-20} = R1;
127 let Inst{19-16} = op{3-0};
131 class InstRIEb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
132 : InstSystemZ<6, outs, ins, asmstr, pattern> {
134 field bits<48> SoftFail = 0;
141 let Inst{47-40} = op{15-8};
142 let Inst{39-36} = R1;
143 let Inst{35-32} = R2;
144 let Inst{31-16} = RI4;
145 let Inst{15-12} = M3;
147 let Inst{7-0} = op{7-0};
150 class InstRIEc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
151 : InstSystemZ<6, outs, ins, asmstr, pattern> {
153 field bits<48> SoftFail = 0;
160 let Inst{47-40} = op{15-8};
161 let Inst{39-36} = R1;
162 let Inst{35-32} = M3;
163 let Inst{31-16} = RI4;
165 let Inst{7-0} = op{7-0};
168 class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
169 : InstSystemZ<6, outs, ins, asmstr, pattern> {
171 field bits<48> SoftFail = 0;
179 let Inst{47-40} = op{15-8};
180 let Inst{39-36} = R1;
181 let Inst{35-32} = R2;
182 let Inst{31-24} = I3;
183 let Inst{23-16} = I4;
185 let Inst{7-0} = op{7-0};
188 class InstRIL<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
189 : InstSystemZ<6, outs, ins, asmstr, pattern> {
191 field bits<48> SoftFail = 0;
196 let Inst{47-40} = op{11-4};
197 let Inst{39-36} = R1;
198 let Inst{35-32} = op{3-0};
202 class InstRR<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
203 : InstSystemZ<2, outs, ins, asmstr, pattern> {
205 field bits<16> SoftFail = 0;
215 class InstRRD<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
216 : InstSystemZ<4, outs, ins, asmstr, pattern> {
218 field bits<32> SoftFail = 0;
224 let Inst{31-16} = op;
225 let Inst{15-12} = R1;
231 class InstRRE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
232 : InstSystemZ<4, outs, ins, asmstr, pattern> {
234 field bits<32> SoftFail = 0;
239 let Inst{31-16} = op;
245 class InstRRF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
246 : InstSystemZ<4, outs, ins, asmstr, pattern> {
248 field bits<32> SoftFail = 0;
254 let Inst{31-16} = op;
255 let Inst{15-12} = R3;
261 class InstRX<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
262 : InstSystemZ<4, outs, ins, asmstr, pattern> {
264 field bits<32> SoftFail = 0;
269 let Inst{31-24} = op;
270 let Inst{23-20} = R1;
271 let Inst{19-0} = XBD2;
276 class InstRXE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
277 : InstSystemZ<6, outs, ins, asmstr, pattern> {
279 field bits<48> SoftFail = 0;
284 let Inst{47-40} = op{15-8};
285 let Inst{39-36} = R1;
286 let Inst{35-16} = XBD2;
288 let Inst{7-0} = op{7-0};
293 class InstRXF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
294 : InstSystemZ<6, outs, ins, asmstr, pattern> {
296 field bits<48> SoftFail = 0;
302 let Inst{47-40} = op{15-8};
303 let Inst{39-36} = R3;
304 let Inst{35-16} = XBD2;
305 let Inst{15-12} = R1;
307 let Inst{7-0} = op{7-0};
312 class InstRXY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
313 : InstSystemZ<6, outs, ins, asmstr, pattern> {
315 field bits<48> SoftFail = 0;
320 let Inst{47-40} = op{15-8};
321 let Inst{39-36} = R1;
322 let Inst{35-8} = XBD2;
323 let Inst{7-0} = op{7-0};
325 let Has20BitOffset = 1;
329 class InstRS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
330 : InstSystemZ<4, outs, ins, asmstr, pattern> {
332 field bits<32> SoftFail = 0;
338 let Inst{31-24} = op;
339 let Inst{23-20} = R1;
340 let Inst{19-16} = R3;
341 let Inst{15-0} = BD2;
344 class InstRSY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
345 : InstSystemZ<6, outs, ins, asmstr, pattern> {
347 field bits<48> SoftFail = 0;
353 let Inst{47-40} = op{15-8};
354 let Inst{39-36} = R1;
355 let Inst{35-32} = R3;
356 let Inst{31-8} = BD2;
357 let Inst{7-0} = op{7-0};
359 let Has20BitOffset = 1;
362 class InstSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
363 : InstSystemZ<4, outs, ins, asmstr, pattern> {
365 field bits<32> SoftFail = 0;
370 let Inst{31-24} = op;
371 let Inst{23-16} = I2;
372 let Inst{15-0} = BD1;
375 class InstSIL<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
376 : InstSystemZ<6, outs, ins, asmstr, pattern> {
378 field bits<48> SoftFail = 0;
383 let Inst{47-32} = op;
384 let Inst{31-16} = BD1;
388 class InstSIY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
389 : InstSystemZ<6, outs, ins, asmstr, pattern> {
391 field bits<48> SoftFail = 0;
396 let Inst{47-40} = op{15-8};
397 let Inst{39-32} = I2;
398 let Inst{31-8} = BD1;
399 let Inst{7-0} = op{7-0};
401 let Has20BitOffset = 1;
404 class InstSS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
405 : InstSystemZ<6, outs, ins, asmstr, pattern> {
407 field bits<48> SoftFail = 0;
412 let Inst{47-40} = op;
413 let Inst{39-16} = BDL1;
414 let Inst{15-0} = BD2;
417 //===----------------------------------------------------------------------===//
418 // Instruction definitions with semantics
419 //===----------------------------------------------------------------------===//
421 // These classes have the form <Category><Format>, where <Format> is one
422 // of the formats defined above and where <Category> describes the inputs
423 // and outputs. <Category> can be one of:
426 // One register output operand and no input operands.
429 // One register or immediate input operand and one address input operand.
430 // The instruction stores the first operand to the address.
432 // This category is used for both pure and truncating stores.
435 // One address input operand and two explicit output operands.
436 // The instruction loads a range of registers from the address,
437 // with the explicit operands giving the first and last register
438 // to load. Other loaded registers are added as implicit definitions.
441 // Two explicit input register operands and an address operand.
442 // The instruction stores a range of registers to the address,
443 // with the explicit operands giving the first and last register
444 // to store. Other stored registers are added as implicit uses.
447 // One register output operand and one input operand. The input
448 // operand may be a register, immediate or memory.
451 // One register output operand and two input operands. The first
452 // input operand is always a register and he second may be a register,
453 // immediate or memory.
456 // One register output operand and two input operands. The first
457 // input operand is a register and the second has the same form as
458 // an address (although it isn't actually used to address memory).
461 // Two input operands. The first operand is always a register,
462 // the second may be a register, immediate or memory.
465 // One register output operand and three register input operands.
468 // One output operand and three input operands. The first two
469 // operands are registers and the third is an address. The instruction
470 // both reads from and writes to the address.
473 // One output operand and five input operands. The first two operands
474 // are registers and the other three are immediates.
476 // The format determines which input operands are tied to output operands,
477 // and also determines the shape of any address operand.
479 // Multiclasses of the form <Category><Format>Pair define two instructions,
480 // one with <Category><Format> and one with <Category><Format>Y. The name
481 // of the first instruction has no suffix, the name of the second has
484 //===----------------------------------------------------------------------===//
486 class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
488 : InstRRE<opcode, (outs cls:$R1), (ins),
490 [(set cls:$R1, src)]> {
494 class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
495 : InstRSY<opcode, (outs cls:$R1, cls:$R3), (ins bdaddr20only:$BD2),
496 mnemonic#"\t$R1, $R3, $BD2", []> {
500 class StoreRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
502 : InstRIL<opcode, (outs), (ins cls:$R1, pcrel32:$I2),
503 mnemonic#"\t$R1, $I2",
504 [(operator cls:$R1, pcrel32:$I2)]> {
506 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
507 // However, BDXs have two extra operands and are therefore 6 units more
509 let AddedComplexity = 7;
512 class StoreRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
513 RegisterOperand cls, bits<5> bytes,
514 AddressingMode mode = bdxaddr12only>
515 : InstRX<opcode, (outs), (ins cls:$R1, mode:$XBD2),
516 mnemonic#"\t$R1, $XBD2",
517 [(operator cls:$R1, mode:$XBD2)]> {
518 let OpKey = mnemonic ## cls;
521 let AccessBytes = bytes;
524 class StoreRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
525 RegisterOperand cls, bits<5> bytes,
526 AddressingMode mode = bdxaddr20only>
527 : InstRXY<opcode, (outs), (ins cls:$R1, mode:$XBD2),
528 mnemonic#"\t$R1, $XBD2",
529 [(operator cls:$R1, mode:$XBD2)]> {
530 let OpKey = mnemonic ## cls;
533 let AccessBytes = bytes;
536 multiclass StoreRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
537 SDPatternOperator operator, RegisterOperand cls,
539 let DispKey = mnemonic ## #cls in {
540 let DispSize = "12" in
541 def "" : StoreRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>;
542 let DispSize = "20" in
543 def Y : StoreRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes,
548 class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
549 : InstRSY<opcode, (outs), (ins cls:$R1, cls:$R3, bdaddr20only:$BD2),
550 mnemonic#"\t$R1, $R3, $BD2", []> {
554 class StoreSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
555 Immediate imm, AddressingMode mode = bdaddr12only>
556 : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
557 mnemonic#"\t$BD1, $I2",
558 [(operator imm:$I2, mode:$BD1)]> {
562 class StoreSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
563 Immediate imm, AddressingMode mode = bdaddr20only>
564 : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
565 mnemonic#"\t$BD1, $I2",
566 [(operator imm:$I2, mode:$BD1)]> {
570 class StoreSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
572 : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
573 mnemonic#"\t$BD1, $I2",
574 [(operator imm:$I2, bdaddr12only:$BD1)]> {
578 multiclass StoreSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
579 SDPatternOperator operator, Immediate imm> {
580 let DispKey = mnemonic in {
581 let DispSize = "12" in
582 def "" : StoreSI<mnemonic, siOpcode, operator, imm, bdaddr12pair>;
583 let DispSize = "20" in
584 def Y : StoreSIY<mnemonic#"y", siyOpcode, operator, imm, bdaddr20pair>;
588 class UnaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
589 RegisterOperand cls1, RegisterOperand cls2>
590 : InstRR<opcode, (outs cls1:$R1), (ins cls2:$R2),
591 mnemonic#"r\t$R1, $R2",
592 [(set cls1:$R1, (operator cls2:$R2))]> {
593 let OpKey = mnemonic ## cls1;
597 class UnaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
598 RegisterOperand cls1, RegisterOperand cls2>
599 : InstRRE<opcode, (outs cls1:$R1), (ins cls2:$R2),
600 mnemonic#"r\t$R1, $R2",
601 [(set cls1:$R1, (operator cls2:$R2))]> {
602 let OpKey = mnemonic ## cls1;
606 class UnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
607 RegisterOperand cls2>
608 : InstRRF<opcode, (outs cls1:$R1), (ins uimm8zx4:$R3, cls2:$R2),
609 mnemonic#"r\t$R1, $R3, $R2", []> {
610 let OpKey = mnemonic ## cls1;
614 class UnaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
615 RegisterOperand cls, Immediate imm>
616 : InstRI<opcode, (outs cls:$R1), (ins imm:$I2),
617 mnemonic#"\t$R1, $I2",
618 [(set cls:$R1, (operator imm:$I2))]>;
620 class UnaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
621 RegisterOperand cls, Immediate imm>
622 : InstRIL<opcode, (outs cls:$R1), (ins imm:$I2),
623 mnemonic#"\t$R1, $I2",
624 [(set cls:$R1, (operator imm:$I2))]>;
626 class UnaryRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
628 : InstRIL<opcode, (outs cls:$R1), (ins pcrel32:$I2),
629 mnemonic#"\t$R1, $I2",
630 [(set cls:$R1, (operator pcrel32:$I2))]> {
632 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
633 // However, BDXs have two extra operands and are therefore 6 units more
635 let AddedComplexity = 7;
638 class UnaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
639 RegisterOperand cls, bits<5> bytes,
640 AddressingMode mode = bdxaddr12only>
641 : InstRX<opcode, (outs cls:$R1), (ins mode:$XBD2),
642 mnemonic#"\t$R1, $XBD2",
643 [(set cls:$R1, (operator mode:$XBD2))]> {
644 let OpKey = mnemonic ## cls;
647 let AccessBytes = bytes;
650 class UnaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
651 RegisterOperand cls, bits<5> bytes>
652 : InstRXE<opcode, (outs cls:$R1), (ins bdxaddr12only:$XBD2),
653 mnemonic#"\t$R1, $XBD2",
654 [(set cls:$R1, (operator bdxaddr12only:$XBD2))]> {
655 let OpKey = mnemonic ## cls;
658 let AccessBytes = bytes;
661 class UnaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
662 RegisterOperand cls, bits<5> bytes,
663 AddressingMode mode = bdxaddr20only>
664 : InstRXY<opcode, (outs cls:$R1), (ins mode:$XBD2),
665 mnemonic#"\t$R1, $XBD2",
666 [(set cls:$R1, (operator mode:$XBD2))]> {
667 let OpKey = mnemonic ## cls;
670 let AccessBytes = bytes;
673 multiclass UnaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
674 SDPatternOperator operator, RegisterOperand cls,
676 let DispKey = mnemonic ## #cls in {
677 let DispSize = "12" in
678 def "" : UnaryRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>;
679 let DispSize = "20" in
680 def Y : UnaryRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes,
685 class BinaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
686 RegisterOperand cls1, RegisterOperand cls2>
687 : InstRR<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
688 mnemonic#"r\t$R1, $R2",
689 [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
690 let OpKey = mnemonic ## cls1;
692 let Constraints = "$R1 = $R1src";
693 let DisableEncoding = "$R1src";
696 class BinaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
697 RegisterOperand cls1, RegisterOperand cls2>
698 : InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
699 mnemonic#"r\t$R1, $R2",
700 [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
701 let OpKey = mnemonic ## cls1;
703 let Constraints = "$R1 = $R1src";
704 let DisableEncoding = "$R1src";
707 class BinaryRRF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
708 RegisterOperand cls1, RegisterOperand cls2>
709 : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R3, cls2:$R2),
710 mnemonic#"r\t$R1, $R3, $R2",
711 [(set cls1:$R1, (operator cls1:$R3, cls2:$R2))]> {
712 let OpKey = mnemonic ## cls1;
716 class BinaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
717 RegisterOperand cls, Immediate imm>
718 : InstRI<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
719 mnemonic#"\t$R1, $I2",
720 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
721 let Constraints = "$R1 = $R1src";
722 let DisableEncoding = "$R1src";
725 class BinaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
726 RegisterOperand cls, Immediate imm>
727 : InstRIL<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
728 mnemonic#"\t$R1, $I2",
729 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
730 let Constraints = "$R1 = $R1src";
731 let DisableEncoding = "$R1src";
734 class BinaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
735 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
736 AddressingMode mode = bdxaddr12only>
737 : InstRX<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
738 mnemonic#"\t$R1, $XBD2",
739 [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
740 let OpKey = mnemonic ## cls;
742 let Constraints = "$R1 = $R1src";
743 let DisableEncoding = "$R1src";
745 let AccessBytes = bytes;
748 class BinaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
749 RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
750 : InstRXE<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr12only:$XBD2),
751 mnemonic#"\t$R1, $XBD2",
752 [(set cls:$R1, (operator cls:$R1src,
753 (load bdxaddr12only:$XBD2)))]> {
754 let OpKey = mnemonic ## cls;
756 let Constraints = "$R1 = $R1src";
757 let DisableEncoding = "$R1src";
759 let AccessBytes = bytes;
762 class BinaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
763 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
764 AddressingMode mode = bdxaddr20only>
765 : InstRXY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
766 mnemonic#"\t$R1, $XBD2",
767 [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
768 let OpKey = mnemonic ## cls;
770 let Constraints = "$R1 = $R1src";
771 let DisableEncoding = "$R1src";
773 let AccessBytes = bytes;
776 multiclass BinaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
777 SDPatternOperator operator, RegisterOperand cls,
778 SDPatternOperator load, bits<5> bytes> {
779 let DispKey = mnemonic ## #cls in {
780 let DispSize = "12" in
781 def "" : BinaryRX<mnemonic, rxOpcode, operator, cls, load, bytes,
783 let DispSize = "20" in
784 def Y : BinaryRXY<mnemonic#"y", rxyOpcode, operator, cls, load, bytes,
789 class BinarySI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
790 Operand imm, AddressingMode mode = bdaddr12only>
791 : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
792 mnemonic#"\t$BD1, $I2",
793 [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
798 class BinarySIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
799 Operand imm, AddressingMode mode = bdaddr20only>
800 : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
801 mnemonic#"\t$BD1, $I2",
802 [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
807 multiclass BinarySIPair<string mnemonic, bits<8> siOpcode,
808 bits<16> siyOpcode, SDPatternOperator operator,
810 let DispKey = mnemonic ## #cls in {
811 let DispSize = "12" in
812 def "" : BinarySI<mnemonic, siOpcode, operator, imm, bdaddr12pair>;
813 let DispSize = "20" in
814 def Y : BinarySIY<mnemonic#"y", siyOpcode, operator, imm, bdaddr20pair>;
818 class ShiftRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
819 RegisterOperand cls, AddressingMode mode>
820 : InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2),
821 mnemonic#"\t$R1, $BD2",
822 [(set cls:$R1, (operator cls:$R1src, mode:$BD2))]> {
824 let Constraints = "$R1 = $R1src";
825 let DisableEncoding = "$R1src";
828 class ShiftRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
829 RegisterOperand cls, AddressingMode mode>
830 : InstRSY<opcode, (outs cls:$R1), (ins cls:$R3, mode:$BD2),
831 mnemonic#"\t$R1, $R3, $BD2",
832 [(set cls:$R1, (operator cls:$R3, mode:$BD2))]>;
834 class CompareRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
835 RegisterOperand cls1, RegisterOperand cls2>
836 : InstRR<opcode, (outs), (ins cls1:$R1, cls2:$R2),
837 mnemonic#"r\t$R1, $R2",
838 [(operator cls1:$R1, cls2:$R2)]> {
839 let OpKey = mnemonic ## cls1;
843 class CompareRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
844 RegisterOperand cls1, RegisterOperand cls2>
845 : InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2),
846 mnemonic#"r\t$R1, $R2",
847 [(operator cls1:$R1, cls2:$R2)]> {
848 let OpKey = mnemonic ## cls1;
852 class CompareRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
853 RegisterOperand cls, Immediate imm>
854 : InstRI<opcode, (outs), (ins cls:$R1, imm:$I2),
855 mnemonic#"\t$R1, $I2",
856 [(operator cls:$R1, imm:$I2)]>;
858 class CompareRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
859 RegisterOperand cls, Immediate imm>
860 : InstRIL<opcode, (outs), (ins cls:$R1, imm:$I2),
861 mnemonic#"\t$R1, $I2",
862 [(operator cls:$R1, imm:$I2)]>;
864 class CompareRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
865 RegisterOperand cls, SDPatternOperator load>
866 : InstRIL<opcode, (outs), (ins cls:$R1, pcrel32:$I2),
867 mnemonic#"\t$R1, $I2",
868 [(operator cls:$R1, (load pcrel32:$I2))]> {
870 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
871 // However, BDXs have two extra operands and are therefore 6 units more
873 let AddedComplexity = 7;
876 class CompareRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
877 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
878 AddressingMode mode = bdxaddr12only>
879 : InstRX<opcode, (outs), (ins cls:$R1, mode:$XBD2),
880 mnemonic#"\t$R1, $XBD2",
881 [(operator cls:$R1, (load mode:$XBD2))]> {
882 let OpKey = mnemonic ## cls;
885 let AccessBytes = bytes;
888 class CompareRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
889 RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
890 : InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
891 mnemonic#"\t$R1, $XBD2",
892 [(operator cls:$R1, (load bdxaddr12only:$XBD2))]> {
893 let OpKey = mnemonic ## cls;
896 let AccessBytes = bytes;
899 class CompareRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
900 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
901 AddressingMode mode = bdxaddr20only>
902 : InstRXY<opcode, (outs), (ins cls:$R1, mode:$XBD2),
903 mnemonic#"\t$R1, $XBD2",
904 [(operator cls:$R1, (load mode:$XBD2))]> {
905 let OpKey = mnemonic ## cls;
908 let AccessBytes = bytes;
911 multiclass CompareRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
912 SDPatternOperator operator, RegisterOperand cls,
913 SDPatternOperator load, bits<5> bytes> {
914 let DispKey = mnemonic ## #cls in {
915 let DispSize = "12" in
916 def "" : CompareRX<mnemonic, rxOpcode, operator, cls,
917 load, bytes, bdxaddr12pair>;
918 let DispSize = "20" in
919 def Y : CompareRXY<mnemonic#"y", rxyOpcode, operator, cls,
920 load, bytes, bdxaddr20pair>;
924 class CompareSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
925 SDPatternOperator load, Immediate imm,
926 AddressingMode mode = bdaddr12only>
927 : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
928 mnemonic#"\t$BD1, $I2",
929 [(operator (load mode:$BD1), imm:$I2)]> {
933 class CompareSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
934 SDPatternOperator load, Immediate imm>
935 : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
936 mnemonic#"\t$BD1, $I2",
937 [(operator (load bdaddr12only:$BD1), imm:$I2)]> {
941 class CompareSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
942 SDPatternOperator load, Immediate imm,
943 AddressingMode mode = bdaddr20only>
944 : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
945 mnemonic#"\t$BD1, $I2",
946 [(operator (load mode:$BD1), imm:$I2)]> {
950 multiclass CompareSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
951 SDPatternOperator operator, SDPatternOperator load,
953 let DispKey = mnemonic in {
954 let DispSize = "12" in
955 def "" : CompareSI<mnemonic, siOpcode, operator, load, imm, bdaddr12pair>;
956 let DispSize = "20" in
957 def Y : CompareSIY<mnemonic#"y", siyOpcode, operator, load, imm,
962 class TernaryRRD<string mnemonic, bits<16> opcode,
963 SDPatternOperator operator, RegisterOperand cls>
964 : InstRRD<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, cls:$R2),
965 mnemonic#"r\t$R1, $R3, $R2",
966 [(set cls:$R1, (operator cls:$R1src, cls:$R3, cls:$R2))]> {
967 let OpKey = mnemonic ## cls;
969 let Constraints = "$R1 = $R1src";
970 let DisableEncoding = "$R1src";
973 class TernaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
974 RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
975 : InstRXF<opcode, (outs cls:$R1),
976 (ins cls:$R1src, cls:$R3, bdxaddr12only:$XBD2),
977 mnemonic#"\t$R1, $R3, $XBD2",
978 [(set cls:$R1, (operator cls:$R1src, cls:$R3,
979 (load bdxaddr12only:$XBD2)))]> {
980 let OpKey = mnemonic ## cls;
982 let Constraints = "$R1 = $R1src";
983 let DisableEncoding = "$R1src";
985 let AccessBytes = bytes;
988 class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
989 RegisterOperand cls, AddressingMode mode = bdaddr12only>
990 : InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
991 mnemonic#"\t$R1, $R3, $BD2",
992 [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
993 let Constraints = "$R1 = $R1src";
994 let DisableEncoding = "$R1src";
999 class CmpSwapRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1000 RegisterOperand cls, AddressingMode mode = bdaddr20only>
1001 : InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
1002 mnemonic#"\t$R1, $R3, $BD2",
1003 [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
1004 let Constraints = "$R1 = $R1src";
1005 let DisableEncoding = "$R1src";
1010 multiclass CmpSwapRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
1011 SDPatternOperator operator, RegisterOperand cls> {
1012 let DispKey = mnemonic ## #cls in {
1013 let DispSize = "12" in
1014 def "" : CmpSwapRS<mnemonic, rsOpcode, operator, cls, bdaddr12pair>;
1015 let DispSize = "20" in
1016 def Y : CmpSwapRSY<mnemonic#"y", rsyOpcode, operator, cls, bdaddr20pair>;
1020 class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
1021 RegisterOperand cls2>
1022 : InstRIEf<opcode, (outs cls1:$R1),
1023 (ins cls1:$R1src, cls2:$R2,
1024 uimm8zx6:$I3, uimm8zx6:$I4, uimm8zx6:$I5),
1025 mnemonic#"\t$R1, $R2, $I3, $I4, $I5", []> {
1026 let Constraints = "$R1 = $R1src";
1027 let DisableEncoding = "$R1src";
1030 //===----------------------------------------------------------------------===//
1031 // Pseudo instructions
1032 //===----------------------------------------------------------------------===//
1034 // Convenience instructions that get lowered to real instructions
1035 // by either SystemZTargetLowering::EmitInstrWithCustomInserter()
1036 // or SystemZInstrInfo::expandPostRAPseudo().
1038 //===----------------------------------------------------------------------===//
1040 class Pseudo<dag outs, dag ins, list<dag> pattern>
1041 : InstSystemZ<0, outs, ins, "", pattern> {
1043 let isCodeGenOnly = 1;
1046 // Implements "$dst = $cc & (8 >> CC) ? $src1 : $src2", where CC is
1047 // the value of the PSW's 2-bit condition code field.
1048 class SelectWrapper<RegisterOperand cls>
1049 : Pseudo<(outs cls:$dst), (ins cls:$src1, cls:$src2, i8imm:$cc),
1050 [(set cls:$dst, (z_select_ccmask cls:$src1, cls:$src2, imm:$cc))]> {
1051 let usesCustomInserter = 1;
1052 // Although the instructions used by these nodes do not in themselves
1053 // change CC, the insertion requires new blocks, and CC cannot be live
1059 // Stores $new to $addr if $cc is true ("" case) or false (Inv case).
1060 multiclass CondStores<RegisterOperand cls, SDPatternOperator store,
1061 SDPatternOperator load, AddressingMode mode> {
1062 let Defs = [CC], Uses = [CC], usesCustomInserter = 1 in {
1063 def "" : Pseudo<(outs), (ins mode:$addr, cls:$new, i8imm:$cc),
1064 [(store (z_select_ccmask cls:$new, (load mode:$addr),
1065 imm:$cc), mode:$addr)]>;
1066 def Inv : Pseudo<(outs), (ins mode:$addr, cls:$new, i8imm:$cc),
1067 [(store (z_select_ccmask (load mode:$addr), cls:$new,
1068 imm:$cc), mode:$addr)]>;
1072 // OPERATOR is ATOMIC_SWAP or an ATOMIC_LOAD_* operation. PAT and OPERAND
1073 // describe the second (non-memory) operand.
1074 class AtomicLoadBinary<SDPatternOperator operator, RegisterOperand cls,
1075 dag pat, DAGOperand operand>
1076 : Pseudo<(outs cls:$dst), (ins bdaddr20only:$ptr, operand:$src2),
1077 [(set cls:$dst, (operator bdaddr20only:$ptr, pat))]> {
1079 let Has20BitOffset = 1;
1082 let usesCustomInserter = 1;
1085 // Specializations of AtomicLoadWBinary.
1086 class AtomicLoadBinaryReg32<SDPatternOperator operator>
1087 : AtomicLoadBinary<operator, GR32, (i32 GR32:$src2), GR32>;
1088 class AtomicLoadBinaryImm32<SDPatternOperator operator, Immediate imm>
1089 : AtomicLoadBinary<operator, GR32, (i32 imm:$src2), imm>;
1090 class AtomicLoadBinaryReg64<SDPatternOperator operator>
1091 : AtomicLoadBinary<operator, GR64, (i64 GR64:$src2), GR64>;
1092 class AtomicLoadBinaryImm64<SDPatternOperator operator, Immediate imm>
1093 : AtomicLoadBinary<operator, GR64, (i64 imm:$src2), imm>;
1095 // OPERATOR is ATOMIC_SWAPW or an ATOMIC_LOADW_* operation. PAT and OPERAND
1096 // describe the second (non-memory) operand.
1097 class AtomicLoadWBinary<SDPatternOperator operator, dag pat,
1099 : Pseudo<(outs GR32:$dst),
1100 (ins bdaddr20only:$ptr, operand:$src2, ADDR32:$bitshift,
1101 ADDR32:$negbitshift, uimm32:$bitsize),
1102 [(set GR32:$dst, (operator bdaddr20only:$ptr, pat, ADDR32:$bitshift,
1103 ADDR32:$negbitshift, uimm32:$bitsize))]> {
1105 let Has20BitOffset = 1;
1108 let usesCustomInserter = 1;
1111 // Specializations of AtomicLoadWBinary.
1112 class AtomicLoadWBinaryReg<SDPatternOperator operator>
1113 : AtomicLoadWBinary<operator, (i32 GR32:$src2), GR32>;
1114 class AtomicLoadWBinaryImm<SDPatternOperator operator, Immediate imm>
1115 : AtomicLoadWBinary<operator, (i32 imm:$src2), imm>;