1 //==- SystemZInstrFormats.td - SystemZ Instruction Formats --*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Basic SystemZ instruction definition
12 //===----------------------------------------------------------------------===//
14 class InstSystemZ<int size, dag outs, dag ins, string asmstr,
15 list<dag> pattern> : Instruction {
16 let Namespace = "SystemZ";
18 dag OutOperandList = outs;
19 dag InOperandList = ins;
21 let Pattern = pattern;
22 let AsmString = asmstr;
24 // Some instructions come in pairs, one having a 12-bit displacement
25 // and the other having a 20-bit displacement. Both instructions in
26 // the pair have the same DispKey and their DispSizes are "12" and "20"
29 string DispSize = "none";
31 // Many register-based <INSN>R instructions have a memory-based <INSN>
32 // counterpart. OpKey uniquely identifies <INSN>, while OpType is
33 // "reg" for <INSN>R and "mem" for <INSN>.
35 string OpType = "none";
37 // Many distinct-operands instructions have older 2-operand equivalents.
38 // NumOpsKey uniquely identifies one of these 2-operand and 3-operand pairs,
39 // with NumOpsValue being "2" or "3" as appropriate.
40 string NumOpsKey = "";
41 string NumOpsValue = "none";
43 // True if this instruction is a simple D(X,B) load of a register
44 // (with no sign or zero extension).
45 bit SimpleBDXLoad = 0;
47 // True if this instruction is a simple D(X,B) store of a register
48 // (with no truncation).
49 bit SimpleBDXStore = 0;
51 // True if this instruction has a 20-bit displacement field.
52 bit Has20BitOffset = 0;
54 // True if addresses in this instruction have an index register.
57 // True if this is a 128-bit pseudo instruction that combines two 64-bit
61 // The access size of all memory operands in bytes, or 0 if not known.
62 bits<5> AccessBytes = 0;
64 // If the instruction sets CC to a useful value, this gives the mask
65 // of all possible CC results. The mask has the same form as
69 // The subset of CCValues that have the same meaning as they would after
70 // a comparison of the first operand against zero.
71 bits<4> CompareZeroCCMask = 0;
73 // True if the instruction is conditional and if the CC mask operand
74 // comes first (as for BRC, etc.).
77 // Similar, but true if the CC mask operand comes last (as for LOC, etc.).
80 // True if the instruction is the "logical" rather than "arithmetic" form,
81 // in cases where a distinction exists.
84 let TSFlags{0} = SimpleBDXLoad;
85 let TSFlags{1} = SimpleBDXStore;
86 let TSFlags{2} = Has20BitOffset;
87 let TSFlags{3} = HasIndex;
88 let TSFlags{4} = Is128Bit;
89 let TSFlags{9-5} = AccessBytes;
90 let TSFlags{13-10} = CCValues;
91 let TSFlags{17-14} = CompareZeroCCMask;
92 let TSFlags{18} = CCMaskFirst;
93 let TSFlags{19} = CCMaskLast;
94 let TSFlags{20} = IsLogical;
97 //===----------------------------------------------------------------------===//
98 // Mappings between instructions
99 //===----------------------------------------------------------------------===//
101 // Return the version of an instruction that has an unsigned 12-bit
103 def getDisp12Opcode : InstrMapping {
104 let FilterClass = "InstSystemZ";
105 let RowFields = ["DispKey"];
106 let ColFields = ["DispSize"];
108 let ValueCols = [["12"]];
111 // Return the version of an instruction that has a signed 20-bit displacement.
112 def getDisp20Opcode : InstrMapping {
113 let FilterClass = "InstSystemZ";
114 let RowFields = ["DispKey"];
115 let ColFields = ["DispSize"];
117 let ValueCols = [["20"]];
120 // Return the memory form of a register instruction.
121 def getMemOpcode : InstrMapping {
122 let FilterClass = "InstSystemZ";
123 let RowFields = ["OpKey"];
124 let ColFields = ["OpType"];
125 let KeyCol = ["reg"];
126 let ValueCols = [["mem"]];
129 // Return the 3-operand form of a 2-operand instruction.
130 def getThreeOperandOpcode : InstrMapping {
131 let FilterClass = "InstSystemZ";
132 let RowFields = ["NumOpsKey"];
133 let ColFields = ["NumOpsValue"];
135 let ValueCols = [["3"]];
138 //===----------------------------------------------------------------------===//
139 // Instruction formats
140 //===----------------------------------------------------------------------===//
142 // Formats are specified using operand field declarations of the form:
144 // bits<4> Rn : register input or output for operand n
145 // bits<5> Vn : vector register input or output for operand n
146 // bits<m> In : immediate value of width m for operand n
147 // bits<4> BDn : address operand n, which has a base and a displacement
148 // bits<m> XBDn : address operand n, which has an index, a base and a
150 // bits<m> VBDn : address operand n, which has a vector index, a base and a
152 // bits<4> Xn : index register for address operand n
153 // bits<4> Mn : mode value for operand n
155 // The operand numbers ("n" in the list above) follow the architecture manual.
156 // Assembly operands sometimes have a different order; in particular, R3 often
157 // is often written between operands 1 and 2.
159 //===----------------------------------------------------------------------===//
161 class InstRI<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
162 : InstSystemZ<4, outs, ins, asmstr, pattern> {
164 field bits<32> SoftFail = 0;
169 let Inst{31-24} = op{11-4};
170 let Inst{23-20} = R1;
171 let Inst{19-16} = op{3-0};
175 class InstRIEb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
176 : InstSystemZ<6, outs, ins, asmstr, pattern> {
178 field bits<48> SoftFail = 0;
185 let Inst{47-40} = op{15-8};
186 let Inst{39-36} = R1;
187 let Inst{35-32} = R2;
188 let Inst{31-16} = RI4;
189 let Inst{15-12} = M3;
191 let Inst{7-0} = op{7-0};
194 class InstRIEc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
195 : InstSystemZ<6, outs, ins, asmstr, pattern> {
197 field bits<48> SoftFail = 0;
204 let Inst{47-40} = op{15-8};
205 let Inst{39-36} = R1;
206 let Inst{35-32} = M3;
207 let Inst{31-16} = RI4;
209 let Inst{7-0} = op{7-0};
212 class InstRIEd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
213 : InstSystemZ<6, outs, ins, asmstr, pattern> {
215 field bits<48> SoftFail = 0;
221 let Inst{47-40} = op{15-8};
222 let Inst{39-36} = R1;
223 let Inst{35-32} = R3;
224 let Inst{31-16} = I2;
226 let Inst{7-0} = op{7-0};
229 class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
230 : InstSystemZ<6, outs, ins, asmstr, pattern> {
232 field bits<48> SoftFail = 0;
240 let Inst{47-40} = op{15-8};
241 let Inst{39-36} = R1;
242 let Inst{35-32} = R2;
243 let Inst{31-24} = I3;
244 let Inst{23-16} = I4;
246 let Inst{7-0} = op{7-0};
249 class InstRIL<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
250 : InstSystemZ<6, outs, ins, asmstr, pattern> {
252 field bits<48> SoftFail = 0;
257 let Inst{47-40} = op{11-4};
258 let Inst{39-36} = R1;
259 let Inst{35-32} = op{3-0};
263 class InstRR<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
264 : InstSystemZ<2, outs, ins, asmstr, pattern> {
266 field bits<16> SoftFail = 0;
276 class InstRRD<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
277 : InstSystemZ<4, outs, ins, asmstr, pattern> {
279 field bits<32> SoftFail = 0;
285 let Inst{31-16} = op;
286 let Inst{15-12} = R1;
292 class InstRRE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
293 : InstSystemZ<4, outs, ins, asmstr, pattern> {
295 field bits<32> SoftFail = 0;
300 let Inst{31-16} = op;
306 class InstRRF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
307 : InstSystemZ<4, outs, ins, asmstr, pattern> {
309 field bits<32> SoftFail = 0;
316 let Inst{31-16} = op;
317 let Inst{15-12} = R3;
323 class InstRX<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
324 : InstSystemZ<4, outs, ins, asmstr, pattern> {
326 field bits<32> SoftFail = 0;
331 let Inst{31-24} = op;
332 let Inst{23-20} = R1;
333 let Inst{19-0} = XBD2;
338 class InstRXE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
339 : InstSystemZ<6, outs, ins, asmstr, pattern> {
341 field bits<48> SoftFail = 0;
347 let Inst{47-40} = op{15-8};
348 let Inst{39-36} = R1;
349 let Inst{35-16} = XBD2;
350 let Inst{15-12} = M3;
352 let Inst{7-0} = op{7-0};
357 class InstRXF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
358 : InstSystemZ<6, outs, ins, asmstr, pattern> {
360 field bits<48> SoftFail = 0;
366 let Inst{47-40} = op{15-8};
367 let Inst{39-36} = R3;
368 let Inst{35-16} = XBD2;
369 let Inst{15-12} = R1;
371 let Inst{7-0} = op{7-0};
376 class InstRXY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
377 : InstSystemZ<6, outs, ins, asmstr, pattern> {
379 field bits<48> SoftFail = 0;
384 let Inst{47-40} = op{15-8};
385 let Inst{39-36} = R1;
386 let Inst{35-8} = XBD2;
387 let Inst{7-0} = op{7-0};
389 let Has20BitOffset = 1;
393 class InstRS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
394 : InstSystemZ<4, outs, ins, asmstr, pattern> {
396 field bits<32> SoftFail = 0;
402 let Inst{31-24} = op;
403 let Inst{23-20} = R1;
404 let Inst{19-16} = R3;
405 let Inst{15-0} = BD2;
408 class InstRSY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
409 : InstSystemZ<6, outs, ins, asmstr, pattern> {
411 field bits<48> SoftFail = 0;
417 let Inst{47-40} = op{15-8};
418 let Inst{39-36} = R1;
419 let Inst{35-32} = R3;
420 let Inst{31-8} = BD2;
421 let Inst{7-0} = op{7-0};
423 let Has20BitOffset = 1;
426 class InstSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
427 : InstSystemZ<4, outs, ins, asmstr, pattern> {
429 field bits<32> SoftFail = 0;
434 let Inst{31-24} = op;
435 let Inst{23-16} = I2;
436 let Inst{15-0} = BD1;
439 class InstSIL<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
440 : InstSystemZ<6, outs, ins, asmstr, pattern> {
442 field bits<48> SoftFail = 0;
447 let Inst{47-32} = op;
448 let Inst{31-16} = BD1;
452 class InstSIY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
453 : InstSystemZ<6, outs, ins, asmstr, pattern> {
455 field bits<48> SoftFail = 0;
460 let Inst{47-40} = op{15-8};
461 let Inst{39-32} = I2;
462 let Inst{31-8} = BD1;
463 let Inst{7-0} = op{7-0};
465 let Has20BitOffset = 1;
468 class InstSS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
469 : InstSystemZ<6, outs, ins, asmstr, pattern> {
471 field bits<48> SoftFail = 0;
476 let Inst{47-40} = op;
477 let Inst{39-16} = BDL1;
478 let Inst{15-0} = BD2;
481 class InstS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
482 : InstSystemZ<4, outs, ins, asmstr, pattern> {
484 field bits<32> SoftFail = 0;
488 let Inst{31-16} = op;
489 let Inst{15-0} = BD2;
492 class InstVRIa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
493 : InstSystemZ<6, outs, ins, asmstr, pattern> {
495 field bits<48> SoftFail = 0;
501 let Inst{47-40} = op{15-8};
502 let Inst{39-36} = V1{3-0};
504 let Inst{31-16} = I2;
505 let Inst{15-12} = M3;
506 let Inst{11} = V1{4};
508 let Inst{7-0} = op{7-0};
511 class InstVRIb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
512 : InstSystemZ<6, outs, ins, asmstr, pattern> {
514 field bits<48> SoftFail = 0;
521 let Inst{47-40} = op{15-8};
522 let Inst{39-36} = V1{3-0};
524 let Inst{31-24} = I2;
525 let Inst{23-16} = I3;
526 let Inst{15-12} = M4;
527 let Inst{11} = V1{4};
529 let Inst{7-0} = op{7-0};
532 class InstVRIc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
533 : InstSystemZ<6, outs, ins, asmstr, pattern> {
535 field bits<48> SoftFail = 0;
542 let Inst{47-40} = op{15-8};
543 let Inst{39-36} = V1{3-0};
544 let Inst{35-32} = V3{3-0};
545 let Inst{31-16} = I2;
546 let Inst{15-12} = M4;
547 let Inst{11} = V1{4};
548 let Inst{10} = V3{4};
550 let Inst{7-0} = op{7-0};
553 class InstVRId<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
554 : InstSystemZ<6, outs, ins, asmstr, pattern> {
556 field bits<48> SoftFail = 0;
564 let Inst{47-40} = op{15-8};
565 let Inst{39-36} = V1{3-0};
566 let Inst{35-32} = V2{3-0};
567 let Inst{31-28} = V3{3-0};
569 let Inst{23-16} = I4;
570 let Inst{15-12} = M5;
571 let Inst{11} = V1{4};
572 let Inst{10} = V2{4};
575 let Inst{7-0} = op{7-0};
578 class InstVRIe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
579 : InstSystemZ<6, outs, ins, asmstr, pattern> {
581 field bits<48> SoftFail = 0;
589 let Inst{47-40} = op{15-8};
590 let Inst{39-36} = V1{3-0};
591 let Inst{35-32} = V2{3-0};
592 let Inst{31-20} = I3;
593 let Inst{19-16} = M5;
594 let Inst{15-12} = M4;
595 let Inst{11} = V1{4};
596 let Inst{10} = V2{4};
598 let Inst{7-0} = op{7-0};
601 // Depending on the instruction mnemonic, certain bits may be or-ed into
602 // the M4 value provided as explicit operand. These are passed as m4or.
603 class InstVRRa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
605 : InstSystemZ<6, outs, ins, asmstr, pattern> {
607 field bits<48> SoftFail = 0;
615 let Inst{47-40} = op{15-8};
616 let Inst{39-36} = V1{3-0};
617 let Inst{35-32} = V2{3-0};
619 let Inst{23-20} = M5;
620 let Inst{19} = !if (!eq (m4or{3}, 1), 1, M4{3});
621 let Inst{18} = !if (!eq (m4or{2}, 1), 1, M4{2});
622 let Inst{17} = !if (!eq (m4or{1}, 1), 1, M4{1});
623 let Inst{16} = !if (!eq (m4or{0}, 1), 1, M4{0});
624 let Inst{15-12} = M3;
625 let Inst{11} = V1{4};
626 let Inst{10} = V2{4};
628 let Inst{7-0} = op{7-0};
631 // Depending on the instruction mnemonic, certain bits may be or-ed into
632 // the M5 value provided as explicit operand. These are passed as m5or.
633 class InstVRRb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
635 : InstSystemZ<6, outs, ins, asmstr, pattern> {
637 field bits<48> SoftFail = 0;
645 let Inst{47-40} = op{15-8};
646 let Inst{39-36} = V1{3-0};
647 let Inst{35-32} = V2{3-0};
648 let Inst{31-28} = V3{3-0};
650 let Inst{23} = !if (!eq (m5or{3}, 1), 1, M5{3});
651 let Inst{22} = !if (!eq (m5or{2}, 1), 1, M5{2});
652 let Inst{21} = !if (!eq (m5or{1}, 1), 1, M5{1});
653 let Inst{20} = !if (!eq (m5or{0}, 1), 1, M5{0});
655 let Inst{15-12} = M4;
656 let Inst{11} = V1{4};
657 let Inst{10} = V2{4};
660 let Inst{7-0} = op{7-0};
663 class InstVRRc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
664 : InstSystemZ<6, outs, ins, asmstr, pattern> {
666 field bits<48> SoftFail = 0;
675 let Inst{47-40} = op{15-8};
676 let Inst{39-36} = V1{3-0};
677 let Inst{35-32} = V2{3-0};
678 let Inst{31-28} = V3{3-0};
680 let Inst{23-20} = M6;
681 let Inst{19-16} = M5;
682 let Inst{15-12} = M4;
683 let Inst{11} = V1{4};
684 let Inst{10} = V2{4};
687 let Inst{7-0} = op{7-0};
690 // Depending on the instruction mnemonic, certain bits may be or-ed into
691 // the M6 value provided as explicit operand. These are passed as m6or.
692 class InstVRRd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
694 : InstSystemZ<6, outs, ins, asmstr, pattern> {
696 field bits<48> SoftFail = 0;
705 let Inst{47-40} = op{15-8};
706 let Inst{39-36} = V1{3-0};
707 let Inst{35-32} = V2{3-0};
708 let Inst{31-28} = V3{3-0};
709 let Inst{27-24} = M5;
710 let Inst{23} = !if (!eq (m6or{3}, 1), 1, M6{3});
711 let Inst{22} = !if (!eq (m6or{2}, 1), 1, M6{2});
712 let Inst{21} = !if (!eq (m6or{1}, 1), 1, M6{1});
713 let Inst{20} = !if (!eq (m6or{0}, 1), 1, M6{0});
715 let Inst{15-12} = V4{3-0};
716 let Inst{11} = V1{4};
717 let Inst{10} = V2{4};
720 let Inst{7-0} = op{7-0};
723 class InstVRRe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
724 : InstSystemZ<6, outs, ins, asmstr, pattern> {
726 field bits<48> SoftFail = 0;
735 let Inst{47-40} = op{15-8};
736 let Inst{39-36} = V1{3-0};
737 let Inst{35-32} = V2{3-0};
738 let Inst{31-28} = V3{3-0};
739 let Inst{27-24} = M6;
741 let Inst{19-16} = M5;
742 let Inst{15-12} = V4{3-0};
743 let Inst{11} = V1{4};
744 let Inst{10} = V2{4};
747 let Inst{7-0} = op{7-0};
750 class InstVRRf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
751 : InstSystemZ<6, outs, ins, asmstr, pattern> {
753 field bits<48> SoftFail = 0;
759 let Inst{47-40} = op{15-8};
760 let Inst{39-36} = V1{3-0};
761 let Inst{35-32} = R2;
762 let Inst{31-28} = R3;
764 let Inst{11} = V1{4};
766 let Inst{7-0} = op{7-0};
769 class InstVRSa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
770 : InstSystemZ<6, outs, ins, asmstr, pattern> {
772 field bits<48> SoftFail = 0;
779 let Inst{47-40} = op{15-8};
780 let Inst{39-36} = V1{3-0};
781 let Inst{35-32} = V3{3-0};
782 let Inst{31-16} = BD2;
783 let Inst{15-12} = M4;
784 let Inst{11} = V1{4};
785 let Inst{10} = V3{4};
787 let Inst{7-0} = op{7-0};
790 class InstVRSb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
791 : InstSystemZ<6, outs, ins, asmstr, pattern> {
793 field bits<48> SoftFail = 0;
800 let Inst{47-40} = op{15-8};
801 let Inst{39-36} = V1{3-0};
802 let Inst{35-32} = R3;
803 let Inst{31-16} = BD2;
804 let Inst{15-12} = M4;
805 let Inst{11} = V1{4};
807 let Inst{7-0} = op{7-0};
810 class InstVRSc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
811 : InstSystemZ<6, outs, ins, asmstr, pattern> {
813 field bits<48> SoftFail = 0;
820 let Inst{47-40} = op{15-8};
821 let Inst{39-36} = R1;
822 let Inst{35-32} = V3{3-0};
823 let Inst{31-16} = BD2;
824 let Inst{15-12} = M4;
826 let Inst{10} = V3{4};
828 let Inst{7-0} = op{7-0};
831 class InstVRV<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
832 : InstSystemZ<6, outs, ins, asmstr, pattern> {
834 field bits<48> SoftFail = 0;
840 let Inst{47-40} = op{15-8};
841 let Inst{39-36} = V1{3-0};
842 let Inst{35-16} = VBD2{19-0};
843 let Inst{15-12} = M3;
844 let Inst{11} = V1{4};
845 let Inst{10} = VBD2{20};
847 let Inst{7-0} = op{7-0};
850 class InstVRX<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
851 : InstSystemZ<6, outs, ins, asmstr, pattern> {
853 field bits<48> SoftFail = 0;
859 let Inst{47-40} = op{15-8};
860 let Inst{39-36} = V1{3-0};
861 let Inst{35-16} = XBD2;
862 let Inst{15-12} = M3;
863 let Inst{11} = V1{4};
865 let Inst{7-0} = op{7-0};
868 //===----------------------------------------------------------------------===//
869 // Instruction definitions with semantics
870 //===----------------------------------------------------------------------===//
872 // These classes have the form [Cond]<Category><Format>, where <Format> is one
873 // of the formats defined above and where <Category> describes the inputs
874 // and outputs. "Cond" is used if the instruction is conditional,
875 // in which case the 4-bit condition-code mask is added as a final operand.
876 // <Category> can be one of:
879 // One register output operand and no input operands.
882 // One register output operand, one register input operand and
883 // one branch displacement. The instructions stores a modified
884 // form of the source register in the destination register and
885 // branches on the result.
888 // One address input operand and two explicit output operands.
889 // The instruction loads a range of registers from the address,
890 // with the explicit operands giving the first and last register
891 // to load. Other loaded registers are added as implicit definitions.
894 // Two explicit input register operands and an address operand.
895 // The instruction stores a range of registers to the address,
896 // with the explicit operands giving the first and last register
897 // to store. Other stored registers are added as implicit uses.
900 // One value operand, one length operand and one address operand.
901 // The instruction stores the value operand to the address but
902 // doesn't write more than the number of bytes specified by the
906 // One register output operand and one input operand.
909 // One address operand and one other input operand. The instruction
910 // stores to the address.
913 // One register output operand and two input operands.
916 // One address operand and two other input operands. The instruction
917 // stores to the address.
920 // Two input operands and an implicit CC output operand.
923 // One register output operand and three input operands.
926 // One register output operand and four input operands.
929 // One output operand and two input operands, one of which is an address.
930 // The instruction both reads from and writes to the address.
933 // One output operand and three input operands, one of which is an address.
934 // The instruction both reads from and writes to the address.
937 // One output operand and five input operands. The first two operands
938 // are registers and the other three are immediates.
941 // One 4-bit immediate operand and one address operand. The immediate
942 // operand is 1 for a load prefetch and 2 for a store prefetch.
944 // The format determines which input operands are tied to output operands,
945 // and also determines the shape of any address operand.
947 // Multiclasses of the form <Category><Format>Pair define two instructions,
948 // one with <Category><Format> and one with <Category><Format>Y. The name
949 // of the first instruction has no suffix, the name of the second has
952 //===----------------------------------------------------------------------===//
954 class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
956 : InstRRE<opcode, (outs cls:$R1), (ins),
958 [(set cls:$R1, src)]> {
962 class InherentVRIa<string mnemonic, bits<16> opcode, bits<16> value>
963 : InstVRIa<opcode, (outs VR128:$V1), (ins), mnemonic#"\t$V1", []> {
968 class BranchUnaryRI<string mnemonic, bits<12> opcode, RegisterOperand cls>
969 : InstRI<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget16:$I2),
970 mnemonic##"\t$R1, $I2", []> {
972 let isTerminator = 1;
973 let Constraints = "$R1 = $R1src";
974 let DisableEncoding = "$R1src";
977 class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
978 : InstRSY<opcode, (outs cls:$R1, cls:$R3), (ins bdaddr20only:$BD2),
979 mnemonic#"\t$R1, $R3, $BD2", []> {
983 class LoadMultipleVRSa<string mnemonic, bits<16> opcode>
984 : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3), (ins bdaddr12only:$BD2),
985 mnemonic#"\t$V1, $V3, $BD2", []> {
990 class StoreRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
992 : InstRIL<opcode, (outs), (ins cls:$R1, pcrel32:$I2),
993 mnemonic#"\t$R1, $I2",
994 [(operator cls:$R1, pcrel32:$I2)]> {
996 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
997 // However, BDXs have two extra operands and are therefore 6 units more
999 let AddedComplexity = 7;
1002 class StoreRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1003 RegisterOperand cls, bits<5> bytes,
1004 AddressingMode mode = bdxaddr12only>
1005 : InstRX<opcode, (outs), (ins cls:$R1, mode:$XBD2),
1006 mnemonic#"\t$R1, $XBD2",
1007 [(operator cls:$R1, mode:$XBD2)]> {
1008 let OpKey = mnemonic ## cls;
1011 let AccessBytes = bytes;
1014 class StoreRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1015 RegisterOperand cls, bits<5> bytes,
1016 AddressingMode mode = bdxaddr20only>
1017 : InstRXY<opcode, (outs), (ins cls:$R1, mode:$XBD2),
1018 mnemonic#"\t$R1, $XBD2",
1019 [(operator cls:$R1, mode:$XBD2)]> {
1020 let OpKey = mnemonic ## cls;
1023 let AccessBytes = bytes;
1026 multiclass StoreRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
1027 SDPatternOperator operator, RegisterOperand cls,
1029 let DispKey = mnemonic ## #cls in {
1030 let DispSize = "12" in
1031 def "" : StoreRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>;
1032 let DispSize = "20" in
1033 def Y : StoreRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes,
1038 class StoreVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1039 TypedReg tr, bits<5> bytes, bits<4> type = 0>
1040 : InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2),
1041 mnemonic#"\t$V1, $XBD2",
1042 [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2)))]> {
1045 let AccessBytes = bytes;
1048 class StoreLengthVRSb<string mnemonic, bits<16> opcode,
1049 SDPatternOperator operator, bits<5> bytes>
1050 : InstVRSb<opcode, (outs), (ins VR128:$V1, GR32:$R3, bdaddr12only:$BD2),
1051 mnemonic#"\t$V1, $R3, $BD2",
1052 [(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> {
1055 let AccessBytes = bytes;
1058 class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
1059 : InstRSY<opcode, (outs), (ins cls:$R1, cls:$R3, bdaddr20only:$BD2),
1060 mnemonic#"\t$R1, $R3, $BD2", []> {
1064 class StoreMultipleVRSa<string mnemonic, bits<16> opcode>
1065 : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3, bdaddr12only:$BD2),
1066 mnemonic#"\t$V1, $V3, $BD2", []> {
1071 // StoreSI* instructions are used to store an integer to memory, but the
1072 // addresses are more restricted than for normal stores. If we are in the
1073 // situation of having to force either the address into a register or the
1074 // constant into a register, it's usually better to do the latter.
1075 // We therefore match the address in the same way as a normal store and
1076 // only use the StoreSI* instruction if the matched address is suitable.
1077 class StoreSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1079 : InstSI<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2),
1080 mnemonic#"\t$BD1, $I2",
1081 [(operator imm:$I2, mviaddr12pair:$BD1)]> {
1085 class StoreSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1087 : InstSIY<opcode, (outs), (ins mviaddr20pair:$BD1, imm:$I2),
1088 mnemonic#"\t$BD1, $I2",
1089 [(operator imm:$I2, mviaddr20pair:$BD1)]> {
1093 class StoreSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1095 : InstSIL<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2),
1096 mnemonic#"\t$BD1, $I2",
1097 [(operator imm:$I2, mviaddr12pair:$BD1)]> {
1101 multiclass StoreSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
1102 SDPatternOperator operator, Immediate imm> {
1103 let DispKey = mnemonic in {
1104 let DispSize = "12" in
1105 def "" : StoreSI<mnemonic, siOpcode, operator, imm>;
1106 let DispSize = "20" in
1107 def Y : StoreSIY<mnemonic#"y", siyOpcode, operator, imm>;
1111 class CondStoreRSY<string mnemonic, bits<16> opcode,
1112 RegisterOperand cls, bits<5> bytes,
1113 AddressingMode mode = bdaddr20only>
1114 : InstRSY<opcode, (outs), (ins cls:$R1, mode:$BD2, cond4:$valid, cond4:$R3),
1115 mnemonic#"$R3\t$R1, $BD2", []>,
1116 Requires<[FeatureLoadStoreOnCond]> {
1118 let AccessBytes = bytes;
1122 // Like CondStoreRSY, but used for the raw assembly form. The condition-code
1123 // mask is the third operand rather than being part of the mnemonic.
1124 class AsmCondStoreRSY<string mnemonic, bits<16> opcode,
1125 RegisterOperand cls, bits<5> bytes,
1126 AddressingMode mode = bdaddr20only>
1127 : InstRSY<opcode, (outs), (ins cls:$R1, mode:$BD2, imm32zx4:$R3),
1128 mnemonic#"\t$R1, $BD2, $R3", []>,
1129 Requires<[FeatureLoadStoreOnCond]> {
1131 let AccessBytes = bytes;
1134 // Like CondStoreRSY, but with a fixed CC mask.
1135 class FixedCondStoreRSY<string mnemonic, bits<16> opcode,
1136 RegisterOperand cls, bits<4> ccmask, bits<5> bytes,
1137 AddressingMode mode = bdaddr20only>
1138 : InstRSY<opcode, (outs), (ins cls:$R1, mode:$BD2),
1139 mnemonic#"\t$R1, $BD2", []>,
1140 Requires<[FeatureLoadStoreOnCond]> {
1142 let AccessBytes = bytes;
1146 class UnaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1147 RegisterOperand cls1, RegisterOperand cls2>
1148 : InstRR<opcode, (outs cls1:$R1), (ins cls2:$R2),
1149 mnemonic#"r\t$R1, $R2",
1150 [(set cls1:$R1, (operator cls2:$R2))]> {
1151 let OpKey = mnemonic ## cls1;
1155 class UnaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1156 RegisterOperand cls1, RegisterOperand cls2>
1157 : InstRRE<opcode, (outs cls1:$R1), (ins cls2:$R2),
1158 mnemonic#"r\t$R1, $R2",
1159 [(set cls1:$R1, (operator cls2:$R2))]> {
1160 let OpKey = mnemonic ## cls1;
1164 class UnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
1165 RegisterOperand cls2>
1166 : InstRRF<opcode, (outs cls1:$R1), (ins imm32zx4:$R3, cls2:$R2),
1167 mnemonic#"r\t$R1, $R3, $R2", []> {
1168 let OpKey = mnemonic ## cls1;
1173 class UnaryRRF4<string mnemonic, bits<16> opcode, RegisterOperand cls1,
1174 RegisterOperand cls2>
1175 : InstRRF<opcode, (outs cls1:$R1), (ins imm32zx4:$R3, cls2:$R2, imm32zx4:$R4),
1176 mnemonic#"\t$R1, $R3, $R2, $R4", []>;
1178 // These instructions are generated by if conversion. The old value of R1
1179 // is added as an implicit use.
1180 class CondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
1181 RegisterOperand cls2>
1182 : InstRRF<opcode, (outs cls1:$R1), (ins cls2:$R2, cond4:$valid, cond4:$R3),
1183 mnemonic#"r$R3\t$R1, $R2", []>,
1184 Requires<[FeatureLoadStoreOnCond]> {
1189 // Like CondUnaryRRF, but used for the raw assembly form. The condition-code
1190 // mask is the third operand rather than being part of the mnemonic.
1191 class AsmCondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
1192 RegisterOperand cls2>
1193 : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2, imm32zx4:$R3),
1194 mnemonic#"r\t$R1, $R2, $R3", []>,
1195 Requires<[FeatureLoadStoreOnCond]> {
1196 let Constraints = "$R1 = $R1src";
1197 let DisableEncoding = "$R1src";
1201 // Like CondUnaryRRF, but with a fixed CC mask.
1202 class FixedCondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
1203 RegisterOperand cls2, bits<4> ccmask>
1204 : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
1205 mnemonic#"\t$R1, $R2", []>,
1206 Requires<[FeatureLoadStoreOnCond]> {
1207 let Constraints = "$R1 = $R1src";
1208 let DisableEncoding = "$R1src";
1213 class UnaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1214 RegisterOperand cls, Immediate imm>
1215 : InstRI<opcode, (outs cls:$R1), (ins imm:$I2),
1216 mnemonic#"\t$R1, $I2",
1217 [(set cls:$R1, (operator imm:$I2))]>;
1219 class UnaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1220 RegisterOperand cls, Immediate imm>
1221 : InstRIL<opcode, (outs cls:$R1), (ins imm:$I2),
1222 mnemonic#"\t$R1, $I2",
1223 [(set cls:$R1, (operator imm:$I2))]>;
1225 class UnaryRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1226 RegisterOperand cls>
1227 : InstRIL<opcode, (outs cls:$R1), (ins pcrel32:$I2),
1228 mnemonic#"\t$R1, $I2",
1229 [(set cls:$R1, (operator pcrel32:$I2))]> {
1231 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
1232 // However, BDXs have two extra operands and are therefore 6 units more
1234 let AddedComplexity = 7;
1237 class CondUnaryRSY<string mnemonic, bits<16> opcode,
1238 SDPatternOperator operator, RegisterOperand cls,
1239 bits<5> bytes, AddressingMode mode = bdaddr20only>
1240 : InstRSY<opcode, (outs cls:$R1),
1241 (ins cls:$R1src, mode:$BD2, cond4:$valid, cond4:$R3),
1242 mnemonic#"$R3\t$R1, $BD2",
1244 (z_select_ccmask (load bdaddr20only:$BD2), cls:$R1src,
1245 cond4:$valid, cond4:$R3))]>,
1246 Requires<[FeatureLoadStoreOnCond]> {
1247 let Constraints = "$R1 = $R1src";
1248 let DisableEncoding = "$R1src";
1250 let AccessBytes = bytes;
1254 // Like CondUnaryRSY, but used for the raw assembly form. The condition-code
1255 // mask is the third operand rather than being part of the mnemonic.
1256 class AsmCondUnaryRSY<string mnemonic, bits<16> opcode,
1257 RegisterOperand cls, bits<5> bytes,
1258 AddressingMode mode = bdaddr20only>
1259 : InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2, imm32zx4:$R3),
1260 mnemonic#"\t$R1, $BD2, $R3", []>,
1261 Requires<[FeatureLoadStoreOnCond]> {
1263 let AccessBytes = bytes;
1264 let Constraints = "$R1 = $R1src";
1265 let DisableEncoding = "$R1src";
1268 // Like CondUnaryRSY, but with a fixed CC mask.
1269 class FixedCondUnaryRSY<string mnemonic, bits<16> opcode,
1270 RegisterOperand cls, bits<4> ccmask, bits<5> bytes,
1271 AddressingMode mode = bdaddr20only>
1272 : InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2),
1273 mnemonic#"\t$R1, $BD2", []>,
1274 Requires<[FeatureLoadStoreOnCond]> {
1275 let Constraints = "$R1 = $R1src";
1276 let DisableEncoding = "$R1src";
1279 let AccessBytes = bytes;
1282 class UnaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1283 RegisterOperand cls, bits<5> bytes,
1284 AddressingMode mode = bdxaddr12only>
1285 : InstRX<opcode, (outs cls:$R1), (ins mode:$XBD2),
1286 mnemonic#"\t$R1, $XBD2",
1287 [(set cls:$R1, (operator mode:$XBD2))]> {
1288 let OpKey = mnemonic ## cls;
1291 let AccessBytes = bytes;
1294 class UnaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1295 RegisterOperand cls, bits<5> bytes>
1296 : InstRXE<opcode, (outs cls:$R1), (ins bdxaddr12only:$XBD2),
1297 mnemonic#"\t$R1, $XBD2",
1298 [(set cls:$R1, (operator bdxaddr12only:$XBD2))]> {
1299 let OpKey = mnemonic ## cls;
1302 let AccessBytes = bytes;
1306 class UnaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1307 RegisterOperand cls, bits<5> bytes,
1308 AddressingMode mode = bdxaddr20only>
1309 : InstRXY<opcode, (outs cls:$R1), (ins mode:$XBD2),
1310 mnemonic#"\t$R1, $XBD2",
1311 [(set cls:$R1, (operator mode:$XBD2))]> {
1312 let OpKey = mnemonic ## cls;
1315 let AccessBytes = bytes;
1318 multiclass UnaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
1319 SDPatternOperator operator, RegisterOperand cls,
1321 let DispKey = mnemonic ## #cls in {
1322 let DispSize = "12" in
1323 def "" : UnaryRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>;
1324 let DispSize = "20" in
1325 def Y : UnaryRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes,
1330 class UnaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1331 TypedReg tr, Immediate imm, bits<4> type = 0>
1332 : InstVRIa<opcode, (outs tr.op:$V1), (ins imm:$I2),
1333 mnemonic#"\t$V1, $I2",
1334 [(set tr.op:$V1, (tr.vt (operator imm:$I2)))]> {
1338 class UnaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1339 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m4 = 0,
1341 : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2),
1342 mnemonic#"\t$V1, $V2",
1343 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2))))]> {
1349 multiclass UnaryVRRaSPair<string mnemonic, bits<16> opcode,
1350 SDPatternOperator operator,
1351 SDPatternOperator operator_cc, TypedReg tr1,
1352 TypedReg tr2, bits<4> type, bits<4> modifier = 0,
1353 bits<4> modifier_cc = 1> {
1354 def "" : UnaryVRRa<mnemonic, opcode, operator, tr1, tr2, type, 0, modifier>;
1356 def S : UnaryVRRa<mnemonic##"s", opcode, operator_cc, tr1, tr2, type, 0,
1360 class UnaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1361 TypedReg tr, bits<5> bytes, bits<4> type = 0>
1362 : InstVRX<opcode, (outs tr.op:$V1), (ins bdxaddr12only:$XBD2),
1363 mnemonic#"\t$V1, $XBD2",
1364 [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2)))]> {
1367 let AccessBytes = bytes;
1370 class BinaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1371 RegisterOperand cls1, RegisterOperand cls2>
1372 : InstRR<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
1373 mnemonic#"r\t$R1, $R2",
1374 [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
1375 let OpKey = mnemonic ## cls1;
1377 let Constraints = "$R1 = $R1src";
1378 let DisableEncoding = "$R1src";
1381 class BinaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1382 RegisterOperand cls1, RegisterOperand cls2>
1383 : InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
1384 mnemonic#"r\t$R1, $R2",
1385 [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
1386 let OpKey = mnemonic ## cls1;
1388 let Constraints = "$R1 = $R1src";
1389 let DisableEncoding = "$R1src";
1392 class BinaryRRF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1393 RegisterOperand cls1, RegisterOperand cls2>
1394 : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R3, cls2:$R2),
1395 mnemonic#"r\t$R1, $R3, $R2",
1396 [(set cls1:$R1, (operator cls1:$R3, cls2:$R2))]> {
1397 let OpKey = mnemonic ## cls1;
1402 class BinaryRRFK<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1403 RegisterOperand cls1, RegisterOperand cls2>
1404 : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R2, cls2:$R3),
1405 mnemonic#"rk\t$R1, $R2, $R3",
1406 [(set cls1:$R1, (operator cls1:$R2, cls2:$R3))]> {
1410 multiclass BinaryRRAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
1411 SDPatternOperator operator, RegisterOperand cls1,
1412 RegisterOperand cls2> {
1413 let NumOpsKey = mnemonic in {
1414 let NumOpsValue = "3" in
1415 def K : BinaryRRFK<mnemonic, opcode2, null_frag, cls1, cls2>,
1416 Requires<[FeatureDistinctOps]>;
1417 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
1418 def "" : BinaryRR<mnemonic, opcode1, operator, cls1, cls2>;
1422 multiclass BinaryRREAndK<string mnemonic, bits<16> opcode1, bits<16> opcode2,
1423 SDPatternOperator operator, RegisterOperand cls1,
1424 RegisterOperand cls2> {
1425 let NumOpsKey = mnemonic in {
1426 let NumOpsValue = "3" in
1427 def K : BinaryRRFK<mnemonic, opcode2, null_frag, cls1, cls2>,
1428 Requires<[FeatureDistinctOps]>;
1429 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
1430 def "" : BinaryRRE<mnemonic, opcode1, operator, cls1, cls2>;
1434 class BinaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1435 RegisterOperand cls, Immediate imm>
1436 : InstRI<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
1437 mnemonic#"\t$R1, $I2",
1438 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
1439 let Constraints = "$R1 = $R1src";
1440 let DisableEncoding = "$R1src";
1443 class BinaryRIE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1444 RegisterOperand cls, Immediate imm>
1445 : InstRIEd<opcode, (outs cls:$R1), (ins cls:$R3, imm:$I2),
1446 mnemonic#"\t$R1, $R3, $I2",
1447 [(set cls:$R1, (operator cls:$R3, imm:$I2))]>;
1449 multiclass BinaryRIAndK<string mnemonic, bits<12> opcode1, bits<16> opcode2,
1450 SDPatternOperator operator, RegisterOperand cls,
1452 let NumOpsKey = mnemonic in {
1453 let NumOpsValue = "3" in
1454 def K : BinaryRIE<mnemonic##"k", opcode2, null_frag, cls, imm>,
1455 Requires<[FeatureDistinctOps]>;
1456 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
1457 def "" : BinaryRI<mnemonic, opcode1, operator, cls, imm>;
1461 class BinaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1462 RegisterOperand cls, Immediate imm>
1463 : InstRIL<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
1464 mnemonic#"\t$R1, $I2",
1465 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
1466 let Constraints = "$R1 = $R1src";
1467 let DisableEncoding = "$R1src";
1470 class BinaryRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1471 RegisterOperand cls>
1472 : InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, shift12only:$BD2),
1473 mnemonic#"\t$R1, $BD2",
1474 [(set cls:$R1, (operator cls:$R1src, shift12only:$BD2))]> {
1476 let Constraints = "$R1 = $R1src";
1477 let DisableEncoding = "$R1src";
1480 class BinaryRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1481 RegisterOperand cls>
1482 : InstRSY<opcode, (outs cls:$R1), (ins cls:$R3, shift20only:$BD2),
1483 mnemonic#"\t$R1, $R3, $BD2",
1484 [(set cls:$R1, (operator cls:$R3, shift20only:$BD2))]>;
1486 multiclass BinaryRSAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
1487 SDPatternOperator operator, RegisterOperand cls> {
1488 let NumOpsKey = mnemonic in {
1489 let NumOpsValue = "3" in
1490 def K : BinaryRSY<mnemonic##"k", opcode2, null_frag, cls>,
1491 Requires<[FeatureDistinctOps]>;
1492 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
1493 def "" : BinaryRS<mnemonic, opcode1, operator, cls>;
1497 class BinaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1498 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
1499 AddressingMode mode = bdxaddr12only>
1500 : InstRX<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
1501 mnemonic#"\t$R1, $XBD2",
1502 [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
1503 let OpKey = mnemonic ## cls;
1505 let Constraints = "$R1 = $R1src";
1506 let DisableEncoding = "$R1src";
1508 let AccessBytes = bytes;
1511 class BinaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1512 RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
1513 : InstRXE<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr12only:$XBD2),
1514 mnemonic#"\t$R1, $XBD2",
1515 [(set cls:$R1, (operator cls:$R1src,
1516 (load bdxaddr12only:$XBD2)))]> {
1517 let OpKey = mnemonic ## cls;
1519 let Constraints = "$R1 = $R1src";
1520 let DisableEncoding = "$R1src";
1522 let AccessBytes = bytes;
1526 class BinaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1527 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
1528 AddressingMode mode = bdxaddr20only>
1529 : InstRXY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
1530 mnemonic#"\t$R1, $XBD2",
1531 [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
1532 let OpKey = mnemonic ## cls;
1534 let Constraints = "$R1 = $R1src";
1535 let DisableEncoding = "$R1src";
1537 let AccessBytes = bytes;
1540 multiclass BinaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
1541 SDPatternOperator operator, RegisterOperand cls,
1542 SDPatternOperator load, bits<5> bytes> {
1543 let DispKey = mnemonic ## #cls in {
1544 let DispSize = "12" in
1545 def "" : BinaryRX<mnemonic, rxOpcode, operator, cls, load, bytes,
1547 let DispSize = "20" in
1548 def Y : BinaryRXY<mnemonic#"y", rxyOpcode, operator, cls, load, bytes,
1553 class BinarySI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1554 Operand imm, AddressingMode mode = bdaddr12only>
1555 : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
1556 mnemonic#"\t$BD1, $I2",
1557 [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
1562 class BinarySIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1563 Operand imm, AddressingMode mode = bdaddr20only>
1564 : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
1565 mnemonic#"\t$BD1, $I2",
1566 [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
1571 multiclass BinarySIPair<string mnemonic, bits<8> siOpcode,
1572 bits<16> siyOpcode, SDPatternOperator operator,
1574 let DispKey = mnemonic ## #cls in {
1575 let DispSize = "12" in
1576 def "" : BinarySI<mnemonic, siOpcode, operator, imm, bdaddr12pair>;
1577 let DispSize = "20" in
1578 def Y : BinarySIY<mnemonic#"y", siyOpcode, operator, imm, bdaddr20pair>;
1582 class BinaryVRIb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1583 TypedReg tr, bits<4> type>
1584 : InstVRIb<opcode, (outs tr.op:$V1), (ins imm32zx8:$I2, imm32zx8:$I3),
1585 mnemonic#"\t$V1, $I2, $I3",
1586 [(set tr.op:$V1, (tr.vt (operator imm32zx8:$I2, imm32zx8:$I3)))]> {
1590 class BinaryVRIc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1591 TypedReg tr1, TypedReg tr2, bits<4> type>
1592 : InstVRIc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, imm32zx16:$I2),
1593 mnemonic#"\t$V1, $V3, $I2",
1594 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V3),
1595 imm32zx16:$I2)))]> {
1599 class BinaryVRIe<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1600 TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m5>
1601 : InstVRIe<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx12:$I3),
1602 mnemonic#"\t$V1, $V2, $I3",
1603 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
1604 imm32zx12:$I3)))]> {
1609 class BinaryVRRa<string mnemonic, bits<16> opcode>
1610 : InstVRRa<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3),
1611 mnemonic#"\t$V1, $V2, $M3", []> {
1616 class BinaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1617 TypedReg tr1, TypedReg tr2, bits<4> type = 0,
1618 bits<4> modifier = 0>
1619 : InstVRRb<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
1620 mnemonic#"\t$V1, $V2, $V3",
1621 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
1622 (tr2.vt tr2.op:$V3))))]> {
1627 // Declare a pair of instructions, one which sets CC and one which doesn't.
1628 // The CC-setting form ends with "S" and sets the low bit of M5.
1629 multiclass BinaryVRRbSPair<string mnemonic, bits<16> opcode,
1630 SDPatternOperator operator,
1631 SDPatternOperator operator_cc, TypedReg tr1,
1632 TypedReg tr2, bits<4> type,
1633 bits<4> modifier = 0, bits<4> modifier_cc = 1> {
1634 def "" : BinaryVRRb<mnemonic, opcode, operator, tr1, tr2, type, modifier>;
1636 def S : BinaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
1640 class BinaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1641 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m5 = 0,
1643 : InstVRRc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
1644 mnemonic#"\t$V1, $V2, $V3",
1645 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
1646 (tr2.vt tr2.op:$V3))))]> {
1652 multiclass BinaryVRRcSPair<string mnemonic, bits<16> opcode,
1653 SDPatternOperator operator,
1654 SDPatternOperator operator_cc, TypedReg tr1,
1655 TypedReg tr2, bits<4> type, bits<4> m5,
1656 bits<4> modifier = 0, bits<4> modifier_cc = 1> {
1657 def "" : BinaryVRRc<mnemonic, opcode, operator, tr1, tr2, type, m5, modifier>;
1659 def S : BinaryVRRc<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
1663 class BinaryVRRf<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1665 : InstVRRf<opcode, (outs tr.op:$V1), (ins GR64:$R2, GR64:$R3),
1666 mnemonic#"\t$V1, $R2, $R3",
1667 [(set tr.op:$V1, (tr.vt (operator GR64:$R2, GR64:$R3)))]>;
1669 class BinaryVRSa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1670 TypedReg tr1, TypedReg tr2, bits<4> type>
1671 : InstVRSa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, shift12only:$BD2),
1672 mnemonic#"\t$V1, $V3, $BD2",
1673 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V3),
1674 shift12only:$BD2)))]> {
1678 class BinaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1680 : InstVRSb<opcode, (outs VR128:$V1), (ins GR32:$R3, bdaddr12only:$BD2),
1681 mnemonic#"\t$V1, $R3, $BD2",
1682 [(set VR128:$V1, (operator GR32:$R3, bdaddr12only:$BD2))]> {
1685 let AccessBytes = bytes;
1688 class BinaryVRSc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1689 TypedReg tr, bits<4> type>
1690 : InstVRSc<opcode, (outs GR64:$R1), (ins tr.op:$V3, shift12only:$BD2),
1691 mnemonic#"\t$R1, $V3, $BD2",
1692 [(set GR64:$R1, (operator (tr.vt tr.op:$V3), shift12only:$BD2))]> {
1696 class BinaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1697 TypedReg tr, bits<5> bytes>
1698 : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
1699 mnemonic#"\t$V1, $XBD2, $M3",
1700 [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2,
1703 let AccessBytes = bytes;
1706 class StoreBinaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes,
1708 : InstVRV<opcode, (outs), (ins VR128:$V1, bdvaddr12only:$VBD2, index:$M3),
1709 mnemonic#"\t$V1, $VBD2, $M3", []> {
1711 let AccessBytes = bytes;
1714 class StoreBinaryVRX<string mnemonic, bits<16> opcode,
1715 SDPatternOperator operator, TypedReg tr, bits<5> bytes,
1717 : InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2, index:$M3),
1718 mnemonic#"\t$V1, $XBD2, $M3",
1719 [(operator (tr.vt tr.op:$V1), bdxaddr12only:$XBD2, index:$M3)]> {
1721 let AccessBytes = bytes;
1724 class CompareRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1725 RegisterOperand cls1, RegisterOperand cls2>
1726 : InstRR<opcode, (outs), (ins cls1:$R1, cls2:$R2),
1727 mnemonic#"r\t$R1, $R2",
1728 [(operator cls1:$R1, cls2:$R2)]> {
1729 let OpKey = mnemonic ## cls1;
1734 class CompareRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1735 RegisterOperand cls1, RegisterOperand cls2>
1736 : InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2),
1737 mnemonic#"r\t$R1, $R2",
1738 [(operator cls1:$R1, cls2:$R2)]> {
1739 let OpKey = mnemonic ## cls1;
1744 class CompareRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1745 RegisterOperand cls, Immediate imm>
1746 : InstRI<opcode, (outs), (ins cls:$R1, imm:$I2),
1747 mnemonic#"\t$R1, $I2",
1748 [(operator cls:$R1, imm:$I2)]> {
1752 class CompareRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1753 RegisterOperand cls, Immediate imm>
1754 : InstRIL<opcode, (outs), (ins cls:$R1, imm:$I2),
1755 mnemonic#"\t$R1, $I2",
1756 [(operator cls:$R1, imm:$I2)]> {
1760 class CompareRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1761 RegisterOperand cls, SDPatternOperator load>
1762 : InstRIL<opcode, (outs), (ins cls:$R1, pcrel32:$I2),
1763 mnemonic#"\t$R1, $I2",
1764 [(operator cls:$R1, (load pcrel32:$I2))]> {
1767 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
1768 // However, BDXs have two extra operands and are therefore 6 units more
1770 let AddedComplexity = 7;
1773 class CompareRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1774 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
1775 AddressingMode mode = bdxaddr12only>
1776 : InstRX<opcode, (outs), (ins cls:$R1, mode:$XBD2),
1777 mnemonic#"\t$R1, $XBD2",
1778 [(operator cls:$R1, (load mode:$XBD2))]> {
1779 let OpKey = mnemonic ## cls;
1783 let AccessBytes = bytes;
1786 class CompareRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1787 RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
1788 : InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
1789 mnemonic#"\t$R1, $XBD2",
1790 [(operator cls:$R1, (load bdxaddr12only:$XBD2))]> {
1791 let OpKey = mnemonic ## cls;
1795 let AccessBytes = bytes;
1799 class CompareRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1800 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
1801 AddressingMode mode = bdxaddr20only>
1802 : InstRXY<opcode, (outs), (ins cls:$R1, mode:$XBD2),
1803 mnemonic#"\t$R1, $XBD2",
1804 [(operator cls:$R1, (load mode:$XBD2))]> {
1805 let OpKey = mnemonic ## cls;
1809 let AccessBytes = bytes;
1812 multiclass CompareRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
1813 SDPatternOperator operator, RegisterOperand cls,
1814 SDPatternOperator load, bits<5> bytes> {
1815 let DispKey = mnemonic ## #cls in {
1816 let DispSize = "12" in
1817 def "" : CompareRX<mnemonic, rxOpcode, operator, cls,
1818 load, bytes, bdxaddr12pair>;
1819 let DispSize = "20" in
1820 def Y : CompareRXY<mnemonic#"y", rxyOpcode, operator, cls,
1821 load, bytes, bdxaddr20pair>;
1825 class CompareSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1826 SDPatternOperator load, Immediate imm,
1827 AddressingMode mode = bdaddr12only>
1828 : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
1829 mnemonic#"\t$BD1, $I2",
1830 [(operator (load mode:$BD1), imm:$I2)]> {
1835 class CompareSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1836 SDPatternOperator load, Immediate imm>
1837 : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
1838 mnemonic#"\t$BD1, $I2",
1839 [(operator (load bdaddr12only:$BD1), imm:$I2)]> {
1844 class CompareSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1845 SDPatternOperator load, Immediate imm,
1846 AddressingMode mode = bdaddr20only>
1847 : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
1848 mnemonic#"\t$BD1, $I2",
1849 [(operator (load mode:$BD1), imm:$I2)]> {
1854 multiclass CompareSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
1855 SDPatternOperator operator, SDPatternOperator load,
1857 let DispKey = mnemonic in {
1858 let DispSize = "12" in
1859 def "" : CompareSI<mnemonic, siOpcode, operator, load, imm, bdaddr12pair>;
1860 let DispSize = "20" in
1861 def Y : CompareSIY<mnemonic#"y", siyOpcode, operator, load, imm,
1866 class CompareVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1867 TypedReg tr, bits<4> type>
1868 : InstVRRa<opcode, (outs), (ins tr.op:$V1, tr.op:$V2),
1869 mnemonic#"\t$V1, $V2",
1870 [(operator (tr.vt tr.op:$V1), (tr.vt tr.op:$V2))]> {
1877 class TernaryRRD<string mnemonic, bits<16> opcode,
1878 SDPatternOperator operator, RegisterOperand cls>
1879 : InstRRD<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, cls:$R2),
1880 mnemonic#"r\t$R1, $R3, $R2",
1881 [(set cls:$R1, (operator cls:$R1src, cls:$R3, cls:$R2))]> {
1882 let OpKey = mnemonic ## cls;
1884 let Constraints = "$R1 = $R1src";
1885 let DisableEncoding = "$R1src";
1888 class TernaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1889 RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
1890 : InstRXF<opcode, (outs cls:$R1),
1891 (ins cls:$R1src, cls:$R3, bdxaddr12only:$XBD2),
1892 mnemonic#"\t$R1, $R3, $XBD2",
1893 [(set cls:$R1, (operator cls:$R1src, cls:$R3,
1894 (load bdxaddr12only:$XBD2)))]> {
1895 let OpKey = mnemonic ## cls;
1897 let Constraints = "$R1 = $R1src";
1898 let DisableEncoding = "$R1src";
1900 let AccessBytes = bytes;
1903 class TernaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1904 TypedReg tr1, TypedReg tr2, Immediate imm, Immediate index>
1905 : InstVRIa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V1src, imm:$I2, index:$M3),
1906 mnemonic#"\t$V1, $I2, $M3",
1907 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
1908 imm:$I2, index:$M3)))]> {
1909 let Constraints = "$V1 = $V1src";
1910 let DisableEncoding = "$V1src";
1913 class TernaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1914 TypedReg tr1, TypedReg tr2, bits<4> type>
1915 : InstVRId<opcode, (outs tr1.op:$V1),
1916 (ins tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4),
1917 mnemonic#"\t$V1, $V2, $V3, $I4",
1918 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
1919 (tr2.vt tr2.op:$V3),
1924 class TernaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1925 TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m4or>
1926 : InstVRRa<opcode, (outs tr1.op:$V1),
1927 (ins tr2.op:$V2, imm32zx4:$M4, imm32zx4:$M5),
1928 mnemonic#"\t$V1, $V2, $M4, $M5",
1929 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
1936 class TernaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1937 TypedReg tr1, TypedReg tr2, bits<4> type,
1938 SDPatternOperator m5mask, bits<4> m5or>
1939 : InstVRRb<opcode, (outs tr1.op:$V1),
1940 (ins tr2.op:$V2, tr2.op:$V3, m5mask:$M5),
1941 mnemonic#"\t$V1, $V2, $V3, $M5",
1942 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
1943 (tr2.vt tr2.op:$V3),
1949 multiclass TernaryVRRbSPair<string mnemonic, bits<16> opcode,
1950 SDPatternOperator operator,
1951 SDPatternOperator operator_cc, TypedReg tr1,
1952 TypedReg tr2, bits<4> type, bits<4> m5or> {
1953 def "" : TernaryVRRb<mnemonic, opcode, operator, tr1, tr2, type,
1954 imm32zx4even, !and (m5or, 14)>;
1955 def : InstAlias<mnemonic#"\t$V1, $V2, $V3",
1956 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
1959 def S : TernaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
1960 imm32zx4even, !add(!and (m5or, 14), 1)>;
1961 def : InstAlias<mnemonic#"s\t$V1, $V2, $V3",
1962 (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
1966 class TernaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1967 TypedReg tr1, TypedReg tr2>
1968 : InstVRRc<opcode, (outs tr1.op:$V1),
1969 (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M4),
1970 mnemonic#"\t$V1, $V2, $V3, $M4",
1971 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
1972 (tr2.vt tr2.op:$V3),
1978 class TernaryVRRd<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1979 TypedReg tr1, TypedReg tr2, bits<4> type = 0>
1980 : InstVRRd<opcode, (outs tr1.op:$V1),
1981 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
1982 mnemonic#"\t$V1, $V2, $V3, $V4",
1983 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
1984 (tr2.vt tr2.op:$V3),
1985 (tr1.vt tr1.op:$V4))))]> {
1990 class TernaryVRRe<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1991 TypedReg tr1, TypedReg tr2, bits<4> m5 = 0, bits<4> type = 0>
1992 : InstVRRe<opcode, (outs tr1.op:$V1),
1993 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
1994 mnemonic#"\t$V1, $V2, $V3, $V4",
1995 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
1996 (tr2.vt tr2.op:$V3),
1997 (tr1.vt tr1.op:$V4))))]> {
2002 class TernaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2003 TypedReg tr1, TypedReg tr2, RegisterOperand cls, bits<4> type>
2004 : InstVRSb<opcode, (outs tr1.op:$V1),
2005 (ins tr2.op:$V1src, cls:$R3, shift12only:$BD2),
2006 mnemonic#"\t$V1, $R3, $BD2",
2007 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
2009 shift12only:$BD2)))]> {
2010 let Constraints = "$V1 = $V1src";
2011 let DisableEncoding = "$V1src";
2015 class TernaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes,
2017 : InstVRV<opcode, (outs VR128:$V1),
2018 (ins VR128:$V1src, bdvaddr12only:$VBD2, index:$M3),
2019 mnemonic#"\t$V1, $VBD2, $M3", []> {
2020 let Constraints = "$V1 = $V1src";
2021 let DisableEncoding = "$V1src";
2023 let AccessBytes = bytes;
2026 class TernaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2027 TypedReg tr1, TypedReg tr2, bits<5> bytes, Immediate index>
2028 : InstVRX<opcode, (outs tr1.op:$V1),
2029 (ins tr2.op:$V1src, bdxaddr12only:$XBD2, index:$M3),
2030 mnemonic#"\t$V1, $XBD2, $M3",
2031 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
2032 bdxaddr12only:$XBD2,
2034 let Constraints = "$V1 = $V1src";
2035 let DisableEncoding = "$V1src";
2037 let AccessBytes = bytes;
2040 class QuaternaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2041 TypedReg tr1, TypedReg tr2, bits<4> type>
2042 : InstVRId<opcode, (outs tr1.op:$V1),
2043 (ins tr2.op:$V1src, tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4),
2044 mnemonic#"\t$V1, $V2, $V3, $I4",
2045 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
2046 (tr2.vt tr2.op:$V2),
2047 (tr2.vt tr2.op:$V3),
2049 let Constraints = "$V1 = $V1src";
2050 let DisableEncoding = "$V1src";
2054 class QuaternaryVRRd<string mnemonic, bits<16> opcode,
2055 SDPatternOperator operator, TypedReg tr1, TypedReg tr2,
2056 bits<4> type, SDPatternOperator m6mask, bits<4> m6or>
2057 : InstVRRd<opcode, (outs tr1.op:$V1),
2058 (ins tr2.op:$V2, tr2.op:$V3, tr2.op:$V4, m6mask:$M6),
2059 mnemonic#"\t$V1, $V2, $V3, $V4, $M6",
2060 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2061 (tr2.vt tr2.op:$V3),
2062 (tr2.vt tr2.op:$V4),
2068 multiclass QuaternaryVRRdSPair<string mnemonic, bits<16> opcode,
2069 SDPatternOperator operator,
2070 SDPatternOperator operator_cc, TypedReg tr1,
2071 TypedReg tr2, bits<4> type, bits<4> m6or> {
2072 def "" : QuaternaryVRRd<mnemonic, opcode, operator, tr1, tr2, type,
2073 imm32zx4even, !and (m6or, 14)>;
2074 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4",
2075 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
2076 tr2.op:$V3, tr2.op:$V4, 0)>;
2078 def S : QuaternaryVRRd<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
2079 imm32zx4even, !add (!and (m6or, 14), 1)>;
2080 def : InstAlias<mnemonic#"s\t$V1, $V2, $V3, $V4",
2081 (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
2082 tr2.op:$V3, tr2.op:$V4, 0)>;
2085 class LoadAndOpRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2086 RegisterOperand cls, AddressingMode mode = bdaddr20only>
2087 : InstRSY<opcode, (outs cls:$R1), (ins cls:$R3, mode:$BD2),
2088 mnemonic#"\t$R1, $R3, $BD2",
2089 [(set cls:$R1, (operator mode:$BD2, cls:$R3))]> {
2094 class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2095 RegisterOperand cls, AddressingMode mode = bdaddr12only>
2096 : InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
2097 mnemonic#"\t$R1, $R3, $BD2",
2098 [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
2099 let Constraints = "$R1 = $R1src";
2100 let DisableEncoding = "$R1src";
2105 class CmpSwapRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2106 RegisterOperand cls, AddressingMode mode = bdaddr20only>
2107 : InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
2108 mnemonic#"\t$R1, $R3, $BD2",
2109 [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
2110 let Constraints = "$R1 = $R1src";
2111 let DisableEncoding = "$R1src";
2116 multiclass CmpSwapRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
2117 SDPatternOperator operator, RegisterOperand cls> {
2118 let DispKey = mnemonic ## #cls in {
2119 let DispSize = "12" in
2120 def "" : CmpSwapRS<mnemonic, rsOpcode, operator, cls, bdaddr12pair>;
2121 let DispSize = "20" in
2122 def Y : CmpSwapRSY<mnemonic#"y", rsyOpcode, operator, cls, bdaddr20pair>;
2126 class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
2127 RegisterOperand cls2>
2128 : InstRIEf<opcode, (outs cls1:$R1),
2129 (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
2131 mnemonic#"\t$R1, $R2, $I3, $I4, $I5", []> {
2132 let Constraints = "$R1 = $R1src";
2133 let DisableEncoding = "$R1src";
2136 class PrefetchRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator>
2137 : InstRXY<opcode, (outs), (ins imm32zx4:$R1, bdxaddr20only:$XBD2),
2138 mnemonic##"\t$R1, $XBD2",
2139 [(operator imm32zx4:$R1, bdxaddr20only:$XBD2)]>;
2141 class PrefetchRILPC<string mnemonic, bits<12> opcode,
2142 SDPatternOperator operator>
2143 : InstRIL<opcode, (outs), (ins imm32zx4:$R1, pcrel32:$I2),
2144 mnemonic##"\t$R1, $I2",
2145 [(operator imm32zx4:$R1, pcrel32:$I2)]> {
2146 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
2147 // However, BDXs have two extra operands and are therefore 6 units more
2149 let AddedComplexity = 7;
2152 // A floating-point load-and test operation. Create both a normal unary
2153 // operation and one that acts as a comparison against zero.
2154 multiclass LoadAndTestRRE<string mnemonic, bits<16> opcode,
2155 RegisterOperand cls> {
2156 def "" : UnaryRRE<mnemonic, opcode, null_frag, cls, cls>;
2157 let isCodeGenOnly = 1 in
2158 def Compare : CompareRRE<mnemonic, opcode, null_frag, cls, cls>;
2161 //===----------------------------------------------------------------------===//
2162 // Pseudo instructions
2163 //===----------------------------------------------------------------------===//
2165 // Convenience instructions that get lowered to real instructions
2166 // by either SystemZTargetLowering::EmitInstrWithCustomInserter()
2167 // or SystemZInstrInfo::expandPostRAPseudo().
2169 //===----------------------------------------------------------------------===//
2171 class Pseudo<dag outs, dag ins, list<dag> pattern>
2172 : InstSystemZ<0, outs, ins, "", pattern> {
2174 let isCodeGenOnly = 1;
2177 // Like UnaryRI, but expanded after RA depending on the choice of register.
2178 class UnaryRIPseudo<SDPatternOperator operator, RegisterOperand cls,
2180 : Pseudo<(outs cls:$R1), (ins imm:$I2),
2181 [(set cls:$R1, (operator imm:$I2))]>;
2183 // Like UnaryRXY, but expanded after RA depending on the choice of register.
2184 class UnaryRXYPseudo<string key, SDPatternOperator operator,
2185 RegisterOperand cls, bits<5> bytes,
2186 AddressingMode mode = bdxaddr20only>
2187 : Pseudo<(outs cls:$R1), (ins mode:$XBD2),
2188 [(set cls:$R1, (operator mode:$XBD2))]> {
2189 let OpKey = key ## cls;
2192 let Has20BitOffset = 1;
2194 let AccessBytes = bytes;
2197 // Like UnaryRR, but expanded after RA depending on the choice of registers.
2198 class UnaryRRPseudo<string key, SDPatternOperator operator,
2199 RegisterOperand cls1, RegisterOperand cls2>
2200 : Pseudo<(outs cls1:$R1), (ins cls2:$R2),
2201 [(set cls1:$R1, (operator cls2:$R2))]> {
2202 let OpKey = key ## cls1;
2206 // Like BinaryRI, but expanded after RA depending on the choice of register.
2207 class BinaryRIPseudo<SDPatternOperator operator, RegisterOperand cls,
2209 : Pseudo<(outs cls:$R1), (ins cls:$R1src, imm:$I2),
2210 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
2211 let Constraints = "$R1 = $R1src";
2214 // Like BinaryRIE, but expanded after RA depending on the choice of register.
2215 class BinaryRIEPseudo<SDPatternOperator operator, RegisterOperand cls,
2217 : Pseudo<(outs cls:$R1), (ins cls:$R3, imm:$I2),
2218 [(set cls:$R1, (operator cls:$R3, imm:$I2))]>;
2220 // Like BinaryRIAndK, but expanded after RA depending on the choice of register.
2221 multiclass BinaryRIAndKPseudo<string key, SDPatternOperator operator,
2222 RegisterOperand cls, Immediate imm> {
2223 let NumOpsKey = key in {
2224 let NumOpsValue = "3" in
2225 def K : BinaryRIEPseudo<null_frag, cls, imm>,
2226 Requires<[FeatureHighWord, FeatureDistinctOps]>;
2227 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
2228 def "" : BinaryRIPseudo<operator, cls, imm>,
2229 Requires<[FeatureHighWord]>;
2233 // Like CompareRI, but expanded after RA depending on the choice of register.
2234 class CompareRIPseudo<SDPatternOperator operator, RegisterOperand cls,
2236 : Pseudo<(outs), (ins cls:$R1, imm:$I2), [(operator cls:$R1, imm:$I2)]>;
2238 // Like CompareRXY, but expanded after RA depending on the choice of register.
2239 class CompareRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
2240 SDPatternOperator load, bits<5> bytes,
2241 AddressingMode mode = bdxaddr20only>
2242 : Pseudo<(outs), (ins cls:$R1, mode:$XBD2),
2243 [(operator cls:$R1, (load mode:$XBD2))]> {
2245 let Has20BitOffset = 1;
2247 let AccessBytes = bytes;
2250 // Like StoreRXY, but expanded after RA depending on the choice of register.
2251 class StoreRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
2252 bits<5> bytes, AddressingMode mode = bdxaddr20only>
2253 : Pseudo<(outs), (ins cls:$R1, mode:$XBD2),
2254 [(operator cls:$R1, mode:$XBD2)]> {
2256 let Has20BitOffset = 1;
2258 let AccessBytes = bytes;
2261 // Like RotateSelectRIEf, but expanded after RA depending on the choice
2263 class RotateSelectRIEfPseudo<RegisterOperand cls1, RegisterOperand cls2>
2264 : Pseudo<(outs cls1:$R1),
2265 (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
2268 let Constraints = "$R1 = $R1src";
2269 let DisableEncoding = "$R1src";
2272 // Implements "$dst = $cc & (8 >> CC) ? $src1 : $src2", where CC is
2273 // the value of the PSW's 2-bit condition code field.
2274 class SelectWrapper<RegisterOperand cls>
2275 : Pseudo<(outs cls:$dst),
2276 (ins cls:$src1, cls:$src2, imm32zx4:$valid, imm32zx4:$cc),
2277 [(set cls:$dst, (z_select_ccmask cls:$src1, cls:$src2,
2278 imm32zx4:$valid, imm32zx4:$cc))]> {
2279 let usesCustomInserter = 1;
2280 // Although the instructions used by these nodes do not in themselves
2281 // change CC, the insertion requires new blocks, and CC cannot be live
2287 // Stores $new to $addr if $cc is true ("" case) or false (Inv case).
2288 multiclass CondStores<RegisterOperand cls, SDPatternOperator store,
2289 SDPatternOperator load, AddressingMode mode> {
2290 let Defs = [CC], Uses = [CC], usesCustomInserter = 1 in {
2291 def "" : Pseudo<(outs),
2292 (ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc),
2293 [(store (z_select_ccmask cls:$new, (load mode:$addr),
2294 imm32zx4:$valid, imm32zx4:$cc),
2296 def Inv : Pseudo<(outs),
2297 (ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc),
2298 [(store (z_select_ccmask (load mode:$addr), cls:$new,
2299 imm32zx4:$valid, imm32zx4:$cc),
2304 // OPERATOR is ATOMIC_SWAP or an ATOMIC_LOAD_* operation. PAT and OPERAND
2305 // describe the second (non-memory) operand.
2306 class AtomicLoadBinary<SDPatternOperator operator, RegisterOperand cls,
2307 dag pat, DAGOperand operand>
2308 : Pseudo<(outs cls:$dst), (ins bdaddr20only:$ptr, operand:$src2),
2309 [(set cls:$dst, (operator bdaddr20only:$ptr, pat))]> {
2311 let Has20BitOffset = 1;
2314 let usesCustomInserter = 1;
2317 // Specializations of AtomicLoadWBinary.
2318 class AtomicLoadBinaryReg32<SDPatternOperator operator>
2319 : AtomicLoadBinary<operator, GR32, (i32 GR32:$src2), GR32>;
2320 class AtomicLoadBinaryImm32<SDPatternOperator operator, Immediate imm>
2321 : AtomicLoadBinary<operator, GR32, (i32 imm:$src2), imm>;
2322 class AtomicLoadBinaryReg64<SDPatternOperator operator>
2323 : AtomicLoadBinary<operator, GR64, (i64 GR64:$src2), GR64>;
2324 class AtomicLoadBinaryImm64<SDPatternOperator operator, Immediate imm>
2325 : AtomicLoadBinary<operator, GR64, (i64 imm:$src2), imm>;
2327 // OPERATOR is ATOMIC_SWAPW or an ATOMIC_LOADW_* operation. PAT and OPERAND
2328 // describe the second (non-memory) operand.
2329 class AtomicLoadWBinary<SDPatternOperator operator, dag pat,
2331 : Pseudo<(outs GR32:$dst),
2332 (ins bdaddr20only:$ptr, operand:$src2, ADDR32:$bitshift,
2333 ADDR32:$negbitshift, uimm32:$bitsize),
2334 [(set GR32:$dst, (operator bdaddr20only:$ptr, pat, ADDR32:$bitshift,
2335 ADDR32:$negbitshift, uimm32:$bitsize))]> {
2337 let Has20BitOffset = 1;
2340 let usesCustomInserter = 1;
2343 // Specializations of AtomicLoadWBinary.
2344 class AtomicLoadWBinaryReg<SDPatternOperator operator>
2345 : AtomicLoadWBinary<operator, (i32 GR32:$src2), GR32>;
2346 class AtomicLoadWBinaryImm<SDPatternOperator operator, Immediate imm>
2347 : AtomicLoadWBinary<operator, (i32 imm:$src2), imm>;
2349 // Define an instruction that operates on two fixed-length blocks of memory,
2350 // and associated pseudo instructions for operating on blocks of any size.
2351 // The Sequence form uses a straight-line sequence of instructions and
2352 // the Loop form uses a loop of length-256 instructions followed by
2353 // another instruction to handle the excess.
2354 multiclass MemorySS<string mnemonic, bits<8> opcode,
2355 SDPatternOperator sequence, SDPatternOperator loop> {
2356 def "" : InstSS<opcode, (outs), (ins bdladdr12onlylen8:$BDL1,
2358 mnemonic##"\t$BDL1, $BD2", []>;
2359 let usesCustomInserter = 1 in {
2360 def Sequence : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
2362 [(sequence bdaddr12only:$dest, bdaddr12only:$src,
2364 def Loop : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
2365 imm64:$length, GR64:$count256),
2366 [(loop bdaddr12only:$dest, bdaddr12only:$src,
2367 imm64:$length, GR64:$count256)]>;
2371 // Define an instruction that operates on two strings, both terminated
2372 // by the character in R0. The instruction processes a CPU-determinated
2373 // number of bytes at a time and sets CC to 3 if the instruction needs
2374 // to be repeated. Also define a pseudo instruction that represents
2375 // the full loop (the main instruction plus the branch on CC==3).
2376 multiclass StringRRE<string mnemonic, bits<16> opcode,
2377 SDPatternOperator operator> {
2378 def "" : InstRRE<opcode, (outs GR64:$R1, GR64:$R2),
2379 (ins GR64:$R1src, GR64:$R2src),
2380 mnemonic#"\t$R1, $R2", []> {
2381 let Constraints = "$R1 = $R1src, $R2 = $R2src";
2382 let DisableEncoding = "$R1src, $R2src";
2384 let usesCustomInserter = 1 in
2385 def Loop : Pseudo<(outs GR64:$end),
2386 (ins GR64:$start1, GR64:$start2, GR32:$char),
2387 [(set GR64:$end, (operator GR64:$start1, GR64:$start2,
2391 // A pseudo instruction that is a direct alias of a real instruction.
2392 // These aliases are used in cases where a particular register operand is
2393 // fixed or where the same instruction is used with different register sizes.
2394 // The size parameter is the size in bytes of the associated real instruction.
2395 class Alias<int size, dag outs, dag ins, list<dag> pattern>
2396 : InstSystemZ<size, outs, ins, "", pattern> {
2398 let isCodeGenOnly = 1;
2401 class UnaryAliasVRS<RegisterOperand cls1, RegisterOperand cls2>
2402 : Alias<6, (outs cls1:$src1), (ins cls2:$src2), []>;
2404 // An alias of a BinaryRI, but with different register sizes.
2405 class BinaryAliasRI<SDPatternOperator operator, RegisterOperand cls,
2407 : Alias<4, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
2408 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
2409 let Constraints = "$R1 = $R1src";
2412 // An alias of a BinaryRIL, but with different register sizes.
2413 class BinaryAliasRIL<SDPatternOperator operator, RegisterOperand cls,
2415 : Alias<6, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
2416 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
2417 let Constraints = "$R1 = $R1src";
2420 // An alias of a BinaryVRRf, but with different register sizes.
2421 class BinaryAliasVRRf<RegisterOperand cls>
2422 : Alias<6, (outs VR128:$V1), (ins cls:$R2, cls:$R3), []>;
2424 // An alias of a CompareRI, but with different register sizes.
2425 class CompareAliasRI<SDPatternOperator operator, RegisterOperand cls,
2427 : Alias<4, (outs), (ins cls:$R1, imm:$I2), [(operator cls:$R1, imm:$I2)]> {
2431 // An alias of a RotateSelectRIEf, but with different register sizes.
2432 class RotateSelectAliasRIEf<RegisterOperand cls1, RegisterOperand cls2>
2433 : Alias<6, (outs cls1:$R1),
2434 (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
2435 imm32zx6:$I5), []> {
2436 let Constraints = "$R1 = $R1src";