1 //==- SystemZInstrFormats.td - SystemZ Instruction Formats --*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Basic SystemZ instruction definition
12 //===----------------------------------------------------------------------===//
14 class InstSystemZ<int size, dag outs, dag ins, string asmstr,
15 list<dag> pattern> : Instruction {
16 let Namespace = "SystemZ";
18 dag OutOperandList = outs;
19 dag InOperandList = ins;
21 let Pattern = pattern;
22 let AsmString = asmstr;
24 // Used to identify a group of related instructions, such as ST and STY.
27 // "12" for an instruction that has a ...Y equivalent, "20" for that
29 string PairType = "none";
31 // True if this instruction is a simple D(X,B) load of a register
32 // (with no sign or zero extension).
33 bit SimpleBDXLoad = 0;
35 // True if this instruction is a simple D(X,B) store of a register
36 // (with no truncation).
37 bit SimpleBDXStore = 0;
39 // True if this instruction has a 20-bit displacement field.
40 bit Has20BitOffset = 0;
42 // True if addresses in this instruction have an index register.
45 // True if this is a 128-bit pseudo instruction that combines two 64-bit
49 let TSFlags{0} = SimpleBDXLoad;
50 let TSFlags{1} = SimpleBDXStore;
51 let TSFlags{2} = Has20BitOffset;
52 let TSFlags{3} = HasIndex;
53 let TSFlags{4} = Is128Bit;
56 //===----------------------------------------------------------------------===//
57 // Mappings between instructions
58 //===----------------------------------------------------------------------===//
60 // Return the version of an instruction that has an unsigned 12-bit
62 def getDisp12Opcode : InstrMapping {
63 let FilterClass = "InstSystemZ";
64 let RowFields = ["Function"];
65 let ColFields = ["PairType"];
67 let ValueCols = [["12"]];
70 // Return the version of an instruction that has a signed 20-bit displacement.
71 def getDisp20Opcode : InstrMapping {
72 let FilterClass = "InstSystemZ";
73 let RowFields = ["Function"];
74 let ColFields = ["PairType"];
76 let ValueCols = [["20"]];
79 //===----------------------------------------------------------------------===//
80 // Instruction formats
81 //===----------------------------------------------------------------------===//
83 // Formats are specified using operand field declarations of the form:
85 // bits<4> Rn : register input or output for operand n
86 // bits<m> In : immediate value of width m for operand n
87 // bits<4> BDn : address operand n, which has a base and a displacement
88 // bits<m> XBDn : address operand n, which has an index, a base and a
90 // bits<4> Xn : index register for address operand n
91 // bits<4> Mn : mode value for operand n
93 // The operand numbers ("n" in the list above) follow the architecture manual.
94 // Assembly operands sometimes have a different order; in particular, R3 often
95 // is often written between operands 1 and 2.
97 //===----------------------------------------------------------------------===//
99 class InstRI<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
100 : InstSystemZ<4, outs, ins, asmstr, pattern> {
102 field bits<32> SoftFail = 0;
107 let Inst{31-24} = op{11-4};
108 let Inst{23-20} = R1;
109 let Inst{19-16} = op{3-0};
113 class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
114 : InstSystemZ<6, outs, ins, asmstr, pattern> {
116 field bits<48> SoftFail = 0;
124 let Inst{47-40} = op{15-8};
125 let Inst{39-36} = R1;
126 let Inst{35-32} = R2;
127 let Inst{31-24} = I3;
128 let Inst{23-16} = I4;
130 let Inst{7-0} = op{7-0};
133 class InstRIL<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
134 : InstSystemZ<6, outs, ins, asmstr, pattern> {
136 field bits<48> SoftFail = 0;
141 let Inst{47-40} = op{11-4};
142 let Inst{39-36} = R1;
143 let Inst{35-32} = op{3-0};
147 class InstRR<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
148 : InstSystemZ<2, outs, ins, asmstr, pattern> {
150 field bits<16> SoftFail = 0;
160 class InstRRD<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
161 : InstSystemZ<4, outs, ins, asmstr, pattern> {
163 field bits<32> SoftFail = 0;
169 let Inst{31-16} = op;
170 let Inst{15-12} = R1;
176 class InstRRE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
177 : InstSystemZ<4, outs, ins, asmstr, pattern> {
179 field bits<32> SoftFail = 0;
184 let Inst{31-16} = op;
190 class InstRRF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
191 : InstSystemZ<4, outs, ins, asmstr, pattern> {
193 field bits<32> SoftFail = 0;
199 let Inst{31-16} = op;
200 let Inst{15-12} = R3;
206 class InstRX<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
207 : InstSystemZ<4, outs, ins, asmstr, pattern> {
209 field bits<32> SoftFail = 0;
214 let Inst{31-24} = op;
215 let Inst{23-20} = R1;
216 let Inst{19-0} = XBD2;
221 class InstRXE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
222 : InstSystemZ<6, outs, ins, asmstr, pattern> {
224 field bits<48> SoftFail = 0;
229 let Inst{47-40} = op{15-8};
230 let Inst{39-36} = R1;
231 let Inst{35-16} = XBD2;
233 let Inst{7-0} = op{7-0};
238 class InstRXF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
239 : InstSystemZ<6, outs, ins, asmstr, pattern> {
241 field bits<48> SoftFail = 0;
247 let Inst{47-40} = op{15-8};
248 let Inst{39-36} = R3;
249 let Inst{35-16} = XBD2;
250 let Inst{15-12} = R1;
252 let Inst{7-0} = op{7-0};
257 class InstRXY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
258 : InstSystemZ<6, outs, ins, asmstr, pattern> {
260 field bits<48> SoftFail = 0;
265 let Inst{47-40} = op{15-8};
266 let Inst{39-36} = R1;
267 let Inst{35-8} = XBD2;
268 let Inst{7-0} = op{7-0};
270 let Has20BitOffset = 1;
274 class InstRS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
275 : InstSystemZ<4, outs, ins, asmstr, pattern> {
277 field bits<32> SoftFail = 0;
283 let Inst{31-24} = op;
284 let Inst{23-20} = R1;
285 let Inst{19-16} = R3;
286 let Inst{15-0} = BD2;
289 class InstRSY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
290 : InstSystemZ<6, outs, ins, asmstr, pattern> {
292 field bits<48> SoftFail = 0;
298 let Inst{47-40} = op{15-8};
299 let Inst{39-36} = R1;
300 let Inst{35-32} = R3;
301 let Inst{31-8} = BD2;
302 let Inst{7-0} = op{7-0};
304 let Has20BitOffset = 1;
307 class InstSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
308 : InstSystemZ<4, outs, ins, asmstr, pattern> {
310 field bits<32> SoftFail = 0;
315 let Inst{31-24} = op;
316 let Inst{23-16} = I2;
317 let Inst{15-0} = BD1;
320 class InstSIL<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
321 : InstSystemZ<6, outs, ins, asmstr, pattern> {
323 field bits<48> SoftFail = 0;
328 let Inst{47-32} = op;
329 let Inst{31-16} = BD1;
333 class InstSIY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
334 : InstSystemZ<6, outs, ins, asmstr, pattern> {
336 field bits<48> SoftFail = 0;
341 let Inst{47-40} = op{15-8};
342 let Inst{39-32} = I2;
343 let Inst{31-8} = BD1;
344 let Inst{7-0} = op{7-0};
346 let Has20BitOffset = 1;
349 //===----------------------------------------------------------------------===//
350 // Instruction definitions with semantics
351 //===----------------------------------------------------------------------===//
353 // These classes have the form <Category><Format>, where <Format> is one
354 // of the formats defined above and where <Category> describes the inputs
355 // and outputs. <Category> can be one of:
358 // One register output operand and no input operands.
361 // One register or immediate input operand and one address input operand.
362 // The instruction stores the first operand to the address.
364 // This category is used for both pure and truncating stores.
367 // One address input operand and two explicit output operands.
368 // The instruction loads a range of registers from the address,
369 // with the explicit operands giving the first and last register
370 // to load. Other loaded registers are added as implicit definitions.
373 // Two explicit input register operands and an address operand.
374 // The instruction stores a range of registers to the address,
375 // with the explicit operands giving the first and last register
376 // to store. Other stored registers are added as implicit uses.
379 // One register output operand and one input operand. The input
380 // operand may be a register, immediate or memory.
383 // One register output operand and two input operands. The first
384 // input operand is always a register and he second may be a register,
385 // immediate or memory.
388 // One register output operand and two input operands. The first
389 // input operand is a register and the second has the same form as
390 // an address (although it isn't actually used to address memory).
393 // Two input operands. The first operand is always a register,
394 // the second may be a register, immediate or memory.
397 // One register output operand and three register input operands.
400 // One output operand and three input operands. The first two
401 // operands are registers and the third is an address. The instruction
402 // both reads from and writes to the address.
405 // One output operand and five input operands. The first two operands
406 // are registers and the other three are immediates.
408 // The format determines which input operands are tied to output operands,
409 // and also determines the shape of any address operand.
411 // Multiclasses of the form <Category><Format>Pair define two instructions,
412 // one with <Category><Format> and one with <Category><Format>Y. The name
413 // of the first instruction has no suffix, the name of the second has
416 //===----------------------------------------------------------------------===//
418 class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
420 : InstRRE<opcode, (outs cls:$R1), (ins),
422 [(set cls:$R1, src)]> {
426 class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
427 : InstRSY<opcode, (outs cls:$R1, cls:$R3), (ins bdaddr20only:$BD2),
428 mnemonic#"\t$R1, $R3, $BD2", []> {
432 class StoreRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
434 : InstRIL<opcode, (outs), (ins cls:$R1, pcrel32:$I2),
435 mnemonic#"\t$R1, $I2",
436 [(operator cls:$R1, pcrel32:$I2)]> {
438 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
439 // However, BDXs have two extra operands and are therefore 6 units more
441 let AddedComplexity = 7;
444 class StoreRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
445 RegisterOperand cls, AddressingMode mode = bdxaddr12only>
446 : InstRX<opcode, (outs), (ins cls:$R1, mode:$XBD2),
447 mnemonic#"\t$R1, $XBD2",
448 [(operator cls:$R1, mode:$XBD2)]> {
452 class StoreRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
453 RegisterOperand cls, AddressingMode mode = bdxaddr20only>
454 : InstRXY<opcode, (outs), (ins cls:$R1, mode:$XBD2),
455 mnemonic#"\t$R1, $XBD2",
456 [(operator cls:$R1, mode:$XBD2)]> {
460 multiclass StoreRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
461 SDPatternOperator operator, RegisterOperand cls> {
462 let Function = mnemonic ## #cls in {
463 let PairType = "12" in
464 def "" : StoreRX<mnemonic, rxOpcode, operator, cls, bdxaddr12pair>;
465 let PairType = "20" in
466 def Y : StoreRXY<mnemonic#"y", rxyOpcode, operator, cls, bdxaddr20pair>;
470 class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
471 : InstRSY<opcode, (outs), (ins cls:$R1, cls:$R3, bdaddr20only:$BD2),
472 mnemonic#"\t$R1, $R3, $BD2", []> {
476 class StoreSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
477 Immediate imm, AddressingMode mode = bdaddr12only>
478 : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
479 mnemonic#"\t$BD1, $I2",
480 [(operator imm:$I2, mode:$BD1)]> {
484 class StoreSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
485 Immediate imm, AddressingMode mode = bdaddr20only>
486 : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
487 mnemonic#"\t$BD1, $I2",
488 [(operator imm:$I2, mode:$BD1)]> {
492 class StoreSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
494 : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
495 mnemonic#"\t$BD1, $I2",
496 [(operator imm:$I2, bdaddr12only:$BD1)]> {
500 multiclass StoreSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
501 SDPatternOperator operator, Immediate imm> {
502 let Function = mnemonic in {
503 let PairType = "12" in
504 def "" : StoreSI<mnemonic, siOpcode, operator, imm, bdaddr12pair>;
505 let PairType = "20" in
506 def Y : StoreSIY<mnemonic#"y", siyOpcode, operator, imm, bdaddr20pair>;
510 class UnaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
511 RegisterOperand cls1, RegisterOperand cls2>
512 : InstRR<opcode, (outs cls1:$R1), (ins cls2:$R2),
513 mnemonic#"\t$R1, $R2",
514 [(set cls1:$R1, (operator cls2:$R2))]>;
516 class UnaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
517 RegisterOperand cls1, RegisterOperand cls2>
518 : InstRRE<opcode, (outs cls1:$R1), (ins cls2:$R2),
519 mnemonic#"\t$R1, $R2",
520 [(set cls1:$R1, (operator cls2:$R2))]>;
522 class UnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
523 RegisterOperand cls2>
524 : InstRRF<opcode, (outs cls1:$R1), (ins uimm8zx4:$R3, cls2:$R2),
525 mnemonic#"\t$R1, $R3, $R2", []>;
527 class UnaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
528 RegisterOperand cls, Immediate imm>
529 : InstRI<opcode, (outs cls:$R1), (ins imm:$I2),
530 mnemonic#"\t$R1, $I2",
531 [(set cls:$R1, (operator imm:$I2))]>;
533 class UnaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
534 RegisterOperand cls, Immediate imm>
535 : InstRIL<opcode, (outs cls:$R1), (ins imm:$I2),
536 mnemonic#"\t$R1, $I2",
537 [(set cls:$R1, (operator imm:$I2))]>;
539 class UnaryRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
541 : InstRIL<opcode, (outs cls:$R1), (ins pcrel32:$I2),
542 mnemonic#"\t$R1, $I2",
543 [(set cls:$R1, (operator pcrel32:$I2))]> {
545 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
546 // However, BDXs have two extra operands and are therefore 6 units more
548 let AddedComplexity = 7;
551 class UnaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
552 RegisterOperand cls, AddressingMode mode = bdxaddr12only>
553 : InstRX<opcode, (outs cls:$R1), (ins mode:$XBD2),
554 mnemonic#"\t$R1, $XBD2",
555 [(set cls:$R1, (operator mode:$XBD2))]> {
559 class UnaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
561 : InstRXE<opcode, (outs cls:$R1), (ins bdxaddr12only:$XBD2),
562 mnemonic#"\t$R1, $XBD2",
563 [(set cls:$R1, (operator bdxaddr12only:$XBD2))]> {
567 class UnaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
568 RegisterOperand cls, AddressingMode mode = bdxaddr20only>
569 : InstRXY<opcode, (outs cls:$R1), (ins mode:$XBD2),
570 mnemonic#"\t$R1, $XBD2",
571 [(set cls:$R1, (operator mode:$XBD2))]> {
575 multiclass UnaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
576 SDPatternOperator operator, RegisterOperand cls> {
577 let Function = mnemonic ## #cls in {
578 let PairType = "12" in
579 def "" : UnaryRX<mnemonic, rxOpcode, operator, cls, bdxaddr12pair>;
580 let PairType = "20" in
581 def Y : UnaryRXY<mnemonic#"y", rxyOpcode, operator, cls, bdxaddr20pair>;
585 class BinaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
586 RegisterOperand cls1, RegisterOperand cls2>
587 : InstRR<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
588 mnemonic#"\t$R1, $R2",
589 [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
590 let Constraints = "$R1 = $R1src";
591 let DisableEncoding = "$R1src";
594 class BinaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
595 RegisterOperand cls1, RegisterOperand cls2>
596 : InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
597 mnemonic#"\t$R1, $R2",
598 [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
599 let Constraints = "$R1 = $R1src";
600 let DisableEncoding = "$R1src";
603 class BinaryRRF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
604 RegisterOperand cls1, RegisterOperand cls2>
605 : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R3, cls2:$R2),
606 mnemonic#"\t$R1, $R3, $R2",
607 [(set cls1:$R1, (operator cls1:$R3, cls2:$R2))]>;
609 class BinaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
610 RegisterOperand cls, Immediate imm>
611 : InstRI<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
612 mnemonic#"\t$R1, $I2",
613 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
614 let Constraints = "$R1 = $R1src";
615 let DisableEncoding = "$R1src";
618 class BinaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
619 RegisterOperand cls, Immediate imm>
620 : InstRIL<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
621 mnemonic#"\t$R1, $I2",
622 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
623 let Constraints = "$R1 = $R1src";
624 let DisableEncoding = "$R1src";
627 class BinaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
628 RegisterOperand cls, SDPatternOperator load,
629 AddressingMode mode = bdxaddr12only>
630 : InstRX<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
631 mnemonic#"\t$R1, $XBD2",
632 [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
633 let Constraints = "$R1 = $R1src";
634 let DisableEncoding = "$R1src";
638 class BinaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
639 RegisterOperand cls, SDPatternOperator load>
640 : InstRXE<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr12only:$XBD2),
641 mnemonic#"\t$R1, $XBD2",
642 [(set cls:$R1, (operator cls:$R1src,
643 (load bdxaddr12only:$XBD2)))]> {
644 let Constraints = "$R1 = $R1src";
645 let DisableEncoding = "$R1src";
649 class BinaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
650 RegisterOperand cls, SDPatternOperator load,
651 AddressingMode mode = bdxaddr20only>
652 : InstRXY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
653 mnemonic#"\t$R1, $XBD2",
654 [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
655 let Constraints = "$R1 = $R1src";
656 let DisableEncoding = "$R1src";
660 multiclass BinaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
661 SDPatternOperator operator, RegisterOperand cls,
662 SDPatternOperator load> {
663 let Function = mnemonic ## #cls in {
664 let PairType = "12" in
665 def "" : BinaryRX<mnemonic, rxOpcode, operator, cls, load, bdxaddr12pair>;
666 let PairType = "20" in
667 def Y : BinaryRXY<mnemonic#"y", rxyOpcode, operator, cls, load,
672 class BinarySI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
673 Operand imm, AddressingMode mode = bdaddr12only>
674 : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
675 mnemonic#"\t$BD1, $I2",
676 [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
681 class BinarySIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
682 Operand imm, AddressingMode mode = bdaddr20only>
683 : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
684 mnemonic#"\t$BD1, $I2",
685 [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
690 multiclass BinarySIPair<string mnemonic, bits<8> siOpcode,
691 bits<16> siyOpcode, SDPatternOperator operator,
693 let Function = mnemonic ## #cls in {
694 let PairType = "12" in
695 def "" : BinarySI<mnemonic, siOpcode, operator, imm, bdaddr12pair>;
696 let PairType = "20" in
697 def Y : BinarySIY<mnemonic#"y", siyOpcode, operator, imm, bdaddr20pair>;
701 class ShiftRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
702 RegisterOperand cls, AddressingMode mode>
703 : InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2),
704 mnemonic#"\t$R1, $BD2",
705 [(set cls:$R1, (operator cls:$R1src, mode:$BD2))]> {
707 let Constraints = "$R1 = $R1src";
708 let DisableEncoding = "$R1src";
711 class ShiftRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
712 RegisterOperand cls, AddressingMode mode>
713 : InstRSY<opcode, (outs cls:$R1), (ins cls:$R3, mode:$BD2),
714 mnemonic#"\t$R1, $R3, $BD2",
715 [(set cls:$R1, (operator cls:$R3, mode:$BD2))]>;
717 class CompareRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
718 RegisterOperand cls1, RegisterOperand cls2>
719 : InstRR<opcode, (outs), (ins cls1:$R1, cls2:$R2),
720 mnemonic#"\t$R1, $R2",
721 [(operator cls1:$R1, cls2:$R2)]>;
723 class CompareRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
724 RegisterOperand cls1, RegisterOperand cls2>
725 : InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2),
726 mnemonic#"\t$R1, $R2",
727 [(operator cls1:$R1, cls2:$R2)]>;
729 class CompareRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
730 RegisterOperand cls, Immediate imm>
731 : InstRI<opcode, (outs), (ins cls:$R1, imm:$I2),
732 mnemonic#"\t$R1, $I2",
733 [(operator cls:$R1, imm:$I2)]>;
735 class CompareRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
736 RegisterOperand cls, Immediate imm>
737 : InstRIL<opcode, (outs), (ins cls:$R1, imm:$I2),
738 mnemonic#"\t$R1, $I2",
739 [(operator cls:$R1, imm:$I2)]>;
741 class CompareRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
742 RegisterOperand cls, SDPatternOperator load>
743 : InstRIL<opcode, (outs), (ins cls:$R1, pcrel32:$I2),
744 mnemonic#"\t$R1, $I2",
745 [(operator cls:$R1, (load pcrel32:$I2))]> {
747 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
748 // However, BDXs have two extra operands and are therefore 6 units more
750 let AddedComplexity = 7;
753 class CompareRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
754 RegisterOperand cls, SDPatternOperator load,
755 AddressingMode mode = bdxaddr12only>
756 : InstRX<opcode, (outs), (ins cls:$R1, mode:$XBD2),
757 mnemonic#"\t$R1, $XBD2",
758 [(operator cls:$R1, (load mode:$XBD2))]> {
762 class CompareRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
763 RegisterOperand cls, SDPatternOperator load>
764 : InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
765 mnemonic#"\t$R1, $XBD2",
766 [(operator cls:$R1, (load bdxaddr12only:$XBD2))]> {
770 class CompareRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
771 RegisterOperand cls, SDPatternOperator load,
772 AddressingMode mode = bdxaddr20only>
773 : InstRXY<opcode, (outs), (ins cls:$R1, mode:$XBD2),
774 mnemonic#"\t$R1, $XBD2",
775 [(operator cls:$R1, (load mode:$XBD2))]> {
779 multiclass CompareRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
780 SDPatternOperator operator, RegisterOperand cls,
781 SDPatternOperator load> {
782 let Function = mnemonic ## #cls in {
783 let PairType = "12" in
784 def "" : CompareRX<mnemonic, rxOpcode, operator, cls,
785 load, bdxaddr12pair>;
786 let PairType = "20" in
787 def Y : CompareRXY<mnemonic#"y", rxyOpcode, operator, cls,
788 load, bdxaddr20pair>;
792 class CompareSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
793 SDPatternOperator load, Immediate imm,
794 AddressingMode mode = bdaddr12only>
795 : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
796 mnemonic#"\t$BD1, $I2",
797 [(operator (load mode:$BD1), imm:$I2)]> {
801 class CompareSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
802 SDPatternOperator load, Immediate imm>
803 : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
804 mnemonic#"\t$BD1, $I2",
805 [(operator (load bdaddr12only:$BD1), imm:$I2)]> {
809 class CompareSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
810 SDPatternOperator load, Immediate imm,
811 AddressingMode mode = bdaddr20only>
812 : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
813 mnemonic#"\t$BD1, $I2",
814 [(operator (load mode:$BD1), imm:$I2)]> {
818 multiclass CompareSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
819 SDPatternOperator operator, SDPatternOperator load,
821 let Function = mnemonic in {
822 let PairType = "12" in
823 def "" : CompareSI<mnemonic, siOpcode, operator, load, imm, bdaddr12pair>;
824 let PairType = "20" in
825 def Y : CompareSIY<mnemonic#"y", siyOpcode, operator, load, imm,
830 class TernaryRRD<string mnemonic, bits<16> opcode,
831 SDPatternOperator operator, RegisterOperand cls>
832 : InstRRD<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, cls:$R2),
833 mnemonic#"\t$R1, $R3, $R2",
834 [(set cls:$R1, (operator cls:$R1src, cls:$R3, cls:$R2))]> {
835 let Constraints = "$R1 = $R1src";
836 let DisableEncoding = "$R1src";
839 class TernaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
840 RegisterOperand cls, SDPatternOperator load>
841 : InstRXF<opcode, (outs cls:$R1),
842 (ins cls:$R1src, cls:$R3, bdxaddr12only:$XBD2),
843 mnemonic#"\t$R1, $R3, $XBD2",
844 [(set cls:$R1, (operator cls:$R1src, cls:$R3,
845 (load bdxaddr12only:$XBD2)))]> {
846 let Constraints = "$R1 = $R1src";
847 let DisableEncoding = "$R1src";
851 class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
852 RegisterOperand cls, AddressingMode mode = bdaddr12only>
853 : InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
854 mnemonic#"\t$R1, $R3, $BD2",
855 [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
856 let Constraints = "$R1 = $R1src";
857 let DisableEncoding = "$R1src";
862 class CmpSwapRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
863 RegisterOperand cls, AddressingMode mode = bdaddr20only>
864 : InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
865 mnemonic#"\t$R1, $R3, $BD2",
866 [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
867 let Constraints = "$R1 = $R1src";
868 let DisableEncoding = "$R1src";
873 multiclass CmpSwapRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
874 SDPatternOperator operator, RegisterOperand cls> {
875 let Function = mnemonic ## #cls in {
876 let PairType = "12" in
877 def "" : CmpSwapRS<mnemonic, rsOpcode, operator, cls, bdaddr12pair>;
878 let PairType = "20" in
879 def Y : CmpSwapRSY<mnemonic#"y", rsyOpcode, operator, cls, bdaddr20pair>;
883 class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
884 RegisterOperand cls2>
885 : InstRIEf<opcode, (outs cls1:$R1),
886 (ins cls1:$R1src, cls2:$R2,
887 uimm8zx6:$I3, uimm8zx6:$I4, uimm8zx6:$I5),
888 mnemonic#"\t$R1, $R2, $I3, $I4, $I5", []> {
889 let Constraints = "$R1 = $R1src";
890 let DisableEncoding = "$R1src";
893 //===----------------------------------------------------------------------===//
894 // Pseudo instructions
895 //===----------------------------------------------------------------------===//
897 // Convenience instructions that get lowered to real instructions
898 // by either SystemZTargetLowering::EmitInstrWithCustomInserter()
899 // or SystemZInstrInfo::expandPostRAPseudo().
901 //===----------------------------------------------------------------------===//
903 class Pseudo<dag outs, dag ins, list<dag> pattern>
904 : InstSystemZ<0, outs, ins, "", pattern> {
906 let isCodeGenOnly = 1;
909 // Implements "$dst = $cc & (8 >> CC) ? $src1 : $src2", where CC is
910 // the value of the PSW's 2-bit condition code field.
911 class SelectWrapper<RegisterOperand cls>
912 : Pseudo<(outs cls:$dst), (ins cls:$src1, cls:$src2, i8imm:$cc),
913 [(set cls:$dst, (z_select_ccmask cls:$src1, cls:$src2, imm:$cc))]> {
914 let usesCustomInserter = 1;
915 // Although the instructions used by these nodes do not in themselves
916 // change CC, the insertion requires new blocks, and CC cannot be live
922 // OPERATOR is ATOMIC_SWAP or an ATOMIC_LOAD_* operation. PAT and OPERAND
923 // describe the second (non-memory) operand.
924 class AtomicLoadBinary<SDPatternOperator operator, RegisterOperand cls,
925 dag pat, DAGOperand operand>
926 : Pseudo<(outs cls:$dst), (ins bdaddr20only:$ptr, operand:$src2),
927 [(set cls:$dst, (operator bdaddr20only:$ptr, pat))]> {
929 let Has20BitOffset = 1;
932 let usesCustomInserter = 1;
935 // Specializations of AtomicLoadWBinary.
936 class AtomicLoadBinaryReg32<SDPatternOperator operator>
937 : AtomicLoadBinary<operator, GR32, (i32 GR32:$src2), GR32>;
938 class AtomicLoadBinaryImm32<SDPatternOperator operator, Immediate imm>
939 : AtomicLoadBinary<operator, GR32, (i32 imm:$src2), imm>;
940 class AtomicLoadBinaryReg64<SDPatternOperator operator>
941 : AtomicLoadBinary<operator, GR64, (i64 GR64:$src2), GR64>;
942 class AtomicLoadBinaryImm64<SDPatternOperator operator, Immediate imm>
943 : AtomicLoadBinary<operator, GR64, (i64 imm:$src2), imm>;
945 // OPERATOR is ATOMIC_SWAPW or an ATOMIC_LOADW_* operation. PAT and OPERAND
946 // describe the second (non-memory) operand.
947 class AtomicLoadWBinary<SDPatternOperator operator, dag pat,
949 : Pseudo<(outs GR32:$dst),
950 (ins bdaddr20only:$ptr, operand:$src2, ADDR32:$bitshift,
951 ADDR32:$negbitshift, uimm32:$bitsize),
952 [(set GR32:$dst, (operator bdaddr20only:$ptr, pat, ADDR32:$bitshift,
953 ADDR32:$negbitshift, uimm32:$bitsize))]> {
955 let Has20BitOffset = 1;
958 let usesCustomInserter = 1;
961 // Specializations of AtomicLoadWBinary.
962 class AtomicLoadWBinaryReg<SDPatternOperator operator>
963 : AtomicLoadWBinary<operator, (i32 GR32:$src2), GR32>;
964 class AtomicLoadWBinaryImm<SDPatternOperator operator, Immediate imm>
965 : AtomicLoadWBinary<operator, (i32 imm:$src2), imm>;