1 //===- SystemZInstrInfo.cpp - SystemZ Instruction Information --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SystemZ implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "SystemZInstrBuilder.h"
16 #include "SystemZInstrInfo.h"
17 #include "SystemZMachineFunctionInfo.h"
18 #include "SystemZTargetMachine.h"
19 #include "SystemZGenInstrInfo.inc"
20 #include "llvm/Function.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/PseudoSourceValue.h"
28 SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm)
29 : TargetInstrInfoImpl(SystemZInsts, array_lengthof(SystemZInsts)),
30 RI(tm, *this), TM(tm) {
31 // Fill the spill offsets map
32 static const unsigned SpillOffsTab[][2] = {
33 { SystemZ::R2D, 0x10 },
34 { SystemZ::R3D, 0x18 },
35 { SystemZ::R4D, 0x20 },
36 { SystemZ::R5D, 0x28 },
37 { SystemZ::R6D, 0x30 },
38 { SystemZ::R7D, 0x38 },
39 { SystemZ::R8D, 0x40 },
40 { SystemZ::R9D, 0x48 },
41 { SystemZ::R10D, 0x50 },
42 { SystemZ::R11D, 0x58 },
43 { SystemZ::R12D, 0x60 },
44 { SystemZ::R13D, 0x68 },
45 { SystemZ::R14D, 0x70 },
46 { SystemZ::R15D, 0x78 }
49 RegSpillOffsets.grow(SystemZ::NUM_TARGET_REGS);
51 for (unsigned i = 0, e = array_lengthof(SpillOffsTab); i != e; ++i)
52 RegSpillOffsets[SpillOffsTab[i][0]] = SpillOffsTab[i][1];
55 void SystemZInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
56 MachineBasicBlock::iterator MI,
57 unsigned SrcReg, bool isKill, int FrameIdx,
58 const TargetRegisterClass *RC) const {
59 DebugLoc DL = DebugLoc::getUnknownLoc();
60 if (MI != MBB.end()) DL = MI->getDebugLoc();
63 if (RC == &SystemZ::GR32RegClass ||
64 RC == &SystemZ::ADDR32RegClass)
65 Opc = SystemZ::MOV32mr;
66 else if (RC == &SystemZ::GR64RegClass ||
67 RC == &SystemZ::ADDR64RegClass) {
68 Opc = SystemZ::MOV64mr;
70 assert(0 && "Unsupported regclass to store");
72 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
73 .addReg(SrcReg, getKillRegState(isKill));
76 void SystemZInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
77 MachineBasicBlock::iterator MI,
78 unsigned DestReg, int FrameIdx,
79 const TargetRegisterClass *RC) const{
80 DebugLoc DL = DebugLoc::getUnknownLoc();
81 if (MI != MBB.end()) DL = MI->getDebugLoc();
84 if (RC == &SystemZ::GR32RegClass ||
85 RC == &SystemZ::ADDR32RegClass)
86 Opc = SystemZ::MOV32rm;
87 else if (RC == &SystemZ::GR64RegClass ||
88 RC == &SystemZ::ADDR64RegClass) {
89 Opc = SystemZ::MOV64rm;
91 assert(0 && "Unsupported regclass to store");
93 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
96 bool SystemZInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
97 MachineBasicBlock::iterator I,
98 unsigned DestReg, unsigned SrcReg,
99 const TargetRegisterClass *DestRC,
100 const TargetRegisterClass *SrcRC) const {
101 DebugLoc DL = DebugLoc::getUnknownLoc();
102 if (I != MBB.end()) DL = I->getDebugLoc();
104 // Determine if DstRC and SrcRC have a common superclass.
105 const TargetRegisterClass *CommonRC = DestRC;
107 /* Same regclass for source and dest */;
108 else if (CommonRC->hasSuperClass(SrcRC))
110 else if (!CommonRC->hasSubClass(SrcRC))
114 if (CommonRC == &SystemZ::GR64RegClass ||
115 CommonRC == &SystemZ::ADDR64RegClass) {
116 BuildMI(MBB, I, DL, get(SystemZ::MOV64rr), DestReg).addReg(SrcReg);
117 } else if (CommonRC == &SystemZ::GR32RegClass ||
118 CommonRC == &SystemZ::ADDR32RegClass) {
119 BuildMI(MBB, I, DL, get(SystemZ::MOV32rr), DestReg).addReg(SrcReg);
120 } else if (CommonRC == &SystemZ::GR64PRegClass) {
121 BuildMI(MBB, I, DL, get(SystemZ::MOV64rrP), DestReg).addReg(SrcReg);
122 } else if (CommonRC == &SystemZ::GR128RegClass) {
123 BuildMI(MBB, I, DL, get(SystemZ::MOV128rr), DestReg).addReg(SrcReg);
124 } else if (CommonRC == &SystemZ::FP32RegClass) {
125 BuildMI(MBB, I, DL, get(SystemZ::FMOV32rr), DestReg).addReg(SrcReg);
126 } else if (CommonRC == &SystemZ::FP64RegClass) {
127 BuildMI(MBB, I, DL, get(SystemZ::FMOV64rr), DestReg).addReg(SrcReg);
135 if ((SrcRC == &SystemZ::GR64RegClass &&
136 DestRC == &SystemZ::ADDR64RegClass) ||
137 (DestRC == &SystemZ::GR64RegClass &&
138 SrcRC == &SystemZ::ADDR64RegClass)) {
139 BuildMI(MBB, I, DL, get(SystemZ::MOV64rr), DestReg).addReg(SrcReg);
141 } else if ((SrcRC == &SystemZ::GR32RegClass &&
142 DestRC == &SystemZ::ADDR32RegClass) ||
143 (DestRC == &SystemZ::GR32RegClass &&
144 SrcRC == &SystemZ::ADDR32RegClass)) {
145 BuildMI(MBB, I, DL, get(SystemZ::MOV32rr), DestReg).addReg(SrcReg);
153 SystemZInstrInfo::isMoveInstr(const MachineInstr& MI,
154 unsigned &SrcReg, unsigned &DstReg,
155 unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
156 switch (MI.getOpcode()) {
159 case SystemZ::MOV32rr:
160 case SystemZ::MOV64rr:
161 case SystemZ::MOV64rrP:
162 case SystemZ::MOV128rr:
163 case SystemZ::FMOV32rr:
164 case SystemZ::FMOV64rr:
165 assert(MI.getNumOperands() >= 2 &&
166 MI.getOperand(0).isReg() &&
167 MI.getOperand(1).isReg() &&
168 "invalid register-register move instruction");
169 SrcReg = MI.getOperand(1).getReg();
170 DstReg = MI.getOperand(0).getReg();
171 SrcSubIdx = MI.getOperand(1).getSubReg();
172 DstSubIdx = MI.getOperand(0).getSubReg();
178 SystemZInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
179 MachineBasicBlock::iterator MI,
180 const std::vector<CalleeSavedInfo> &CSI) const {
181 DebugLoc DL = DebugLoc::getUnknownLoc();
182 if (MI != MBB.end()) DL = MI->getDebugLoc();
184 MachineFunction &MF = *MBB.getParent();
185 SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>();
186 MFI->setCalleeSavedFrameSize(CSI.size() * 8);
188 // Scan the callee-saved and find the bounds of register spill area.
189 unsigned LowReg = 0, HighReg = 0, StartOffset = -1U, EndOffset = 0;
190 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
191 unsigned Reg = CSI[i].getReg();
192 unsigned Offset = RegSpillOffsets[Reg];
193 if (StartOffset > Offset) {
194 LowReg = Reg; StartOffset = Offset;
196 if (EndOffset < Offset) {
197 HighReg = Reg; EndOffset = RegSpillOffsets[Reg];
201 // Save information for epilogue inserter.
202 MFI->setLowReg(LowReg); MFI->setHighReg(HighReg);
204 // Build a store instruction. Use STORE MULTIPLE instruction if there are many
205 // registers to store, otherwise - just STORE.
206 MachineInstrBuilder MIB =
207 BuildMI(MBB, MI, DL, get((LowReg == HighReg ?
208 SystemZ::MOV64mr : SystemZ::MOV64mrm)));
210 // Add store operands.
211 MIB.addReg(SystemZ::R15D).addImm(StartOffset);
212 if (LowReg == HighReg)
214 MIB.addReg(LowReg, RegState::Kill);
215 if (LowReg != HighReg)
216 MIB.addReg(HighReg, RegState::Kill);
218 // Do a second scan adding regs as being killed by instruction
219 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
220 unsigned Reg = CSI[i].getReg();
221 // Add the callee-saved register as live-in. It's killed at the spill.
223 if (Reg != LowReg && Reg != HighReg)
224 MIB.addReg(Reg, RegState::ImplicitKill);
231 SystemZInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
232 MachineBasicBlock::iterator MI,
233 const std::vector<CalleeSavedInfo> &CSI) const {
237 DebugLoc DL = DebugLoc::getUnknownLoc();
238 if (MI != MBB.end()) DL = MI->getDebugLoc();
240 MachineFunction &MF = *MBB.getParent();
241 const TargetRegisterInfo *RegInfo= MF.getTarget().getRegisterInfo();
242 SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>();
244 unsigned LowReg = MFI->getLowReg(), HighReg = MFI->getHighReg();
245 unsigned StartOffset = RegSpillOffsets[LowReg];
247 // Build a load instruction. Use LOAD MULTIPLE instruction if there are many
248 // registers to load, otherwise - just LOAD.
249 MachineInstrBuilder MIB =
250 BuildMI(MBB, MI, DL, get((LowReg == HighReg ?
251 SystemZ::MOV64rm : SystemZ::MOV64rmm)));
252 // Add store operands.
253 MIB.addReg(LowReg, RegState::Define);
254 if (LowReg != HighReg)
255 MIB.addReg(HighReg, RegState::Define);
257 MIB.addReg((RegInfo->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D));
258 MIB.addImm(StartOffset);
259 if (LowReg == HighReg)
262 // Do a second scan adding regs as being defined by instruction
263 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
264 unsigned Reg = CSI[i].getReg();
265 if (Reg != LowReg && Reg != HighReg)
266 MIB.addReg(Reg, RegState::ImplicitDefine);
273 SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
274 MachineBasicBlock *FBB,
275 const SmallVectorImpl<MachineOperand> &Cond) const {
276 // FIXME: this should probably have a DebugLoc operand
277 DebugLoc dl = DebugLoc::getUnknownLoc();
278 // Shouldn't be a fall through.
279 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
280 assert((Cond.size() == 1 || Cond.size() == 0) &&
281 "SystemZ branch conditions have one component!");
284 // Unconditional branch?
285 assert(!FBB && "Unconditional branch with multiple successors!");
286 BuildMI(&MBB, dl, get(SystemZ::JMP)).addMBB(TBB);
290 // Conditional branch.
292 SystemZCC::CondCodes CC = (SystemZCC::CondCodes)Cond[0].getImm();
293 BuildMI(&MBB, dl, getBrCond(CC)).addMBB(TBB);
297 // Two-way Conditional branch. Insert the second branch.
298 BuildMI(&MBB, dl, get(SystemZ::JMP)).addMBB(FBB);
304 const TargetInstrDesc&
305 SystemZInstrInfo::getBrCond(SystemZCC::CondCodes CC) const {
309 assert(0 && "Unknown condition code!");
333 const TargetInstrDesc&
334 SystemZInstrInfo::getLongDispOpc(unsigned Opc) const {
336 case SystemZ::MOV32mr:
337 Opc = SystemZ::MOV32mry;
339 case SystemZ::MOV32rm:
340 Opc = SystemZ::MOV32rmy;
342 case SystemZ::MOVSX32rm16:
343 Opc = SystemZ::MOVSX32rm16y;
345 case SystemZ::MOV32m8r:
346 Opc = SystemZ::MOV32m8ry;
348 case SystemZ::MOV32m16r:
349 Opc = SystemZ::MOV32m16ry;
351 case SystemZ::MOV64m8r:
352 Opc = SystemZ::MOV64m8ry;
354 case SystemZ::MOV64m16r:
355 Opc = SystemZ::MOV64m16ry;
357 case SystemZ::MOV64m32r:
358 Opc = SystemZ::MOV64m32ry;
360 case SystemZ::MOV8mi:
361 Opc = SystemZ::MOV8miy;
363 case SystemZ::MUL32rm:
364 Opc = SystemZ::MUL32rmy;
366 case SystemZ::CMP32rm:
367 Opc = SystemZ::CMP32rmy;
369 case SystemZ::UCMP32rm:
370 Opc = SystemZ::UCMP32rmy;