1 //===-- SystemZInstrInfo.cpp - SystemZ instruction information ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SystemZ implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "SystemZInstrInfo.h"
15 #include "SystemZInstrBuilder.h"
16 #include "SystemZTargetMachine.h"
17 #include "llvm/CodeGen/LiveVariables.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #define GET_INSTRINFO_CTOR_DTOR
23 #define GET_INSTRMAP_INFO
24 #include "SystemZGenInstrInfo.inc"
26 // Return a mask with Count low bits set.
27 static uint64_t allOnes(unsigned int Count) {
28 return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1;
31 // Reg should be a 32-bit GPR. Return true if it is a high register rather
32 // than a low register.
33 static bool isHighReg(unsigned int Reg) {
34 if (SystemZ::GRH32BitRegClass.contains(Reg))
36 assert(SystemZ::GR32BitRegClass.contains(Reg) && "Invalid GRX32");
40 // Pin the vtable to this file.
41 void SystemZInstrInfo::anchor() {}
43 SystemZInstrInfo::SystemZInstrInfo(SystemZSubtarget &sti)
44 : SystemZGenInstrInfo(SystemZ::ADJCALLSTACKDOWN, SystemZ::ADJCALLSTACKUP),
48 // MI is a 128-bit load or store. Split it into two 64-bit loads or stores,
49 // each having the opcode given by NewOpcode.
50 void SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI,
51 unsigned NewOpcode) const {
52 MachineBasicBlock *MBB = MI->getParent();
53 MachineFunction &MF = *MBB->getParent();
55 // Get two load or store instructions. Use the original instruction for one
56 // of them (arbitrarily the second here) and create a clone for the other.
57 MachineInstr *EarlierMI = MF.CloneMachineInstr(MI);
58 MBB->insert(MI, EarlierMI);
60 // Set up the two 64-bit registers.
61 MachineOperand &HighRegOp = EarlierMI->getOperand(0);
62 MachineOperand &LowRegOp = MI->getOperand(0);
63 HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64));
64 LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64));
66 // The address in the first (high) instruction is already correct.
67 // Adjust the offset in the second (low) instruction.
68 MachineOperand &HighOffsetOp = EarlierMI->getOperand(2);
69 MachineOperand &LowOffsetOp = MI->getOperand(2);
70 LowOffsetOp.setImm(LowOffsetOp.getImm() + 8);
73 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm());
74 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm());
75 assert(HighOpcode && LowOpcode && "Both offsets should be in range");
77 EarlierMI->setDesc(get(HighOpcode));
78 MI->setDesc(get(LowOpcode));
81 // Split ADJDYNALLOC instruction MI.
82 void SystemZInstrInfo::splitAdjDynAlloc(MachineBasicBlock::iterator MI) const {
83 MachineBasicBlock *MBB = MI->getParent();
84 MachineFunction &MF = *MBB->getParent();
85 MachineFrameInfo *MFFrame = MF.getFrameInfo();
86 MachineOperand &OffsetMO = MI->getOperand(2);
88 uint64_t Offset = (MFFrame->getMaxCallFrameSize() +
89 SystemZMC::CallFrameSize +
91 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset);
92 assert(NewOpcode && "No support for huge argument lists yet");
93 MI->setDesc(get(NewOpcode));
94 OffsetMO.setImm(Offset);
97 // MI is an RI-style pseudo instruction. Replace it with LowOpcode
98 // if the first operand is a low GR32 and HighOpcode if the first operand
99 // is a high GR32. ConvertHigh is true if LowOpcode takes a signed operand
100 // and HighOpcode takes an unsigned 32-bit operand. In those cases,
101 // MI has the same kind of operand as LowOpcode, so needs to be converted
102 // if HighOpcode is used.
103 void SystemZInstrInfo::expandRIPseudo(MachineInstr *MI, unsigned LowOpcode,
105 bool ConvertHigh) const {
106 unsigned Reg = MI->getOperand(0).getReg();
107 bool IsHigh = isHighReg(Reg);
108 MI->setDesc(get(IsHigh ? HighOpcode : LowOpcode));
109 if (IsHigh && ConvertHigh)
110 MI->getOperand(1).setImm(uint32_t(MI->getOperand(1).getImm()));
113 // MI is a three-operand RIE-style pseudo instruction. Replace it with
114 // LowOpcode3 if the registers are both low GR32s, otherwise use a move
115 // followed by HighOpcode or LowOpcode, depending on whether the target
116 // is a high or low GR32.
117 void SystemZInstrInfo::expandRIEPseudo(MachineInstr *MI, unsigned LowOpcode,
119 unsigned HighOpcode) const {
120 unsigned DestReg = MI->getOperand(0).getReg();
121 unsigned SrcReg = MI->getOperand(1).getReg();
122 bool DestIsHigh = isHighReg(DestReg);
123 bool SrcIsHigh = isHighReg(SrcReg);
124 if (!DestIsHigh && !SrcIsHigh)
125 MI->setDesc(get(LowOpcodeK));
127 emitGRX32Move(*MI->getParent(), MI, MI->getDebugLoc(),
128 DestReg, SrcReg, SystemZ::LR, 32,
129 MI->getOperand(1).isKill());
130 MI->setDesc(get(DestIsHigh ? HighOpcode : LowOpcode));
131 MI->getOperand(1).setReg(DestReg);
135 // MI is an RXY-style pseudo instruction. Replace it with LowOpcode
136 // if the first operand is a low GR32 and HighOpcode if the first operand
138 void SystemZInstrInfo::expandRXYPseudo(MachineInstr *MI, unsigned LowOpcode,
139 unsigned HighOpcode) const {
140 unsigned Reg = MI->getOperand(0).getReg();
141 unsigned Opcode = getOpcodeForOffset(isHighReg(Reg) ? HighOpcode : LowOpcode,
142 MI->getOperand(2).getImm());
143 MI->setDesc(get(Opcode));
146 // MI is an RR-style pseudo instruction that zero-extends the low Size bits
147 // of one GRX32 into another. Replace it with LowOpcode if both operands
148 // are low registers, otherwise use RISB[LH]G.
149 void SystemZInstrInfo::expandZExtPseudo(MachineInstr *MI, unsigned LowOpcode,
150 unsigned Size) const {
151 emitGRX32Move(*MI->getParent(), MI, MI->getDebugLoc(),
152 MI->getOperand(0).getReg(), MI->getOperand(1).getReg(),
153 LowOpcode, Size, MI->getOperand(1).isKill());
154 MI->eraseFromParent();
157 // Emit a zero-extending move from 32-bit GPR SrcReg to 32-bit GPR
158 // DestReg before MBBI in MBB. Use LowLowOpcode when both DestReg and SrcReg
159 // are low registers, otherwise use RISB[LH]G. Size is the number of bits
160 // taken from the low end of SrcReg (8 for LLCR, 16 for LLHR and 32 for LR).
161 // KillSrc is true if this move is the last use of SrcReg.
162 void SystemZInstrInfo::emitGRX32Move(MachineBasicBlock &MBB,
163 MachineBasicBlock::iterator MBBI,
164 DebugLoc DL, unsigned DestReg,
165 unsigned SrcReg, unsigned LowLowOpcode,
166 unsigned Size, bool KillSrc) const {
168 bool DestIsHigh = isHighReg(DestReg);
169 bool SrcIsHigh = isHighReg(SrcReg);
170 if (DestIsHigh && SrcIsHigh)
171 Opcode = SystemZ::RISBHH;
172 else if (DestIsHigh && !SrcIsHigh)
173 Opcode = SystemZ::RISBHL;
174 else if (!DestIsHigh && SrcIsHigh)
175 Opcode = SystemZ::RISBLH;
177 BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg)
178 .addReg(SrcReg, getKillRegState(KillSrc));
181 unsigned Rotate = (DestIsHigh != SrcIsHigh ? 32 : 0);
182 BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
183 .addReg(DestReg, RegState::Undef)
184 .addReg(SrcReg, getKillRegState(KillSrc))
185 .addImm(32 - Size).addImm(128 + 31).addImm(Rotate);
188 // If MI is a simple load or store for a frame object, return the register
189 // it loads or stores and set FrameIndex to the index of the frame object.
190 // Return 0 otherwise.
192 // Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
193 static int isSimpleMove(const MachineInstr *MI, int &FrameIndex,
195 const MCInstrDesc &MCID = MI->getDesc();
196 if ((MCID.TSFlags & Flag) &&
197 MI->getOperand(1).isFI() &&
198 MI->getOperand(2).getImm() == 0 &&
199 MI->getOperand(3).getReg() == 0) {
200 FrameIndex = MI->getOperand(1).getIndex();
201 return MI->getOperand(0).getReg();
206 unsigned SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
207 int &FrameIndex) const {
208 return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXLoad);
211 unsigned SystemZInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
212 int &FrameIndex) const {
213 return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXStore);
216 bool SystemZInstrInfo::isStackSlotCopy(const MachineInstr *MI,
218 int &SrcFrameIndex) const {
219 // Check for MVC 0(Length,FI1),0(FI2)
220 const MachineFrameInfo *MFI = MI->getParent()->getParent()->getFrameInfo();
221 if (MI->getOpcode() != SystemZ::MVC ||
222 !MI->getOperand(0).isFI() ||
223 MI->getOperand(1).getImm() != 0 ||
224 !MI->getOperand(3).isFI() ||
225 MI->getOperand(4).getImm() != 0)
228 // Check that Length covers the full slots.
229 int64_t Length = MI->getOperand(2).getImm();
230 unsigned FI1 = MI->getOperand(0).getIndex();
231 unsigned FI2 = MI->getOperand(3).getIndex();
232 if (MFI->getObjectSize(FI1) != Length ||
233 MFI->getObjectSize(FI2) != Length)
236 DestFrameIndex = FI1;
241 bool SystemZInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
242 MachineBasicBlock *&TBB,
243 MachineBasicBlock *&FBB,
244 SmallVectorImpl<MachineOperand> &Cond,
245 bool AllowModify) const {
246 // Most of the code and comments here are boilerplate.
248 // Start from the bottom of the block and work up, examining the
249 // terminator instructions.
250 MachineBasicBlock::iterator I = MBB.end();
251 while (I != MBB.begin()) {
253 if (I->isDebugValue())
256 // Working from the bottom, when we see a non-terminator instruction, we're
258 if (!isUnpredicatedTerminator(I))
261 // A terminator that isn't a branch can't easily be handled by this
266 // Can't handle indirect branches.
267 SystemZII::Branch Branch(getBranchInfo(I));
268 if (!Branch.Target->isMBB())
271 // Punt on compound branches.
272 if (Branch.Type != SystemZII::BranchNormal)
275 if (Branch.CCMask == SystemZ::CCMASK_ANY) {
276 // Handle unconditional branches.
278 TBB = Branch.Target->getMBB();
282 // If the block has any instructions after a JMP, delete them.
283 while (std::next(I) != MBB.end())
284 std::next(I)->eraseFromParent();
289 // Delete the JMP if it's equivalent to a fall-through.
290 if (MBB.isLayoutSuccessor(Branch.Target->getMBB())) {
292 I->eraseFromParent();
297 // TBB is used to indicate the unconditinal destination.
298 TBB = Branch.Target->getMBB();
302 // Working from the bottom, handle the first conditional branch.
304 // FIXME: add X86-style branch swap
306 TBB = Branch.Target->getMBB();
307 Cond.push_back(MachineOperand::CreateImm(Branch.CCValid));
308 Cond.push_back(MachineOperand::CreateImm(Branch.CCMask));
312 // Handle subsequent conditional branches.
313 assert(Cond.size() == 2 && TBB && "Should have seen a conditional branch");
315 // Only handle the case where all conditional branches branch to the same
317 if (TBB != Branch.Target->getMBB())
320 // If the conditions are the same, we can leave them alone.
321 unsigned OldCCValid = Cond[0].getImm();
322 unsigned OldCCMask = Cond[1].getImm();
323 if (OldCCValid == Branch.CCValid && OldCCMask == Branch.CCMask)
326 // FIXME: Try combining conditions like X86 does. Should be easy on Z!
333 unsigned SystemZInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
334 // Most of the code and comments here are boilerplate.
335 MachineBasicBlock::iterator I = MBB.end();
338 while (I != MBB.begin()) {
340 if (I->isDebugValue())
344 if (!getBranchInfo(I).Target->isMBB())
346 // Remove the branch.
347 I->eraseFromParent();
355 bool SystemZInstrInfo::
356 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
357 assert(Cond.size() == 2 && "Invalid condition");
358 Cond[1].setImm(Cond[1].getImm() ^ Cond[0].getImm());
363 SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
364 MachineBasicBlock *FBB,
365 ArrayRef<MachineOperand> Cond,
367 // In this function we output 32-bit branches, which should always
368 // have enough range. They can be shortened and relaxed by later code
369 // in the pipeline, if desired.
371 // Shouldn't be a fall through.
372 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
373 assert((Cond.size() == 2 || Cond.size() == 0) &&
374 "SystemZ branch conditions have one component!");
377 // Unconditional branch?
378 assert(!FBB && "Unconditional branch with multiple successors!");
379 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(TBB);
383 // Conditional branch.
385 unsigned CCValid = Cond[0].getImm();
386 unsigned CCMask = Cond[1].getImm();
387 BuildMI(&MBB, DL, get(SystemZ::BRC))
388 .addImm(CCValid).addImm(CCMask).addMBB(TBB);
392 // Two-way Conditional branch. Insert the second branch.
393 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(FBB);
399 bool SystemZInstrInfo::analyzeCompare(const MachineInstr *MI,
400 unsigned &SrcReg, unsigned &SrcReg2,
401 int &Mask, int &Value) const {
402 assert(MI->isCompare() && "Caller should have checked for a comparison");
404 if (MI->getNumExplicitOperands() == 2 &&
405 MI->getOperand(0).isReg() &&
406 MI->getOperand(1).isImm()) {
407 SrcReg = MI->getOperand(0).getReg();
409 Value = MI->getOperand(1).getImm();
417 // If Reg is a virtual register, return its definition, otherwise return null.
418 static MachineInstr *getDef(unsigned Reg,
419 const MachineRegisterInfo *MRI) {
420 if (TargetRegisterInfo::isPhysicalRegister(Reg))
422 return MRI->getUniqueVRegDef(Reg);
425 // Return true if MI is a shift of type Opcode by Imm bits.
426 static bool isShift(MachineInstr *MI, unsigned Opcode, int64_t Imm) {
427 return (MI->getOpcode() == Opcode &&
428 !MI->getOperand(2).getReg() &&
429 MI->getOperand(3).getImm() == Imm);
432 // If the destination of MI has no uses, delete it as dead.
433 static void eraseIfDead(MachineInstr *MI, const MachineRegisterInfo *MRI) {
434 if (MRI->use_nodbg_empty(MI->getOperand(0).getReg()))
435 MI->eraseFromParent();
438 // Compare compares SrcReg against zero. Check whether SrcReg contains
439 // the result of an IPM sequence whose input CC survives until Compare,
440 // and whether Compare is therefore redundant. Delete it and return
442 static bool removeIPMBasedCompare(MachineInstr *Compare, unsigned SrcReg,
443 const MachineRegisterInfo *MRI,
444 const TargetRegisterInfo *TRI) {
445 MachineInstr *LGFR = nullptr;
446 MachineInstr *RLL = getDef(SrcReg, MRI);
447 if (RLL && RLL->getOpcode() == SystemZ::LGFR) {
449 RLL = getDef(LGFR->getOperand(1).getReg(), MRI);
451 if (!RLL || !isShift(RLL, SystemZ::RLL, 31))
454 MachineInstr *SRL = getDef(RLL->getOperand(1).getReg(), MRI);
455 if (!SRL || !isShift(SRL, SystemZ::SRL, SystemZ::IPM_CC))
458 MachineInstr *IPM = getDef(SRL->getOperand(1).getReg(), MRI);
459 if (!IPM || IPM->getOpcode() != SystemZ::IPM)
462 // Check that there are no assignments to CC between the IPM and Compare,
463 if (IPM->getParent() != Compare->getParent())
465 MachineBasicBlock::iterator MBBI = IPM, MBBE = Compare;
466 for (++MBBI; MBBI != MBBE; ++MBBI) {
467 MachineInstr *MI = MBBI;
468 if (MI->modifiesRegister(SystemZ::CC, TRI))
472 Compare->eraseFromParent();
474 eraseIfDead(LGFR, MRI);
475 eraseIfDead(RLL, MRI);
476 eraseIfDead(SRL, MRI);
477 eraseIfDead(IPM, MRI);
483 SystemZInstrInfo::optimizeCompareInstr(MachineInstr *Compare,
484 unsigned SrcReg, unsigned SrcReg2,
486 const MachineRegisterInfo *MRI) const {
487 assert(!SrcReg2 && "Only optimizing constant comparisons so far");
488 bool IsLogical = (Compare->getDesc().TSFlags & SystemZII::IsLogical) != 0;
491 removeIPMBasedCompare(Compare, SrcReg, MRI, &RI))
496 // If Opcode is a move that has a conditional variant, return that variant,
497 // otherwise return 0.
498 static unsigned getConditionalMove(unsigned Opcode) {
500 case SystemZ::LR: return SystemZ::LOCR;
501 case SystemZ::LGR: return SystemZ::LOCGR;
506 bool SystemZInstrInfo::isPredicable(MachineInstr *MI) const {
507 unsigned Opcode = MI->getOpcode();
508 if (STI.hasLoadStoreOnCond() &&
509 getConditionalMove(Opcode))
514 bool SystemZInstrInfo::
515 isProfitableToIfCvt(MachineBasicBlock &MBB,
516 unsigned NumCycles, unsigned ExtraPredCycles,
517 const BranchProbability &Probability) const {
518 // For now only convert single instructions.
519 return NumCycles == 1;
522 bool SystemZInstrInfo::
523 isProfitableToIfCvt(MachineBasicBlock &TMBB,
524 unsigned NumCyclesT, unsigned ExtraPredCyclesT,
525 MachineBasicBlock &FMBB,
526 unsigned NumCyclesF, unsigned ExtraPredCyclesF,
527 const BranchProbability &Probability) const {
528 // For now avoid converting mutually-exclusive cases.
532 bool SystemZInstrInfo::
533 PredicateInstruction(MachineInstr *MI, ArrayRef<MachineOperand> Pred) const {
534 assert(Pred.size() == 2 && "Invalid condition");
535 unsigned CCValid = Pred[0].getImm();
536 unsigned CCMask = Pred[1].getImm();
537 assert(CCMask > 0 && CCMask < 15 && "Invalid predicate");
538 unsigned Opcode = MI->getOpcode();
539 if (STI.hasLoadStoreOnCond()) {
540 if (unsigned CondOpcode = getConditionalMove(Opcode)) {
541 MI->setDesc(get(CondOpcode));
542 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
543 .addImm(CCValid).addImm(CCMask)
544 .addReg(SystemZ::CC, RegState::Implicit);
552 SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
553 MachineBasicBlock::iterator MBBI, DebugLoc DL,
554 unsigned DestReg, unsigned SrcReg,
555 bool KillSrc) const {
556 // Split 128-bit GPR moves into two 64-bit moves. This handles ADDR128 too.
557 if (SystemZ::GR128BitRegClass.contains(DestReg, SrcReg)) {
558 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_h64),
559 RI.getSubReg(SrcReg, SystemZ::subreg_h64), KillSrc);
560 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_l64),
561 RI.getSubReg(SrcReg, SystemZ::subreg_l64), KillSrc);
565 if (SystemZ::GRX32BitRegClass.contains(DestReg, SrcReg)) {
566 emitGRX32Move(MBB, MBBI, DL, DestReg, SrcReg, SystemZ::LR, 32, KillSrc);
570 // Everything else needs only one instruction.
572 if (SystemZ::GR64BitRegClass.contains(DestReg, SrcReg))
573 Opcode = SystemZ::LGR;
574 else if (SystemZ::FP32BitRegClass.contains(DestReg, SrcReg))
575 Opcode = SystemZ::LER;
576 else if (SystemZ::FP64BitRegClass.contains(DestReg, SrcReg))
577 Opcode = SystemZ::LDR;
578 else if (SystemZ::FP128BitRegClass.contains(DestReg, SrcReg))
579 Opcode = SystemZ::LXR;
580 else if (SystemZ::VR32BitRegClass.contains(DestReg, SrcReg))
581 Opcode = SystemZ::VLR32;
582 else if (SystemZ::VR64BitRegClass.contains(DestReg, SrcReg))
583 Opcode = SystemZ::VLR64;
584 else if (SystemZ::VR128BitRegClass.contains(DestReg, SrcReg))
585 Opcode = SystemZ::VLR;
587 llvm_unreachable("Impossible reg-to-reg copy");
589 BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
590 .addReg(SrcReg, getKillRegState(KillSrc));
594 SystemZInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
595 MachineBasicBlock::iterator MBBI,
596 unsigned SrcReg, bool isKill,
598 const TargetRegisterClass *RC,
599 const TargetRegisterInfo *TRI) const {
600 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
602 // Callers may expect a single instruction, so keep 128-bit moves
603 // together for now and lower them after register allocation.
604 unsigned LoadOpcode, StoreOpcode;
605 getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
606 addFrameReference(BuildMI(MBB, MBBI, DL, get(StoreOpcode))
607 .addReg(SrcReg, getKillRegState(isKill)), FrameIdx);
611 SystemZInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
612 MachineBasicBlock::iterator MBBI,
613 unsigned DestReg, int FrameIdx,
614 const TargetRegisterClass *RC,
615 const TargetRegisterInfo *TRI) const {
616 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
618 // Callers may expect a single instruction, so keep 128-bit moves
619 // together for now and lower them after register allocation.
620 unsigned LoadOpcode, StoreOpcode;
621 getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
622 addFrameReference(BuildMI(MBB, MBBI, DL, get(LoadOpcode), DestReg),
626 // Return true if MI is a simple load or store with a 12-bit displacement
627 // and no index. Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
628 static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag) {
629 const MCInstrDesc &MCID = MI->getDesc();
630 return ((MCID.TSFlags & Flag) &&
631 isUInt<12>(MI->getOperand(2).getImm()) &&
632 MI->getOperand(3).getReg() == 0);
637 LogicOp() : RegSize(0), ImmLSB(0), ImmSize(0) {}
638 LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize)
639 : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}
641 explicit operator bool() const { return RegSize; }
643 unsigned RegSize, ImmLSB, ImmSize;
645 } // end anonymous namespace
647 static LogicOp interpretAndImmediate(unsigned Opcode) {
649 case SystemZ::NILMux: return LogicOp(32, 0, 16);
650 case SystemZ::NIHMux: return LogicOp(32, 16, 16);
651 case SystemZ::NILL64: return LogicOp(64, 0, 16);
652 case SystemZ::NILH64: return LogicOp(64, 16, 16);
653 case SystemZ::NIHL64: return LogicOp(64, 32, 16);
654 case SystemZ::NIHH64: return LogicOp(64, 48, 16);
655 case SystemZ::NIFMux: return LogicOp(32, 0, 32);
656 case SystemZ::NILF64: return LogicOp(64, 0, 32);
657 case SystemZ::NIHF64: return LogicOp(64, 32, 32);
658 default: return LogicOp();
662 // Used to return from convertToThreeAddress after replacing two-address
663 // instruction OldMI with three-address instruction NewMI.
664 static MachineInstr *finishConvertToThreeAddress(MachineInstr *OldMI,
668 unsigned NumOps = OldMI->getNumOperands();
669 for (unsigned I = 1; I < NumOps; ++I) {
670 MachineOperand &Op = OldMI->getOperand(I);
671 if (Op.isReg() && Op.isKill())
672 LV->replaceKillInstruction(Op.getReg(), OldMI, NewMI);
679 SystemZInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
680 MachineBasicBlock::iterator &MBBI,
681 LiveVariables *LV) const {
682 MachineInstr *MI = MBBI;
683 MachineBasicBlock *MBB = MI->getParent();
684 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
686 unsigned Opcode = MI->getOpcode();
687 unsigned NumOps = MI->getNumOperands();
689 // Try to convert something like SLL into SLLK, if supported.
690 // We prefer to keep the two-operand form where possible both
691 // because it tends to be shorter and because some instructions
692 // have memory forms that can be used during spilling.
693 if (STI.hasDistinctOps()) {
694 MachineOperand &Dest = MI->getOperand(0);
695 MachineOperand &Src = MI->getOperand(1);
696 unsigned DestReg = Dest.getReg();
697 unsigned SrcReg = Src.getReg();
698 // AHIMux is only really a three-operand instruction when both operands
699 // are low registers. Try to constrain both operands to be low if
701 if (Opcode == SystemZ::AHIMux &&
702 TargetRegisterInfo::isVirtualRegister(DestReg) &&
703 TargetRegisterInfo::isVirtualRegister(SrcReg) &&
704 MRI.getRegClass(DestReg)->contains(SystemZ::R1L) &&
705 MRI.getRegClass(SrcReg)->contains(SystemZ::R1L)) {
706 MRI.constrainRegClass(DestReg, &SystemZ::GR32BitRegClass);
707 MRI.constrainRegClass(SrcReg, &SystemZ::GR32BitRegClass);
709 int ThreeOperandOpcode = SystemZ::getThreeOperandOpcode(Opcode);
710 if (ThreeOperandOpcode >= 0) {
711 MachineInstrBuilder MIB =
712 BuildMI(*MBB, MBBI, MI->getDebugLoc(), get(ThreeOperandOpcode))
714 // Keep the kill state, but drop the tied flag.
715 MIB.addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg());
716 // Keep the remaining operands as-is.
717 for (unsigned I = 2; I < NumOps; ++I)
718 MIB.addOperand(MI->getOperand(I));
719 return finishConvertToThreeAddress(MI, MIB, LV);
723 // Try to convert an AND into an RISBG-type instruction.
724 if (LogicOp And = interpretAndImmediate(Opcode)) {
725 uint64_t Imm = MI->getOperand(2).getImm() << And.ImmLSB;
726 // AND IMMEDIATE leaves the other bits of the register unchanged.
727 Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB);
729 if (isRxSBGMask(Imm, And.RegSize, Start, End)) {
731 if (And.RegSize == 64) {
732 NewOpcode = SystemZ::RISBG;
733 // Prefer RISBGN if available, since it does not clobber CC.
734 if (STI.hasMiscellaneousExtensions())
735 NewOpcode = SystemZ::RISBGN;
737 NewOpcode = SystemZ::RISBMux;
741 MachineOperand &Dest = MI->getOperand(0);
742 MachineOperand &Src = MI->getOperand(1);
743 MachineInstrBuilder MIB =
744 BuildMI(*MBB, MI, MI->getDebugLoc(), get(NewOpcode))
745 .addOperand(Dest).addReg(0)
746 .addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg())
747 .addImm(Start).addImm(End + 128).addImm(0);
748 return finishConvertToThreeAddress(MI, MIB, LV);
754 MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
755 MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops,
756 MachineBasicBlock::iterator InsertPt, int FrameIndex) const {
757 const MachineFrameInfo *MFI = MF.getFrameInfo();
758 unsigned Size = MFI->getObjectSize(FrameIndex);
759 unsigned Opcode = MI->getOpcode();
761 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
762 if ((Opcode == SystemZ::LA || Opcode == SystemZ::LAY) &&
763 isInt<8>(MI->getOperand(2).getImm()) &&
764 !MI->getOperand(3).getReg()) {
765 // LA(Y) %reg, CONST(%reg) -> AGSI %mem, CONST
766 return BuildMI(*InsertPt->getParent(), InsertPt, MI->getDebugLoc(),
768 .addFrameIndex(FrameIndex)
770 .addImm(MI->getOperand(2).getImm());
775 // All other cases require a single operand.
779 unsigned OpNum = Ops[0];
780 assert(Size == MF.getRegInfo()
781 .getRegClass(MI->getOperand(OpNum).getReg())->getSize() &&
782 "Invalid size combination");
784 if ((Opcode == SystemZ::AHI || Opcode == SystemZ::AGHI) &&
786 isInt<8>(MI->getOperand(2).getImm())) {
787 // A(G)HI %reg, CONST -> A(G)SI %mem, CONST
788 Opcode = (Opcode == SystemZ::AHI ? SystemZ::ASI : SystemZ::AGSI);
789 return BuildMI(*InsertPt->getParent(), InsertPt, MI->getDebugLoc(),
791 .addFrameIndex(FrameIndex)
793 .addImm(MI->getOperand(2).getImm());
796 if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {
797 bool Op0IsGPR = (Opcode == SystemZ::LGDR);
798 bool Op1IsGPR = (Opcode == SystemZ::LDGR);
799 // If we're spilling the destination of an LDGR or LGDR, store the
800 // source register instead.
802 unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD;
803 return BuildMI(*InsertPt->getParent(), InsertPt, MI->getDebugLoc(),
805 .addOperand(MI->getOperand(1))
806 .addFrameIndex(FrameIndex)
810 // If we're spilling the source of an LDGR or LGDR, load the
811 // destination register instead.
813 unsigned LoadOpcode = Op0IsGPR ? SystemZ::LG : SystemZ::LD;
814 unsigned Dest = MI->getOperand(0).getReg();
815 return BuildMI(*InsertPt->getParent(), InsertPt, MI->getDebugLoc(),
816 get(LoadOpcode), Dest)
817 .addFrameIndex(FrameIndex)
823 // Look for cases where the source of a simple store or the destination
824 // of a simple load is being spilled. Try to use MVC instead.
826 // Although MVC is in practice a fast choice in these cases, it is still
827 // logically a bytewise copy. This means that we cannot use it if the
828 // load or store is volatile. We also wouldn't be able to use MVC if
829 // the two memories partially overlap, but that case cannot occur here,
830 // because we know that one of the memories is a full frame index.
832 // For performance reasons, we also want to avoid using MVC if the addresses
833 // might be equal. We don't worry about that case here, because spill slot
834 // coloring happens later, and because we have special code to remove
835 // MVCs that turn out to be redundant.
836 if (OpNum == 0 && MI->hasOneMemOperand()) {
837 MachineMemOperand *MMO = *MI->memoperands_begin();
838 if (MMO->getSize() == Size && !MMO->isVolatile()) {
839 // Handle conversion of loads.
840 if (isSimpleBD12Move(MI, SystemZII::SimpleBDXLoad)) {
841 return BuildMI(*InsertPt->getParent(), InsertPt, MI->getDebugLoc(),
843 .addFrameIndex(FrameIndex)
846 .addOperand(MI->getOperand(1))
847 .addImm(MI->getOperand(2).getImm())
850 // Handle conversion of stores.
851 if (isSimpleBD12Move(MI, SystemZII::SimpleBDXStore)) {
852 return BuildMI(*InsertPt->getParent(), InsertPt, MI->getDebugLoc(),
854 .addOperand(MI->getOperand(1))
855 .addImm(MI->getOperand(2).getImm())
857 .addFrameIndex(FrameIndex)
864 // If the spilled operand is the final one, try to change <INSN>R
866 int MemOpcode = SystemZ::getMemOpcode(Opcode);
867 if (MemOpcode >= 0) {
868 unsigned NumOps = MI->getNumExplicitOperands();
869 if (OpNum == NumOps - 1) {
870 const MCInstrDesc &MemDesc = get(MemOpcode);
871 uint64_t AccessBytes = SystemZII::getAccessSize(MemDesc.TSFlags);
872 assert(AccessBytes != 0 && "Size of access should be known");
873 assert(AccessBytes <= Size && "Access outside the frame index");
874 uint64_t Offset = Size - AccessBytes;
875 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
876 MI->getDebugLoc(), get(MemOpcode));
877 for (unsigned I = 0; I < OpNum; ++I)
878 MIB.addOperand(MI->getOperand(I));
879 MIB.addFrameIndex(FrameIndex).addImm(Offset);
880 if (MemDesc.TSFlags & SystemZII::HasIndex)
889 MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
890 MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops,
891 MachineBasicBlock::iterator InsertPt, MachineInstr *LoadMI) const {
896 SystemZInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
897 switch (MI->getOpcode()) {
899 splitMove(MI, SystemZ::LG);
903 splitMove(MI, SystemZ::STG);
907 splitMove(MI, SystemZ::LD);
911 splitMove(MI, SystemZ::STD);
915 expandRXYPseudo(MI, SystemZ::LB, SystemZ::LBH);
919 expandRXYPseudo(MI, SystemZ::LH, SystemZ::LHH);
922 case SystemZ::LLCRMux:
923 expandZExtPseudo(MI, SystemZ::LLCR, 8);
926 case SystemZ::LLHRMux:
927 expandZExtPseudo(MI, SystemZ::LLHR, 16);
930 case SystemZ::LLCMux:
931 expandRXYPseudo(MI, SystemZ::LLC, SystemZ::LLCH);
934 case SystemZ::LLHMux:
935 expandRXYPseudo(MI, SystemZ::LLH, SystemZ::LLHH);
939 expandRXYPseudo(MI, SystemZ::L, SystemZ::LFH);
942 case SystemZ::STCMux:
943 expandRXYPseudo(MI, SystemZ::STC, SystemZ::STCH);
946 case SystemZ::STHMux:
947 expandRXYPseudo(MI, SystemZ::STH, SystemZ::STHH);
951 expandRXYPseudo(MI, SystemZ::ST, SystemZ::STFH);
954 case SystemZ::LHIMux:
955 expandRIPseudo(MI, SystemZ::LHI, SystemZ::IIHF, true);
958 case SystemZ::IIFMux:
959 expandRIPseudo(MI, SystemZ::IILF, SystemZ::IIHF, false);
962 case SystemZ::IILMux:
963 expandRIPseudo(MI, SystemZ::IILL, SystemZ::IIHL, false);
966 case SystemZ::IIHMux:
967 expandRIPseudo(MI, SystemZ::IILH, SystemZ::IIHH, false);
970 case SystemZ::NIFMux:
971 expandRIPseudo(MI, SystemZ::NILF, SystemZ::NIHF, false);
974 case SystemZ::NILMux:
975 expandRIPseudo(MI, SystemZ::NILL, SystemZ::NIHL, false);
978 case SystemZ::NIHMux:
979 expandRIPseudo(MI, SystemZ::NILH, SystemZ::NIHH, false);
982 case SystemZ::OIFMux:
983 expandRIPseudo(MI, SystemZ::OILF, SystemZ::OIHF, false);
986 case SystemZ::OILMux:
987 expandRIPseudo(MI, SystemZ::OILL, SystemZ::OIHL, false);
990 case SystemZ::OIHMux:
991 expandRIPseudo(MI, SystemZ::OILH, SystemZ::OIHH, false);
994 case SystemZ::XIFMux:
995 expandRIPseudo(MI, SystemZ::XILF, SystemZ::XIHF, false);
998 case SystemZ::TMLMux:
999 expandRIPseudo(MI, SystemZ::TMLL, SystemZ::TMHL, false);
1002 case SystemZ::TMHMux:
1003 expandRIPseudo(MI, SystemZ::TMLH, SystemZ::TMHH, false);
1006 case SystemZ::AHIMux:
1007 expandRIPseudo(MI, SystemZ::AHI, SystemZ::AIH, false);
1010 case SystemZ::AHIMuxK:
1011 expandRIEPseudo(MI, SystemZ::AHI, SystemZ::AHIK, SystemZ::AIH);
1014 case SystemZ::AFIMux:
1015 expandRIPseudo(MI, SystemZ::AFI, SystemZ::AIH, false);
1018 case SystemZ::CFIMux:
1019 expandRIPseudo(MI, SystemZ::CFI, SystemZ::CIH, false);
1022 case SystemZ::CLFIMux:
1023 expandRIPseudo(MI, SystemZ::CLFI, SystemZ::CLIH, false);
1027 expandRXYPseudo(MI, SystemZ::C, SystemZ::CHF);
1030 case SystemZ::CLMux:
1031 expandRXYPseudo(MI, SystemZ::CL, SystemZ::CLHF);
1034 case SystemZ::RISBMux: {
1035 bool DestIsHigh = isHighReg(MI->getOperand(0).getReg());
1036 bool SrcIsHigh = isHighReg(MI->getOperand(2).getReg());
1037 if (SrcIsHigh == DestIsHigh)
1038 MI->setDesc(get(DestIsHigh ? SystemZ::RISBHH : SystemZ::RISBLL));
1040 MI->setDesc(get(DestIsHigh ? SystemZ::RISBHL : SystemZ::RISBLH));
1041 MI->getOperand(5).setImm(MI->getOperand(5).getImm() ^ 32);
1046 case SystemZ::ADJDYNALLOC:
1047 splitAdjDynAlloc(MI);
1055 uint64_t SystemZInstrInfo::getInstSizeInBytes(const MachineInstr *MI) const {
1056 if (MI->getOpcode() == TargetOpcode::INLINEASM) {
1057 const MachineFunction *MF = MI->getParent()->getParent();
1058 const char *AsmStr = MI->getOperand(0).getSymbolName();
1059 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1061 return MI->getDesc().getSize();
1065 SystemZInstrInfo::getBranchInfo(const MachineInstr *MI) const {
1066 switch (MI->getOpcode()) {
1070 return SystemZII::Branch(SystemZII::BranchNormal, SystemZ::CCMASK_ANY,
1071 SystemZ::CCMASK_ANY, &MI->getOperand(0));
1075 return SystemZII::Branch(SystemZII::BranchNormal,
1076 MI->getOperand(0).getImm(),
1077 MI->getOperand(1).getImm(), &MI->getOperand(2));
1080 return SystemZII::Branch(SystemZII::BranchCT, SystemZ::CCMASK_ICMP,
1081 SystemZ::CCMASK_CMP_NE, &MI->getOperand(2));
1083 case SystemZ::BRCTG:
1084 return SystemZII::Branch(SystemZII::BranchCTG, SystemZ::CCMASK_ICMP,
1085 SystemZ::CCMASK_CMP_NE, &MI->getOperand(2));
1089 return SystemZII::Branch(SystemZII::BranchC, SystemZ::CCMASK_ICMP,
1090 MI->getOperand(2).getImm(), &MI->getOperand(3));
1094 return SystemZII::Branch(SystemZII::BranchCL, SystemZ::CCMASK_ICMP,
1095 MI->getOperand(2).getImm(), &MI->getOperand(3));
1099 return SystemZII::Branch(SystemZII::BranchCG, SystemZ::CCMASK_ICMP,
1100 MI->getOperand(2).getImm(), &MI->getOperand(3));
1102 case SystemZ::CLGIJ:
1103 case SystemZ::CLGRJ:
1104 return SystemZII::Branch(SystemZII::BranchCLG, SystemZ::CCMASK_ICMP,
1105 MI->getOperand(2).getImm(), &MI->getOperand(3));
1108 llvm_unreachable("Unrecognized branch opcode");
1112 void SystemZInstrInfo::getLoadStoreOpcodes(const TargetRegisterClass *RC,
1113 unsigned &LoadOpcode,
1114 unsigned &StoreOpcode) const {
1115 if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) {
1116 LoadOpcode = SystemZ::L;
1117 StoreOpcode = SystemZ::ST;
1118 } else if (RC == &SystemZ::GRH32BitRegClass) {
1119 LoadOpcode = SystemZ::LFH;
1120 StoreOpcode = SystemZ::STFH;
1121 } else if (RC == &SystemZ::GRX32BitRegClass) {
1122 LoadOpcode = SystemZ::LMux;
1123 StoreOpcode = SystemZ::STMux;
1124 } else if (RC == &SystemZ::GR64BitRegClass ||
1125 RC == &SystemZ::ADDR64BitRegClass) {
1126 LoadOpcode = SystemZ::LG;
1127 StoreOpcode = SystemZ::STG;
1128 } else if (RC == &SystemZ::GR128BitRegClass ||
1129 RC == &SystemZ::ADDR128BitRegClass) {
1130 LoadOpcode = SystemZ::L128;
1131 StoreOpcode = SystemZ::ST128;
1132 } else if (RC == &SystemZ::FP32BitRegClass) {
1133 LoadOpcode = SystemZ::LE;
1134 StoreOpcode = SystemZ::STE;
1135 } else if (RC == &SystemZ::FP64BitRegClass) {
1136 LoadOpcode = SystemZ::LD;
1137 StoreOpcode = SystemZ::STD;
1138 } else if (RC == &SystemZ::FP128BitRegClass) {
1139 LoadOpcode = SystemZ::LX;
1140 StoreOpcode = SystemZ::STX;
1141 } else if (RC == &SystemZ::VR32BitRegClass) {
1142 LoadOpcode = SystemZ::VL32;
1143 StoreOpcode = SystemZ::VST32;
1144 } else if (RC == &SystemZ::VR64BitRegClass) {
1145 LoadOpcode = SystemZ::VL64;
1146 StoreOpcode = SystemZ::VST64;
1147 } else if (RC == &SystemZ::VF128BitRegClass ||
1148 RC == &SystemZ::VR128BitRegClass) {
1149 LoadOpcode = SystemZ::VL;
1150 StoreOpcode = SystemZ::VST;
1152 llvm_unreachable("Unsupported regclass to load or store");
1155 unsigned SystemZInstrInfo::getOpcodeForOffset(unsigned Opcode,
1156 int64_t Offset) const {
1157 const MCInstrDesc &MCID = get(Opcode);
1158 int64_t Offset2 = (MCID.TSFlags & SystemZII::Is128Bit ? Offset + 8 : Offset);
1159 if (isUInt<12>(Offset) && isUInt<12>(Offset2)) {
1160 // Get the instruction to use for unsigned 12-bit displacements.
1161 int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
1162 if (Disp12Opcode >= 0)
1163 return Disp12Opcode;
1165 // All address-related instructions can use unsigned 12-bit
1169 if (isInt<20>(Offset) && isInt<20>(Offset2)) {
1170 // Get the instruction to use for signed 20-bit displacements.
1171 int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
1172 if (Disp20Opcode >= 0)
1173 return Disp20Opcode;
1175 // Check whether Opcode allows signed 20-bit displacements.
1176 if (MCID.TSFlags & SystemZII::Has20BitOffset)
1182 unsigned SystemZInstrInfo::getLoadAndTest(unsigned Opcode) const {
1184 case SystemZ::L: return SystemZ::LT;
1185 case SystemZ::LY: return SystemZ::LT;
1186 case SystemZ::LG: return SystemZ::LTG;
1187 case SystemZ::LGF: return SystemZ::LTGF;
1188 case SystemZ::LR: return SystemZ::LTR;
1189 case SystemZ::LGFR: return SystemZ::LTGFR;
1190 case SystemZ::LGR: return SystemZ::LTGR;
1191 case SystemZ::LER: return SystemZ::LTEBR;
1192 case SystemZ::LDR: return SystemZ::LTDBR;
1193 case SystemZ::LXR: return SystemZ::LTXBR;
1194 // On zEC12 we prefer to use RISBGN. But if there is a chance to
1195 // actually use the condition code, we may turn it back into RISGB.
1196 // Note that RISBG is not really a "load-and-test" instruction,
1197 // but sets the same condition code values, so is OK to use here.
1198 case SystemZ::RISBGN: return SystemZ::RISBG;
1203 // Return true if Mask matches the regexp 0*1+0*, given that zero masks
1204 // have already been filtered out. Store the first set bit in LSB and
1205 // the number of set bits in Length if so.
1206 static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length) {
1207 unsigned First = findFirstSet(Mask);
1208 uint64_t Top = (Mask >> First) + 1;
1209 if ((Top & -Top) == Top) {
1211 Length = findFirstSet(Top);
1217 bool SystemZInstrInfo::isRxSBGMask(uint64_t Mask, unsigned BitSize,
1218 unsigned &Start, unsigned &End) const {
1219 // Reject trivial all-zero masks.
1220 Mask &= allOnes(BitSize);
1224 // Handle the 1+0+ or 0+1+0* cases. Start then specifies the index of
1225 // the msb and End specifies the index of the lsb.
1226 unsigned LSB, Length;
1227 if (isStringOfOnes(Mask, LSB, Length)) {
1228 Start = 63 - (LSB + Length - 1);
1233 // Handle the wrap-around 1+0+1+ cases. Start then specifies the msb
1234 // of the low 1s and End specifies the lsb of the high 1s.
1235 if (isStringOfOnes(Mask ^ allOnes(BitSize), LSB, Length)) {
1236 assert(LSB > 0 && "Bottom bit must be set");
1237 assert(LSB + Length < BitSize && "Top bit must be set");
1238 Start = 63 - (LSB - 1);
1239 End = 63 - (LSB + Length);
1246 unsigned SystemZInstrInfo::getCompareAndBranch(unsigned Opcode,
1247 const MachineInstr *MI) const {
1250 return SystemZ::CRJ;
1252 return SystemZ::CGRJ;
1254 return MI && isInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CIJ : 0;
1256 return MI && isInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CGIJ : 0;
1258 return SystemZ::CLRJ;
1260 return SystemZ::CLGRJ;
1262 return MI && isUInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CLIJ : 0;
1263 case SystemZ::CLGFI:
1264 return MI && isUInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CLGIJ : 0;
1270 void SystemZInstrInfo::loadImmediate(MachineBasicBlock &MBB,
1271 MachineBasicBlock::iterator MBBI,
1272 unsigned Reg, uint64_t Value) const {
1273 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1275 if (isInt<16>(Value))
1276 Opcode = SystemZ::LGHI;
1277 else if (SystemZ::isImmLL(Value))
1278 Opcode = SystemZ::LLILL;
1279 else if (SystemZ::isImmLH(Value)) {
1280 Opcode = SystemZ::LLILH;
1283 assert(isInt<32>(Value) && "Huge values not handled yet");
1284 Opcode = SystemZ::LGFI;
1286 BuildMI(MBB, MBBI, DL, get(Opcode), Reg).addImm(Value);