1 //===-- SystemZInstrInfo.cpp - SystemZ instruction information ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SystemZ implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "SystemZInstrInfo.h"
15 #include "SystemZInstrBuilder.h"
16 #include "SystemZTargetMachine.h"
17 #include "llvm/CodeGen/LiveVariables.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #define GET_INSTRINFO_CTOR_DTOR
23 #define GET_INSTRMAP_INFO
24 #include "SystemZGenInstrInfo.inc"
26 // Return a mask with Count low bits set.
27 static uint64_t allOnes(unsigned int Count) {
28 return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1;
31 // Reg should be a 32-bit GPR. Return true if it is a high register rather
32 // than a low register.
33 static bool isHighReg(unsigned int Reg) {
34 if (SystemZ::GRH32BitRegClass.contains(Reg))
36 assert(SystemZ::GR32BitRegClass.contains(Reg) && "Invalid GRX32");
40 // Pin the vtable to this file.
41 void SystemZInstrInfo::anchor() {}
43 SystemZInstrInfo::SystemZInstrInfo(SystemZSubtarget &sti)
44 : SystemZGenInstrInfo(SystemZ::ADJCALLSTACKDOWN, SystemZ::ADJCALLSTACKUP),
48 // MI is a 128-bit load or store. Split it into two 64-bit loads or stores,
49 // each having the opcode given by NewOpcode.
50 void SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI,
51 unsigned NewOpcode) const {
52 MachineBasicBlock *MBB = MI->getParent();
53 MachineFunction &MF = *MBB->getParent();
55 // Get two load or store instructions. Use the original instruction for one
56 // of them (arbitrarily the second here) and create a clone for the other.
57 MachineInstr *EarlierMI = MF.CloneMachineInstr(MI);
58 MBB->insert(MI, EarlierMI);
60 // Set up the two 64-bit registers.
61 MachineOperand &HighRegOp = EarlierMI->getOperand(0);
62 MachineOperand &LowRegOp = MI->getOperand(0);
63 HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64));
64 LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64));
66 // The address in the first (high) instruction is already correct.
67 // Adjust the offset in the second (low) instruction.
68 MachineOperand &HighOffsetOp = EarlierMI->getOperand(2);
69 MachineOperand &LowOffsetOp = MI->getOperand(2);
70 LowOffsetOp.setImm(LowOffsetOp.getImm() + 8);
72 // Clear the kill flag for the address reg in the first instruction.
73 EarlierMI->getOperand(1).setIsKill(false);
76 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm());
77 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm());
78 assert(HighOpcode && LowOpcode && "Both offsets should be in range");
80 EarlierMI->setDesc(get(HighOpcode));
81 MI->setDesc(get(LowOpcode));
84 // Split ADJDYNALLOC instruction MI.
85 void SystemZInstrInfo::splitAdjDynAlloc(MachineBasicBlock::iterator MI) const {
86 MachineBasicBlock *MBB = MI->getParent();
87 MachineFunction &MF = *MBB->getParent();
88 MachineFrameInfo *MFFrame = MF.getFrameInfo();
89 MachineOperand &OffsetMO = MI->getOperand(2);
91 uint64_t Offset = (MFFrame->getMaxCallFrameSize() +
92 SystemZMC::CallFrameSize +
94 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset);
95 assert(NewOpcode && "No support for huge argument lists yet");
96 MI->setDesc(get(NewOpcode));
97 OffsetMO.setImm(Offset);
100 // MI is an RI-style pseudo instruction. Replace it with LowOpcode
101 // if the first operand is a low GR32 and HighOpcode if the first operand
102 // is a high GR32. ConvertHigh is true if LowOpcode takes a signed operand
103 // and HighOpcode takes an unsigned 32-bit operand. In those cases,
104 // MI has the same kind of operand as LowOpcode, so needs to be converted
105 // if HighOpcode is used.
106 void SystemZInstrInfo::expandRIPseudo(MachineInstr *MI, unsigned LowOpcode,
108 bool ConvertHigh) const {
109 unsigned Reg = MI->getOperand(0).getReg();
110 bool IsHigh = isHighReg(Reg);
111 MI->setDesc(get(IsHigh ? HighOpcode : LowOpcode));
112 if (IsHigh && ConvertHigh)
113 MI->getOperand(1).setImm(uint32_t(MI->getOperand(1).getImm()));
116 // MI is a three-operand RIE-style pseudo instruction. Replace it with
117 // LowOpcodeK if the registers are both low GR32s, otherwise use a move
118 // followed by HighOpcode or LowOpcode, depending on whether the target
119 // is a high or low GR32.
120 void SystemZInstrInfo::expandRIEPseudo(MachineInstr *MI, unsigned LowOpcode,
122 unsigned HighOpcode) const {
123 unsigned DestReg = MI->getOperand(0).getReg();
124 unsigned SrcReg = MI->getOperand(1).getReg();
125 bool DestIsHigh = isHighReg(DestReg);
126 bool SrcIsHigh = isHighReg(SrcReg);
127 if (!DestIsHigh && !SrcIsHigh)
128 MI->setDesc(get(LowOpcodeK));
130 emitGRX32Move(*MI->getParent(), MI, MI->getDebugLoc(),
131 DestReg, SrcReg, SystemZ::LR, 32,
132 MI->getOperand(1).isKill());
133 MI->setDesc(get(DestIsHigh ? HighOpcode : LowOpcode));
134 MI->getOperand(1).setReg(DestReg);
135 MI->tieOperands(0, 1);
139 // MI is an RXY-style pseudo instruction. Replace it with LowOpcode
140 // if the first operand is a low GR32 and HighOpcode if the first operand
142 void SystemZInstrInfo::expandRXYPseudo(MachineInstr *MI, unsigned LowOpcode,
143 unsigned HighOpcode) const {
144 unsigned Reg = MI->getOperand(0).getReg();
145 unsigned Opcode = getOpcodeForOffset(isHighReg(Reg) ? HighOpcode : LowOpcode,
146 MI->getOperand(2).getImm());
147 MI->setDesc(get(Opcode));
150 // MI is an RR-style pseudo instruction that zero-extends the low Size bits
151 // of one GRX32 into another. Replace it with LowOpcode if both operands
152 // are low registers, otherwise use RISB[LH]G.
153 void SystemZInstrInfo::expandZExtPseudo(MachineInstr *MI, unsigned LowOpcode,
154 unsigned Size) const {
155 emitGRX32Move(*MI->getParent(), MI, MI->getDebugLoc(),
156 MI->getOperand(0).getReg(), MI->getOperand(1).getReg(),
157 LowOpcode, Size, MI->getOperand(1).isKill());
158 MI->eraseFromParent();
161 // Emit a zero-extending move from 32-bit GPR SrcReg to 32-bit GPR
162 // DestReg before MBBI in MBB. Use LowLowOpcode when both DestReg and SrcReg
163 // are low registers, otherwise use RISB[LH]G. Size is the number of bits
164 // taken from the low end of SrcReg (8 for LLCR, 16 for LLHR and 32 for LR).
165 // KillSrc is true if this move is the last use of SrcReg.
166 void SystemZInstrInfo::emitGRX32Move(MachineBasicBlock &MBB,
167 MachineBasicBlock::iterator MBBI,
168 DebugLoc DL, unsigned DestReg,
169 unsigned SrcReg, unsigned LowLowOpcode,
170 unsigned Size, bool KillSrc) const {
172 bool DestIsHigh = isHighReg(DestReg);
173 bool SrcIsHigh = isHighReg(SrcReg);
174 if (DestIsHigh && SrcIsHigh)
175 Opcode = SystemZ::RISBHH;
176 else if (DestIsHigh && !SrcIsHigh)
177 Opcode = SystemZ::RISBHL;
178 else if (!DestIsHigh && SrcIsHigh)
179 Opcode = SystemZ::RISBLH;
181 BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg)
182 .addReg(SrcReg, getKillRegState(KillSrc));
185 unsigned Rotate = (DestIsHigh != SrcIsHigh ? 32 : 0);
186 BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
187 .addReg(DestReg, RegState::Undef)
188 .addReg(SrcReg, getKillRegState(KillSrc))
189 .addImm(32 - Size).addImm(128 + 31).addImm(Rotate);
192 // If MI is a simple load or store for a frame object, return the register
193 // it loads or stores and set FrameIndex to the index of the frame object.
194 // Return 0 otherwise.
196 // Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
197 static int isSimpleMove(const MachineInstr *MI, int &FrameIndex,
199 const MCInstrDesc &MCID = MI->getDesc();
200 if ((MCID.TSFlags & Flag) &&
201 MI->getOperand(1).isFI() &&
202 MI->getOperand(2).getImm() == 0 &&
203 MI->getOperand(3).getReg() == 0) {
204 FrameIndex = MI->getOperand(1).getIndex();
205 return MI->getOperand(0).getReg();
210 unsigned SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
211 int &FrameIndex) const {
212 return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXLoad);
215 unsigned SystemZInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
216 int &FrameIndex) const {
217 return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXStore);
220 bool SystemZInstrInfo::isStackSlotCopy(const MachineInstr *MI,
222 int &SrcFrameIndex) const {
223 // Check for MVC 0(Length,FI1),0(FI2)
224 const MachineFrameInfo *MFI = MI->getParent()->getParent()->getFrameInfo();
225 if (MI->getOpcode() != SystemZ::MVC ||
226 !MI->getOperand(0).isFI() ||
227 MI->getOperand(1).getImm() != 0 ||
228 !MI->getOperand(3).isFI() ||
229 MI->getOperand(4).getImm() != 0)
232 // Check that Length covers the full slots.
233 int64_t Length = MI->getOperand(2).getImm();
234 unsigned FI1 = MI->getOperand(0).getIndex();
235 unsigned FI2 = MI->getOperand(3).getIndex();
236 if (MFI->getObjectSize(FI1) != Length ||
237 MFI->getObjectSize(FI2) != Length)
240 DestFrameIndex = FI1;
245 bool SystemZInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
246 MachineBasicBlock *&TBB,
247 MachineBasicBlock *&FBB,
248 SmallVectorImpl<MachineOperand> &Cond,
249 bool AllowModify) const {
250 // Most of the code and comments here are boilerplate.
252 // Start from the bottom of the block and work up, examining the
253 // terminator instructions.
254 MachineBasicBlock::iterator I = MBB.end();
255 while (I != MBB.begin()) {
257 if (I->isDebugValue())
260 // Working from the bottom, when we see a non-terminator instruction, we're
262 if (!isUnpredicatedTerminator(I))
265 // A terminator that isn't a branch can't easily be handled by this
270 // Can't handle indirect branches.
271 SystemZII::Branch Branch(getBranchInfo(I));
272 if (!Branch.Target->isMBB())
275 // Punt on compound branches.
276 if (Branch.Type != SystemZII::BranchNormal)
279 if (Branch.CCMask == SystemZ::CCMASK_ANY) {
280 // Handle unconditional branches.
282 TBB = Branch.Target->getMBB();
286 // If the block has any instructions after a JMP, delete them.
287 while (std::next(I) != MBB.end())
288 std::next(I)->eraseFromParent();
293 // Delete the JMP if it's equivalent to a fall-through.
294 if (MBB.isLayoutSuccessor(Branch.Target->getMBB())) {
296 I->eraseFromParent();
301 // TBB is used to indicate the unconditinal destination.
302 TBB = Branch.Target->getMBB();
306 // Working from the bottom, handle the first conditional branch.
308 // FIXME: add X86-style branch swap
310 TBB = Branch.Target->getMBB();
311 Cond.push_back(MachineOperand::CreateImm(Branch.CCValid));
312 Cond.push_back(MachineOperand::CreateImm(Branch.CCMask));
316 // Handle subsequent conditional branches.
317 assert(Cond.size() == 2 && TBB && "Should have seen a conditional branch");
319 // Only handle the case where all conditional branches branch to the same
321 if (TBB != Branch.Target->getMBB())
324 // If the conditions are the same, we can leave them alone.
325 unsigned OldCCValid = Cond[0].getImm();
326 unsigned OldCCMask = Cond[1].getImm();
327 if (OldCCValid == Branch.CCValid && OldCCMask == Branch.CCMask)
330 // FIXME: Try combining conditions like X86 does. Should be easy on Z!
337 unsigned SystemZInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
338 // Most of the code and comments here are boilerplate.
339 MachineBasicBlock::iterator I = MBB.end();
342 while (I != MBB.begin()) {
344 if (I->isDebugValue())
348 if (!getBranchInfo(I).Target->isMBB())
350 // Remove the branch.
351 I->eraseFromParent();
359 bool SystemZInstrInfo::
360 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
361 assert(Cond.size() == 2 && "Invalid condition");
362 Cond[1].setImm(Cond[1].getImm() ^ Cond[0].getImm());
367 SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
368 MachineBasicBlock *FBB,
369 ArrayRef<MachineOperand> Cond,
371 // In this function we output 32-bit branches, which should always
372 // have enough range. They can be shortened and relaxed by later code
373 // in the pipeline, if desired.
375 // Shouldn't be a fall through.
376 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
377 assert((Cond.size() == 2 || Cond.size() == 0) &&
378 "SystemZ branch conditions have one component!");
381 // Unconditional branch?
382 assert(!FBB && "Unconditional branch with multiple successors!");
383 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(TBB);
387 // Conditional branch.
389 unsigned CCValid = Cond[0].getImm();
390 unsigned CCMask = Cond[1].getImm();
391 BuildMI(&MBB, DL, get(SystemZ::BRC))
392 .addImm(CCValid).addImm(CCMask).addMBB(TBB);
396 // Two-way Conditional branch. Insert the second branch.
397 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(FBB);
403 bool SystemZInstrInfo::analyzeCompare(const MachineInstr *MI,
404 unsigned &SrcReg, unsigned &SrcReg2,
405 int &Mask, int &Value) const {
406 assert(MI->isCompare() && "Caller should have checked for a comparison");
408 if (MI->getNumExplicitOperands() == 2 &&
409 MI->getOperand(0).isReg() &&
410 MI->getOperand(1).isImm()) {
411 SrcReg = MI->getOperand(0).getReg();
413 Value = MI->getOperand(1).getImm();
421 // If Reg is a virtual register, return its definition, otherwise return null.
422 static MachineInstr *getDef(unsigned Reg,
423 const MachineRegisterInfo *MRI) {
424 if (TargetRegisterInfo::isPhysicalRegister(Reg))
426 return MRI->getUniqueVRegDef(Reg);
429 // Return true if MI is a shift of type Opcode by Imm bits.
430 static bool isShift(MachineInstr *MI, unsigned Opcode, int64_t Imm) {
431 return (MI->getOpcode() == Opcode &&
432 !MI->getOperand(2).getReg() &&
433 MI->getOperand(3).getImm() == Imm);
436 // If the destination of MI has no uses, delete it as dead.
437 static void eraseIfDead(MachineInstr *MI, const MachineRegisterInfo *MRI) {
438 if (MRI->use_nodbg_empty(MI->getOperand(0).getReg()))
439 MI->eraseFromParent();
442 // Compare compares SrcReg against zero. Check whether SrcReg contains
443 // the result of an IPM sequence whose input CC survives until Compare,
444 // and whether Compare is therefore redundant. Delete it and return
446 static bool removeIPMBasedCompare(MachineInstr *Compare, unsigned SrcReg,
447 const MachineRegisterInfo *MRI,
448 const TargetRegisterInfo *TRI) {
449 MachineInstr *LGFR = nullptr;
450 MachineInstr *RLL = getDef(SrcReg, MRI);
451 if (RLL && RLL->getOpcode() == SystemZ::LGFR) {
453 RLL = getDef(LGFR->getOperand(1).getReg(), MRI);
455 if (!RLL || !isShift(RLL, SystemZ::RLL, 31))
458 MachineInstr *SRL = getDef(RLL->getOperand(1).getReg(), MRI);
459 if (!SRL || !isShift(SRL, SystemZ::SRL, SystemZ::IPM_CC))
462 MachineInstr *IPM = getDef(SRL->getOperand(1).getReg(), MRI);
463 if (!IPM || IPM->getOpcode() != SystemZ::IPM)
466 // Check that there are no assignments to CC between the IPM and Compare,
467 if (IPM->getParent() != Compare->getParent())
469 MachineBasicBlock::iterator MBBI = IPM, MBBE = Compare;
470 for (++MBBI; MBBI != MBBE; ++MBBI) {
471 MachineInstr *MI = MBBI;
472 if (MI->modifiesRegister(SystemZ::CC, TRI))
476 Compare->eraseFromParent();
478 eraseIfDead(LGFR, MRI);
479 eraseIfDead(RLL, MRI);
480 eraseIfDead(SRL, MRI);
481 eraseIfDead(IPM, MRI);
487 SystemZInstrInfo::optimizeCompareInstr(MachineInstr *Compare,
488 unsigned SrcReg, unsigned SrcReg2,
490 const MachineRegisterInfo *MRI) const {
491 assert(!SrcReg2 && "Only optimizing constant comparisons so far");
492 bool IsLogical = (Compare->getDesc().TSFlags & SystemZII::IsLogical) != 0;
495 removeIPMBasedCompare(Compare, SrcReg, MRI, &RI))
500 // If Opcode is a move that has a conditional variant, return that variant,
501 // otherwise return 0.
502 static unsigned getConditionalMove(unsigned Opcode) {
504 case SystemZ::LR: return SystemZ::LOCR;
505 case SystemZ::LGR: return SystemZ::LOCGR;
510 bool SystemZInstrInfo::isPredicable(MachineInstr *MI) const {
511 unsigned Opcode = MI->getOpcode();
512 if (STI.hasLoadStoreOnCond() &&
513 getConditionalMove(Opcode))
518 bool SystemZInstrInfo::
519 isProfitableToIfCvt(MachineBasicBlock &MBB,
520 unsigned NumCycles, unsigned ExtraPredCycles,
521 BranchProbability Probability) const {
522 // For now only convert single instructions.
523 return NumCycles == 1;
526 bool SystemZInstrInfo::
527 isProfitableToIfCvt(MachineBasicBlock &TMBB,
528 unsigned NumCyclesT, unsigned ExtraPredCyclesT,
529 MachineBasicBlock &FMBB,
530 unsigned NumCyclesF, unsigned ExtraPredCyclesF,
531 BranchProbability Probability) const {
532 // For now avoid converting mutually-exclusive cases.
536 bool SystemZInstrInfo::
537 PredicateInstruction(MachineInstr *MI, ArrayRef<MachineOperand> Pred) const {
538 assert(Pred.size() == 2 && "Invalid condition");
539 unsigned CCValid = Pred[0].getImm();
540 unsigned CCMask = Pred[1].getImm();
541 assert(CCMask > 0 && CCMask < 15 && "Invalid predicate");
542 unsigned Opcode = MI->getOpcode();
543 if (STI.hasLoadStoreOnCond()) {
544 if (unsigned CondOpcode = getConditionalMove(Opcode)) {
545 MI->setDesc(get(CondOpcode));
546 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
547 .addImm(CCValid).addImm(CCMask)
548 .addReg(SystemZ::CC, RegState::Implicit);
555 void SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
556 MachineBasicBlock::iterator MBBI,
557 DebugLoc DL, unsigned DestReg,
558 unsigned SrcReg, bool KillSrc) const {
559 // Split 128-bit GPR moves into two 64-bit moves. This handles ADDR128 too.
560 if (SystemZ::GR128BitRegClass.contains(DestReg, SrcReg)) {
561 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_h64),
562 RI.getSubReg(SrcReg, SystemZ::subreg_h64), KillSrc);
563 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_l64),
564 RI.getSubReg(SrcReg, SystemZ::subreg_l64), KillSrc);
568 if (SystemZ::GRX32BitRegClass.contains(DestReg, SrcReg)) {
569 emitGRX32Move(MBB, MBBI, DL, DestReg, SrcReg, SystemZ::LR, 32, KillSrc);
573 // Everything else needs only one instruction.
575 if (SystemZ::GR64BitRegClass.contains(DestReg, SrcReg))
576 Opcode = SystemZ::LGR;
577 else if (SystemZ::FP32BitRegClass.contains(DestReg, SrcReg))
578 Opcode = SystemZ::LER;
579 else if (SystemZ::FP64BitRegClass.contains(DestReg, SrcReg))
580 Opcode = SystemZ::LDR;
581 else if (SystemZ::FP128BitRegClass.contains(DestReg, SrcReg))
582 Opcode = SystemZ::LXR;
583 else if (SystemZ::VR32BitRegClass.contains(DestReg, SrcReg))
584 Opcode = SystemZ::VLR32;
585 else if (SystemZ::VR64BitRegClass.contains(DestReg, SrcReg))
586 Opcode = SystemZ::VLR64;
587 else if (SystemZ::VR128BitRegClass.contains(DestReg, SrcReg))
588 Opcode = SystemZ::VLR;
590 llvm_unreachable("Impossible reg-to-reg copy");
592 BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
593 .addReg(SrcReg, getKillRegState(KillSrc));
596 void SystemZInstrInfo::storeRegToStackSlot(
597 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg,
598 bool isKill, int FrameIdx, const TargetRegisterClass *RC,
599 const TargetRegisterInfo *TRI) const {
600 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
602 // Callers may expect a single instruction, so keep 128-bit moves
603 // together for now and lower them after register allocation.
604 unsigned LoadOpcode, StoreOpcode;
605 getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
606 addFrameReference(BuildMI(MBB, MBBI, DL, get(StoreOpcode))
607 .addReg(SrcReg, getKillRegState(isKill)),
611 void SystemZInstrInfo::loadRegFromStackSlot(
612 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg,
613 int FrameIdx, const TargetRegisterClass *RC,
614 const TargetRegisterInfo *TRI) const {
615 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
617 // Callers may expect a single instruction, so keep 128-bit moves
618 // together for now and lower them after register allocation.
619 unsigned LoadOpcode, StoreOpcode;
620 getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
621 addFrameReference(BuildMI(MBB, MBBI, DL, get(LoadOpcode), DestReg),
625 // Return true if MI is a simple load or store with a 12-bit displacement
626 // and no index. Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
627 static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag) {
628 const MCInstrDesc &MCID = MI->getDesc();
629 return ((MCID.TSFlags & Flag) &&
630 isUInt<12>(MI->getOperand(2).getImm()) &&
631 MI->getOperand(3).getReg() == 0);
636 LogicOp() : RegSize(0), ImmLSB(0), ImmSize(0) {}
637 LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize)
638 : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}
640 explicit operator bool() const { return RegSize; }
642 unsigned RegSize, ImmLSB, ImmSize;
644 } // end anonymous namespace
646 static LogicOp interpretAndImmediate(unsigned Opcode) {
648 case SystemZ::NILMux: return LogicOp(32, 0, 16);
649 case SystemZ::NIHMux: return LogicOp(32, 16, 16);
650 case SystemZ::NILL64: return LogicOp(64, 0, 16);
651 case SystemZ::NILH64: return LogicOp(64, 16, 16);
652 case SystemZ::NIHL64: return LogicOp(64, 32, 16);
653 case SystemZ::NIHH64: return LogicOp(64, 48, 16);
654 case SystemZ::NIFMux: return LogicOp(32, 0, 32);
655 case SystemZ::NILF64: return LogicOp(64, 0, 32);
656 case SystemZ::NIHF64: return LogicOp(64, 32, 32);
657 default: return LogicOp();
661 // Used to return from convertToThreeAddress after replacing two-address
662 // instruction OldMI with three-address instruction NewMI.
663 static MachineInstr *finishConvertToThreeAddress(MachineInstr *OldMI,
667 unsigned NumOps = OldMI->getNumOperands();
668 for (unsigned I = 1; I < NumOps; ++I) {
669 MachineOperand &Op = OldMI->getOperand(I);
670 if (Op.isReg() && Op.isKill())
671 LV->replaceKillInstruction(Op.getReg(), OldMI, NewMI);
678 SystemZInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
679 MachineBasicBlock::iterator &MBBI,
680 LiveVariables *LV) const {
681 MachineInstr *MI = MBBI;
682 MachineBasicBlock *MBB = MI->getParent();
683 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
685 unsigned Opcode = MI->getOpcode();
686 unsigned NumOps = MI->getNumOperands();
688 // Try to convert something like SLL into SLLK, if supported.
689 // We prefer to keep the two-operand form where possible both
690 // because it tends to be shorter and because some instructions
691 // have memory forms that can be used during spilling.
692 if (STI.hasDistinctOps()) {
693 MachineOperand &Dest = MI->getOperand(0);
694 MachineOperand &Src = MI->getOperand(1);
695 unsigned DestReg = Dest.getReg();
696 unsigned SrcReg = Src.getReg();
697 // AHIMux is only really a three-operand instruction when both operands
698 // are low registers. Try to constrain both operands to be low if
700 if (Opcode == SystemZ::AHIMux &&
701 TargetRegisterInfo::isVirtualRegister(DestReg) &&
702 TargetRegisterInfo::isVirtualRegister(SrcReg) &&
703 MRI.getRegClass(DestReg)->contains(SystemZ::R1L) &&
704 MRI.getRegClass(SrcReg)->contains(SystemZ::R1L)) {
705 MRI.constrainRegClass(DestReg, &SystemZ::GR32BitRegClass);
706 MRI.constrainRegClass(SrcReg, &SystemZ::GR32BitRegClass);
708 int ThreeOperandOpcode = SystemZ::getThreeOperandOpcode(Opcode);
709 if (ThreeOperandOpcode >= 0) {
710 MachineInstrBuilder MIB =
711 BuildMI(*MBB, MBBI, MI->getDebugLoc(), get(ThreeOperandOpcode))
713 // Keep the kill state, but drop the tied flag.
714 MIB.addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg());
715 // Keep the remaining operands as-is.
716 for (unsigned I = 2; I < NumOps; ++I)
717 MIB.addOperand(MI->getOperand(I));
718 return finishConvertToThreeAddress(MI, MIB, LV);
722 // Try to convert an AND into an RISBG-type instruction.
723 if (LogicOp And = interpretAndImmediate(Opcode)) {
724 uint64_t Imm = MI->getOperand(2).getImm() << And.ImmLSB;
725 // AND IMMEDIATE leaves the other bits of the register unchanged.
726 Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB);
728 if (isRxSBGMask(Imm, And.RegSize, Start, End)) {
730 if (And.RegSize == 64) {
731 NewOpcode = SystemZ::RISBG;
732 // Prefer RISBGN if available, since it does not clobber CC.
733 if (STI.hasMiscellaneousExtensions())
734 NewOpcode = SystemZ::RISBGN;
736 NewOpcode = SystemZ::RISBMux;
740 MachineOperand &Dest = MI->getOperand(0);
741 MachineOperand &Src = MI->getOperand(1);
742 MachineInstrBuilder MIB =
743 BuildMI(*MBB, MI, MI->getDebugLoc(), get(NewOpcode))
744 .addOperand(Dest).addReg(0)
745 .addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg())
746 .addImm(Start).addImm(End + 128).addImm(0);
747 return finishConvertToThreeAddress(MI, MIB, LV);
753 MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
754 MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops,
755 MachineBasicBlock::iterator InsertPt, int FrameIndex) const {
756 const MachineFrameInfo *MFI = MF.getFrameInfo();
757 unsigned Size = MFI->getObjectSize(FrameIndex);
758 unsigned Opcode = MI->getOpcode();
760 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
761 if ((Opcode == SystemZ::LA || Opcode == SystemZ::LAY) &&
762 isInt<8>(MI->getOperand(2).getImm()) &&
763 !MI->getOperand(3).getReg()) {
764 // LA(Y) %reg, CONST(%reg) -> AGSI %mem, CONST
765 return BuildMI(*InsertPt->getParent(), InsertPt, MI->getDebugLoc(),
767 .addFrameIndex(FrameIndex)
769 .addImm(MI->getOperand(2).getImm());
774 // All other cases require a single operand.
778 unsigned OpNum = Ops[0];
779 assert(Size == MF.getRegInfo()
780 .getRegClass(MI->getOperand(OpNum).getReg())->getSize() &&
781 "Invalid size combination");
783 if ((Opcode == SystemZ::AHI || Opcode == SystemZ::AGHI) &&
785 isInt<8>(MI->getOperand(2).getImm())) {
786 // A(G)HI %reg, CONST -> A(G)SI %mem, CONST
787 Opcode = (Opcode == SystemZ::AHI ? SystemZ::ASI : SystemZ::AGSI);
788 return BuildMI(*InsertPt->getParent(), InsertPt, MI->getDebugLoc(),
790 .addFrameIndex(FrameIndex)
792 .addImm(MI->getOperand(2).getImm());
795 if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {
796 bool Op0IsGPR = (Opcode == SystemZ::LGDR);
797 bool Op1IsGPR = (Opcode == SystemZ::LDGR);
798 // If we're spilling the destination of an LDGR or LGDR, store the
799 // source register instead.
801 unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD;
802 return BuildMI(*InsertPt->getParent(), InsertPt, MI->getDebugLoc(),
804 .addOperand(MI->getOperand(1))
805 .addFrameIndex(FrameIndex)
809 // If we're spilling the source of an LDGR or LGDR, load the
810 // destination register instead.
812 unsigned LoadOpcode = Op0IsGPR ? SystemZ::LG : SystemZ::LD;
813 unsigned Dest = MI->getOperand(0).getReg();
814 return BuildMI(*InsertPt->getParent(), InsertPt, MI->getDebugLoc(),
815 get(LoadOpcode), Dest)
816 .addFrameIndex(FrameIndex)
822 // Look for cases where the source of a simple store or the destination
823 // of a simple load is being spilled. Try to use MVC instead.
825 // Although MVC is in practice a fast choice in these cases, it is still
826 // logically a bytewise copy. This means that we cannot use it if the
827 // load or store is volatile. We also wouldn't be able to use MVC if
828 // the two memories partially overlap, but that case cannot occur here,
829 // because we know that one of the memories is a full frame index.
831 // For performance reasons, we also want to avoid using MVC if the addresses
832 // might be equal. We don't worry about that case here, because spill slot
833 // coloring happens later, and because we have special code to remove
834 // MVCs that turn out to be redundant.
835 if (OpNum == 0 && MI->hasOneMemOperand()) {
836 MachineMemOperand *MMO = *MI->memoperands_begin();
837 if (MMO->getSize() == Size && !MMO->isVolatile()) {
838 // Handle conversion of loads.
839 if (isSimpleBD12Move(MI, SystemZII::SimpleBDXLoad)) {
840 return BuildMI(*InsertPt->getParent(), InsertPt, MI->getDebugLoc(),
842 .addFrameIndex(FrameIndex)
845 .addOperand(MI->getOperand(1))
846 .addImm(MI->getOperand(2).getImm())
849 // Handle conversion of stores.
850 if (isSimpleBD12Move(MI, SystemZII::SimpleBDXStore)) {
851 return BuildMI(*InsertPt->getParent(), InsertPt, MI->getDebugLoc(),
853 .addOperand(MI->getOperand(1))
854 .addImm(MI->getOperand(2).getImm())
856 .addFrameIndex(FrameIndex)
863 // If the spilled operand is the final one, try to change <INSN>R
865 int MemOpcode = SystemZ::getMemOpcode(Opcode);
866 if (MemOpcode >= 0) {
867 unsigned NumOps = MI->getNumExplicitOperands();
868 if (OpNum == NumOps - 1) {
869 const MCInstrDesc &MemDesc = get(MemOpcode);
870 uint64_t AccessBytes = SystemZII::getAccessSize(MemDesc.TSFlags);
871 assert(AccessBytes != 0 && "Size of access should be known");
872 assert(AccessBytes <= Size && "Access outside the frame index");
873 uint64_t Offset = Size - AccessBytes;
874 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
875 MI->getDebugLoc(), get(MemOpcode));
876 for (unsigned I = 0; I < OpNum; ++I)
877 MIB.addOperand(MI->getOperand(I));
878 MIB.addFrameIndex(FrameIndex).addImm(Offset);
879 if (MemDesc.TSFlags & SystemZII::HasIndex)
888 MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
889 MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops,
890 MachineBasicBlock::iterator InsertPt, MachineInstr *LoadMI) const {
895 SystemZInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
896 switch (MI->getOpcode()) {
898 splitMove(MI, SystemZ::LG);
902 splitMove(MI, SystemZ::STG);
906 splitMove(MI, SystemZ::LD);
910 splitMove(MI, SystemZ::STD);
914 expandRXYPseudo(MI, SystemZ::LB, SystemZ::LBH);
918 expandRXYPseudo(MI, SystemZ::LH, SystemZ::LHH);
921 case SystemZ::LLCRMux:
922 expandZExtPseudo(MI, SystemZ::LLCR, 8);
925 case SystemZ::LLHRMux:
926 expandZExtPseudo(MI, SystemZ::LLHR, 16);
929 case SystemZ::LLCMux:
930 expandRXYPseudo(MI, SystemZ::LLC, SystemZ::LLCH);
933 case SystemZ::LLHMux:
934 expandRXYPseudo(MI, SystemZ::LLH, SystemZ::LLHH);
938 expandRXYPseudo(MI, SystemZ::L, SystemZ::LFH);
941 case SystemZ::STCMux:
942 expandRXYPseudo(MI, SystemZ::STC, SystemZ::STCH);
945 case SystemZ::STHMux:
946 expandRXYPseudo(MI, SystemZ::STH, SystemZ::STHH);
950 expandRXYPseudo(MI, SystemZ::ST, SystemZ::STFH);
953 case SystemZ::LHIMux:
954 expandRIPseudo(MI, SystemZ::LHI, SystemZ::IIHF, true);
957 case SystemZ::IIFMux:
958 expandRIPseudo(MI, SystemZ::IILF, SystemZ::IIHF, false);
961 case SystemZ::IILMux:
962 expandRIPseudo(MI, SystemZ::IILL, SystemZ::IIHL, false);
965 case SystemZ::IIHMux:
966 expandRIPseudo(MI, SystemZ::IILH, SystemZ::IIHH, false);
969 case SystemZ::NIFMux:
970 expandRIPseudo(MI, SystemZ::NILF, SystemZ::NIHF, false);
973 case SystemZ::NILMux:
974 expandRIPseudo(MI, SystemZ::NILL, SystemZ::NIHL, false);
977 case SystemZ::NIHMux:
978 expandRIPseudo(MI, SystemZ::NILH, SystemZ::NIHH, false);
981 case SystemZ::OIFMux:
982 expandRIPseudo(MI, SystemZ::OILF, SystemZ::OIHF, false);
985 case SystemZ::OILMux:
986 expandRIPseudo(MI, SystemZ::OILL, SystemZ::OIHL, false);
989 case SystemZ::OIHMux:
990 expandRIPseudo(MI, SystemZ::OILH, SystemZ::OIHH, false);
993 case SystemZ::XIFMux:
994 expandRIPseudo(MI, SystemZ::XILF, SystemZ::XIHF, false);
997 case SystemZ::TMLMux:
998 expandRIPseudo(MI, SystemZ::TMLL, SystemZ::TMHL, false);
1001 case SystemZ::TMHMux:
1002 expandRIPseudo(MI, SystemZ::TMLH, SystemZ::TMHH, false);
1005 case SystemZ::AHIMux:
1006 expandRIPseudo(MI, SystemZ::AHI, SystemZ::AIH, false);
1009 case SystemZ::AHIMuxK:
1010 expandRIEPseudo(MI, SystemZ::AHI, SystemZ::AHIK, SystemZ::AIH);
1013 case SystemZ::AFIMux:
1014 expandRIPseudo(MI, SystemZ::AFI, SystemZ::AIH, false);
1017 case SystemZ::CFIMux:
1018 expandRIPseudo(MI, SystemZ::CFI, SystemZ::CIH, false);
1021 case SystemZ::CLFIMux:
1022 expandRIPseudo(MI, SystemZ::CLFI, SystemZ::CLIH, false);
1026 expandRXYPseudo(MI, SystemZ::C, SystemZ::CHF);
1029 case SystemZ::CLMux:
1030 expandRXYPseudo(MI, SystemZ::CL, SystemZ::CLHF);
1033 case SystemZ::RISBMux: {
1034 bool DestIsHigh = isHighReg(MI->getOperand(0).getReg());
1035 bool SrcIsHigh = isHighReg(MI->getOperand(2).getReg());
1036 if (SrcIsHigh == DestIsHigh)
1037 MI->setDesc(get(DestIsHigh ? SystemZ::RISBHH : SystemZ::RISBLL));
1039 MI->setDesc(get(DestIsHigh ? SystemZ::RISBHL : SystemZ::RISBLH));
1040 MI->getOperand(5).setImm(MI->getOperand(5).getImm() ^ 32);
1045 case SystemZ::ADJDYNALLOC:
1046 splitAdjDynAlloc(MI);
1054 uint64_t SystemZInstrInfo::getInstSizeInBytes(const MachineInstr *MI) const {
1055 if (MI->getOpcode() == TargetOpcode::INLINEASM) {
1056 const MachineFunction *MF = MI->getParent()->getParent();
1057 const char *AsmStr = MI->getOperand(0).getSymbolName();
1058 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1060 return MI->getDesc().getSize();
1064 SystemZInstrInfo::getBranchInfo(const MachineInstr *MI) const {
1065 switch (MI->getOpcode()) {
1069 return SystemZII::Branch(SystemZII::BranchNormal, SystemZ::CCMASK_ANY,
1070 SystemZ::CCMASK_ANY, &MI->getOperand(0));
1074 return SystemZII::Branch(SystemZII::BranchNormal,
1075 MI->getOperand(0).getImm(),
1076 MI->getOperand(1).getImm(), &MI->getOperand(2));
1079 return SystemZII::Branch(SystemZII::BranchCT, SystemZ::CCMASK_ICMP,
1080 SystemZ::CCMASK_CMP_NE, &MI->getOperand(2));
1082 case SystemZ::BRCTG:
1083 return SystemZII::Branch(SystemZII::BranchCTG, SystemZ::CCMASK_ICMP,
1084 SystemZ::CCMASK_CMP_NE, &MI->getOperand(2));
1088 return SystemZII::Branch(SystemZII::BranchC, SystemZ::CCMASK_ICMP,
1089 MI->getOperand(2).getImm(), &MI->getOperand(3));
1093 return SystemZII::Branch(SystemZII::BranchCL, SystemZ::CCMASK_ICMP,
1094 MI->getOperand(2).getImm(), &MI->getOperand(3));
1098 return SystemZII::Branch(SystemZII::BranchCG, SystemZ::CCMASK_ICMP,
1099 MI->getOperand(2).getImm(), &MI->getOperand(3));
1101 case SystemZ::CLGIJ:
1102 case SystemZ::CLGRJ:
1103 return SystemZII::Branch(SystemZII::BranchCLG, SystemZ::CCMASK_ICMP,
1104 MI->getOperand(2).getImm(), &MI->getOperand(3));
1107 llvm_unreachable("Unrecognized branch opcode");
1111 void SystemZInstrInfo::getLoadStoreOpcodes(const TargetRegisterClass *RC,
1112 unsigned &LoadOpcode,
1113 unsigned &StoreOpcode) const {
1114 if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) {
1115 LoadOpcode = SystemZ::L;
1116 StoreOpcode = SystemZ::ST;
1117 } else if (RC == &SystemZ::GRH32BitRegClass) {
1118 LoadOpcode = SystemZ::LFH;
1119 StoreOpcode = SystemZ::STFH;
1120 } else if (RC == &SystemZ::GRX32BitRegClass) {
1121 LoadOpcode = SystemZ::LMux;
1122 StoreOpcode = SystemZ::STMux;
1123 } else if (RC == &SystemZ::GR64BitRegClass ||
1124 RC == &SystemZ::ADDR64BitRegClass) {
1125 LoadOpcode = SystemZ::LG;
1126 StoreOpcode = SystemZ::STG;
1127 } else if (RC == &SystemZ::GR128BitRegClass ||
1128 RC == &SystemZ::ADDR128BitRegClass) {
1129 LoadOpcode = SystemZ::L128;
1130 StoreOpcode = SystemZ::ST128;
1131 } else if (RC == &SystemZ::FP32BitRegClass) {
1132 LoadOpcode = SystemZ::LE;
1133 StoreOpcode = SystemZ::STE;
1134 } else if (RC == &SystemZ::FP64BitRegClass) {
1135 LoadOpcode = SystemZ::LD;
1136 StoreOpcode = SystemZ::STD;
1137 } else if (RC == &SystemZ::FP128BitRegClass) {
1138 LoadOpcode = SystemZ::LX;
1139 StoreOpcode = SystemZ::STX;
1140 } else if (RC == &SystemZ::VR32BitRegClass) {
1141 LoadOpcode = SystemZ::VL32;
1142 StoreOpcode = SystemZ::VST32;
1143 } else if (RC == &SystemZ::VR64BitRegClass) {
1144 LoadOpcode = SystemZ::VL64;
1145 StoreOpcode = SystemZ::VST64;
1146 } else if (RC == &SystemZ::VF128BitRegClass ||
1147 RC == &SystemZ::VR128BitRegClass) {
1148 LoadOpcode = SystemZ::VL;
1149 StoreOpcode = SystemZ::VST;
1151 llvm_unreachable("Unsupported regclass to load or store");
1154 unsigned SystemZInstrInfo::getOpcodeForOffset(unsigned Opcode,
1155 int64_t Offset) const {
1156 const MCInstrDesc &MCID = get(Opcode);
1157 int64_t Offset2 = (MCID.TSFlags & SystemZII::Is128Bit ? Offset + 8 : Offset);
1158 if (isUInt<12>(Offset) && isUInt<12>(Offset2)) {
1159 // Get the instruction to use for unsigned 12-bit displacements.
1160 int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
1161 if (Disp12Opcode >= 0)
1162 return Disp12Opcode;
1164 // All address-related instructions can use unsigned 12-bit
1168 if (isInt<20>(Offset) && isInt<20>(Offset2)) {
1169 // Get the instruction to use for signed 20-bit displacements.
1170 int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
1171 if (Disp20Opcode >= 0)
1172 return Disp20Opcode;
1174 // Check whether Opcode allows signed 20-bit displacements.
1175 if (MCID.TSFlags & SystemZII::Has20BitOffset)
1181 unsigned SystemZInstrInfo::getLoadAndTest(unsigned Opcode) const {
1183 case SystemZ::L: return SystemZ::LT;
1184 case SystemZ::LY: return SystemZ::LT;
1185 case SystemZ::LG: return SystemZ::LTG;
1186 case SystemZ::LGF: return SystemZ::LTGF;
1187 case SystemZ::LR: return SystemZ::LTR;
1188 case SystemZ::LGFR: return SystemZ::LTGFR;
1189 case SystemZ::LGR: return SystemZ::LTGR;
1190 case SystemZ::LER: return SystemZ::LTEBR;
1191 case SystemZ::LDR: return SystemZ::LTDBR;
1192 case SystemZ::LXR: return SystemZ::LTXBR;
1193 case SystemZ::LCDFR: return SystemZ::LCDBR;
1194 case SystemZ::LPDFR: return SystemZ::LPDBR;
1195 case SystemZ::LNDFR: return SystemZ::LNDBR;
1196 case SystemZ::LCDFR_32: return SystemZ::LCEBR;
1197 case SystemZ::LPDFR_32: return SystemZ::LPEBR;
1198 case SystemZ::LNDFR_32: return SystemZ::LNEBR;
1199 // On zEC12 we prefer to use RISBGN. But if there is a chance to
1200 // actually use the condition code, we may turn it back into RISGB.
1201 // Note that RISBG is not really a "load-and-test" instruction,
1202 // but sets the same condition code values, so is OK to use here.
1203 case SystemZ::RISBGN: return SystemZ::RISBG;
1208 // Return true if Mask matches the regexp 0*1+0*, given that zero masks
1209 // have already been filtered out. Store the first set bit in LSB and
1210 // the number of set bits in Length if so.
1211 static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length) {
1212 unsigned First = findFirstSet(Mask);
1213 uint64_t Top = (Mask >> First) + 1;
1214 if ((Top & -Top) == Top) {
1216 Length = findFirstSet(Top);
1222 bool SystemZInstrInfo::isRxSBGMask(uint64_t Mask, unsigned BitSize,
1223 unsigned &Start, unsigned &End) const {
1224 // Reject trivial all-zero masks.
1225 Mask &= allOnes(BitSize);
1229 // Handle the 1+0+ or 0+1+0* cases. Start then specifies the index of
1230 // the msb and End specifies the index of the lsb.
1231 unsigned LSB, Length;
1232 if (isStringOfOnes(Mask, LSB, Length)) {
1233 Start = 63 - (LSB + Length - 1);
1238 // Handle the wrap-around 1+0+1+ cases. Start then specifies the msb
1239 // of the low 1s and End specifies the lsb of the high 1s.
1240 if (isStringOfOnes(Mask ^ allOnes(BitSize), LSB, Length)) {
1241 assert(LSB > 0 && "Bottom bit must be set");
1242 assert(LSB + Length < BitSize && "Top bit must be set");
1243 Start = 63 - (LSB - 1);
1244 End = 63 - (LSB + Length);
1251 unsigned SystemZInstrInfo::getCompareAndBranch(unsigned Opcode,
1252 const MachineInstr *MI) const {
1255 return SystemZ::CRJ;
1257 return SystemZ::CGRJ;
1259 return MI && isInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CIJ : 0;
1261 return MI && isInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CGIJ : 0;
1263 return SystemZ::CLRJ;
1265 return SystemZ::CLGRJ;
1267 return MI && isUInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CLIJ : 0;
1268 case SystemZ::CLGFI:
1269 return MI && isUInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CLGIJ : 0;
1275 void SystemZInstrInfo::loadImmediate(MachineBasicBlock &MBB,
1276 MachineBasicBlock::iterator MBBI,
1277 unsigned Reg, uint64_t Value) const {
1278 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1280 if (isInt<16>(Value))
1281 Opcode = SystemZ::LGHI;
1282 else if (SystemZ::isImmLL(Value))
1283 Opcode = SystemZ::LLILL;
1284 else if (SystemZ::isImmLH(Value)) {
1285 Opcode = SystemZ::LLILH;
1288 assert(isInt<32>(Value) && "Huge values not handled yet");
1289 Opcode = SystemZ::LGFI;
1291 BuildMI(MBB, MBBI, DL, get(Opcode), Reg).addImm(Value);