1 //===-- SystemZInstrInfo.cpp - SystemZ instruction information ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SystemZ implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "SystemZInstrInfo.h"
15 #include "SystemZInstrBuilder.h"
16 #include "SystemZTargetMachine.h"
17 #include "llvm/CodeGen/LiveVariables.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #define GET_INSTRINFO_CTOR_DTOR
23 #define GET_INSTRMAP_INFO
24 #include "SystemZGenInstrInfo.inc"
26 // Return a mask with Count low bits set.
27 static uint64_t allOnes(unsigned int Count) {
28 return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1;
31 // Reg should be a 32-bit GPR. Return true if it is a high register rather
32 // than a low register.
33 static bool isHighReg(unsigned int Reg) {
34 if (SystemZ::GRH32BitRegClass.contains(Reg))
36 assert(SystemZ::GR32BitRegClass.contains(Reg) && "Invalid GRX32");
40 // Pin the vtable to this file.
41 void SystemZInstrInfo::anchor() {}
43 SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm)
44 : SystemZGenInstrInfo(SystemZ::ADJCALLSTACKDOWN, SystemZ::ADJCALLSTACKUP),
48 // MI is a 128-bit load or store. Split it into two 64-bit loads or stores,
49 // each having the opcode given by NewOpcode.
50 void SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI,
51 unsigned NewOpcode) const {
52 MachineBasicBlock *MBB = MI->getParent();
53 MachineFunction &MF = *MBB->getParent();
55 // Get two load or store instructions. Use the original instruction for one
56 // of them (arbitrarily the second here) and create a clone for the other.
57 MachineInstr *EarlierMI = MF.CloneMachineInstr(MI);
58 MBB->insert(MI, EarlierMI);
60 // Set up the two 64-bit registers.
61 MachineOperand &HighRegOp = EarlierMI->getOperand(0);
62 MachineOperand &LowRegOp = MI->getOperand(0);
63 HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64));
64 LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64));
66 // The address in the first (high) instruction is already correct.
67 // Adjust the offset in the second (low) instruction.
68 MachineOperand &HighOffsetOp = EarlierMI->getOperand(2);
69 MachineOperand &LowOffsetOp = MI->getOperand(2);
70 LowOffsetOp.setImm(LowOffsetOp.getImm() + 8);
73 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm());
74 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm());
75 assert(HighOpcode && LowOpcode && "Both offsets should be in range");
77 EarlierMI->setDesc(get(HighOpcode));
78 MI->setDesc(get(LowOpcode));
81 // Split ADJDYNALLOC instruction MI.
82 void SystemZInstrInfo::splitAdjDynAlloc(MachineBasicBlock::iterator MI) const {
83 MachineBasicBlock *MBB = MI->getParent();
84 MachineFunction &MF = *MBB->getParent();
85 MachineFrameInfo *MFFrame = MF.getFrameInfo();
86 MachineOperand &OffsetMO = MI->getOperand(2);
88 uint64_t Offset = (MFFrame->getMaxCallFrameSize() +
89 SystemZMC::CallFrameSize +
91 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset);
92 assert(NewOpcode && "No support for huge argument lists yet");
93 MI->setDesc(get(NewOpcode));
94 OffsetMO.setImm(Offset);
97 // MI is an RI-style pseudo instruction. Replace it with LowOpcode
98 // if the first operand is a low GR32 and HighOpcode if the first operand
99 // is a high GR32. ConvertHigh is true if LowOpcode takes a signed operand
100 // and HighOpcode takes an unsigned 32-bit operand. In those cases,
101 // MI has the same kind of operand as LowOpcode, so needs to be converted
102 // if HighOpcode is used.
103 void SystemZInstrInfo::expandRIPseudo(MachineInstr *MI, unsigned LowOpcode,
105 bool ConvertHigh) const {
106 unsigned Reg = MI->getOperand(0).getReg();
107 bool IsHigh = isHighReg(Reg);
108 MI->setDesc(get(IsHigh ? HighOpcode : LowOpcode));
109 if (IsHigh && ConvertHigh)
110 MI->getOperand(1).setImm(uint32_t(MI->getOperand(1).getImm()));
113 // MI is a three-operand RIE-style pseudo instruction. Replace it with
114 // LowOpcode3 if the registers are both low GR32s, otherwise use a move
115 // followed by HighOpcode or LowOpcode, depending on whether the target
116 // is a high or low GR32.
117 void SystemZInstrInfo::expandRIEPseudo(MachineInstr *MI, unsigned LowOpcode,
119 unsigned HighOpcode) const {
120 unsigned DestReg = MI->getOperand(0).getReg();
121 unsigned SrcReg = MI->getOperand(1).getReg();
122 bool DestIsHigh = isHighReg(DestReg);
123 bool SrcIsHigh = isHighReg(SrcReg);
124 if (!DestIsHigh && !SrcIsHigh)
125 MI->setDesc(get(LowOpcodeK));
127 emitGRX32Move(*MI->getParent(), MI, MI->getDebugLoc(),
128 DestReg, SrcReg, SystemZ::LR, 32,
129 MI->getOperand(1).isKill());
130 MI->setDesc(get(DestIsHigh ? HighOpcode : LowOpcode));
131 MI->getOperand(1).setReg(DestReg);
135 // MI is an RXY-style pseudo instruction. Replace it with LowOpcode
136 // if the first operand is a low GR32 and HighOpcode if the first operand
138 void SystemZInstrInfo::expandRXYPseudo(MachineInstr *MI, unsigned LowOpcode,
139 unsigned HighOpcode) const {
140 unsigned Reg = MI->getOperand(0).getReg();
141 unsigned Opcode = getOpcodeForOffset(isHighReg(Reg) ? HighOpcode : LowOpcode,
142 MI->getOperand(2).getImm());
143 MI->setDesc(get(Opcode));
146 // MI is an RR-style pseudo instruction that zero-extends the low Size bits
147 // of one GRX32 into another. Replace it with LowOpcode if both operands
148 // are low registers, otherwise use RISB[LH]G.
149 void SystemZInstrInfo::expandZExtPseudo(MachineInstr *MI, unsigned LowOpcode,
150 unsigned Size) const {
151 emitGRX32Move(*MI->getParent(), MI, MI->getDebugLoc(),
152 MI->getOperand(0).getReg(), MI->getOperand(1).getReg(),
153 LowOpcode, Size, MI->getOperand(1).isKill());
154 MI->eraseFromParent();
157 // Emit a zero-extending move from 32-bit GPR SrcReg to 32-bit GPR
158 // DestReg before MBBI in MBB. Use LowLowOpcode when both DestReg and SrcReg
159 // are low registers, otherwise use RISB[LH]G. Size is the number of bits
160 // taken from the low end of SrcReg (8 for LLCR, 16 for LLHR and 32 for LR).
161 // KillSrc is true if this move is the last use of SrcReg.
162 void SystemZInstrInfo::emitGRX32Move(MachineBasicBlock &MBB,
163 MachineBasicBlock::iterator MBBI,
164 DebugLoc DL, unsigned DestReg,
165 unsigned SrcReg, unsigned LowLowOpcode,
166 unsigned Size, bool KillSrc) const {
168 bool DestIsHigh = isHighReg(DestReg);
169 bool SrcIsHigh = isHighReg(SrcReg);
170 if (DestIsHigh && SrcIsHigh)
171 Opcode = SystemZ::RISBHH;
172 else if (DestIsHigh && !SrcIsHigh)
173 Opcode = SystemZ::RISBHL;
174 else if (!DestIsHigh && SrcIsHigh)
175 Opcode = SystemZ::RISBLH;
177 BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg)
178 .addReg(SrcReg, getKillRegState(KillSrc));
181 unsigned Rotate = (DestIsHigh != SrcIsHigh ? 32 : 0);
182 BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
183 .addReg(DestReg, RegState::Undef)
184 .addReg(SrcReg, getKillRegState(KillSrc))
185 .addImm(32 - Size).addImm(128 + 31).addImm(Rotate);
188 // If MI is a simple load or store for a frame object, return the register
189 // it loads or stores and set FrameIndex to the index of the frame object.
190 // Return 0 otherwise.
192 // Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
193 static int isSimpleMove(const MachineInstr *MI, int &FrameIndex,
195 const MCInstrDesc &MCID = MI->getDesc();
196 if ((MCID.TSFlags & Flag) &&
197 MI->getOperand(1).isFI() &&
198 MI->getOperand(2).getImm() == 0 &&
199 MI->getOperand(3).getReg() == 0) {
200 FrameIndex = MI->getOperand(1).getIndex();
201 return MI->getOperand(0).getReg();
206 unsigned SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
207 int &FrameIndex) const {
208 return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXLoad);
211 unsigned SystemZInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
212 int &FrameIndex) const {
213 return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXStore);
216 bool SystemZInstrInfo::isStackSlotCopy(const MachineInstr *MI,
218 int &SrcFrameIndex) const {
219 // Check for MVC 0(Length,FI1),0(FI2)
220 const MachineFrameInfo *MFI = MI->getParent()->getParent()->getFrameInfo();
221 if (MI->getOpcode() != SystemZ::MVC ||
222 !MI->getOperand(0).isFI() ||
223 MI->getOperand(1).getImm() != 0 ||
224 !MI->getOperand(3).isFI() ||
225 MI->getOperand(4).getImm() != 0)
228 // Check that Length covers the full slots.
229 int64_t Length = MI->getOperand(2).getImm();
230 unsigned FI1 = MI->getOperand(0).getIndex();
231 unsigned FI2 = MI->getOperand(3).getIndex();
232 if (MFI->getObjectSize(FI1) != Length ||
233 MFI->getObjectSize(FI2) != Length)
236 DestFrameIndex = FI1;
241 bool SystemZInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
242 MachineBasicBlock *&TBB,
243 MachineBasicBlock *&FBB,
244 SmallVectorImpl<MachineOperand> &Cond,
245 bool AllowModify) const {
246 // Most of the code and comments here are boilerplate.
248 // Start from the bottom of the block and work up, examining the
249 // terminator instructions.
250 MachineBasicBlock::iterator I = MBB.end();
251 while (I != MBB.begin()) {
253 if (I->isDebugValue())
256 // Working from the bottom, when we see a non-terminator instruction, we're
258 if (!isUnpredicatedTerminator(I))
261 // A terminator that isn't a branch can't easily be handled by this
266 // Can't handle indirect branches.
267 SystemZII::Branch Branch(getBranchInfo(I));
268 if (!Branch.Target->isMBB())
271 // Punt on compound branches.
272 if (Branch.Type != SystemZII::BranchNormal)
275 if (Branch.CCMask == SystemZ::CCMASK_ANY) {
276 // Handle unconditional branches.
278 TBB = Branch.Target->getMBB();
282 // If the block has any instructions after a JMP, delete them.
283 while (std::next(I) != MBB.end())
284 std::next(I)->eraseFromParent();
289 // Delete the JMP if it's equivalent to a fall-through.
290 if (MBB.isLayoutSuccessor(Branch.Target->getMBB())) {
292 I->eraseFromParent();
297 // TBB is used to indicate the unconditinal destination.
298 TBB = Branch.Target->getMBB();
302 // Working from the bottom, handle the first conditional branch.
304 // FIXME: add X86-style branch swap
306 TBB = Branch.Target->getMBB();
307 Cond.push_back(MachineOperand::CreateImm(Branch.CCValid));
308 Cond.push_back(MachineOperand::CreateImm(Branch.CCMask));
312 // Handle subsequent conditional branches.
313 assert(Cond.size() == 2 && TBB && "Should have seen a conditional branch");
315 // Only handle the case where all conditional branches branch to the same
317 if (TBB != Branch.Target->getMBB())
320 // If the conditions are the same, we can leave them alone.
321 unsigned OldCCValid = Cond[0].getImm();
322 unsigned OldCCMask = Cond[1].getImm();
323 if (OldCCValid == Branch.CCValid && OldCCMask == Branch.CCMask)
326 // FIXME: Try combining conditions like X86 does. Should be easy on Z!
333 unsigned SystemZInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
334 // Most of the code and comments here are boilerplate.
335 MachineBasicBlock::iterator I = MBB.end();
338 while (I != MBB.begin()) {
340 if (I->isDebugValue())
344 if (!getBranchInfo(I).Target->isMBB())
346 // Remove the branch.
347 I->eraseFromParent();
355 bool SystemZInstrInfo::
356 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
357 assert(Cond.size() == 2 && "Invalid condition");
358 Cond[1].setImm(Cond[1].getImm() ^ Cond[0].getImm());
363 SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
364 MachineBasicBlock *FBB,
365 const SmallVectorImpl<MachineOperand> &Cond,
367 // In this function we output 32-bit branches, which should always
368 // have enough range. They can be shortened and relaxed by later code
369 // in the pipeline, if desired.
371 // Shouldn't be a fall through.
372 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
373 assert((Cond.size() == 2 || Cond.size() == 0) &&
374 "SystemZ branch conditions have one component!");
377 // Unconditional branch?
378 assert(!FBB && "Unconditional branch with multiple successors!");
379 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(TBB);
383 // Conditional branch.
385 unsigned CCValid = Cond[0].getImm();
386 unsigned CCMask = Cond[1].getImm();
387 BuildMI(&MBB, DL, get(SystemZ::BRC))
388 .addImm(CCValid).addImm(CCMask).addMBB(TBB);
392 // Two-way Conditional branch. Insert the second branch.
393 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(FBB);
399 bool SystemZInstrInfo::analyzeCompare(const MachineInstr *MI,
400 unsigned &SrcReg, unsigned &SrcReg2,
401 int &Mask, int &Value) const {
402 assert(MI->isCompare() && "Caller should have checked for a comparison");
404 if (MI->getNumExplicitOperands() == 2 &&
405 MI->getOperand(0).isReg() &&
406 MI->getOperand(1).isImm()) {
407 SrcReg = MI->getOperand(0).getReg();
409 Value = MI->getOperand(1).getImm();
417 // If Reg is a virtual register, return its definition, otherwise return null.
418 static MachineInstr *getDef(unsigned Reg,
419 const MachineRegisterInfo *MRI) {
420 if (TargetRegisterInfo::isPhysicalRegister(Reg))
422 return MRI->getUniqueVRegDef(Reg);
425 // Return true if MI is a shift of type Opcode by Imm bits.
426 static bool isShift(MachineInstr *MI, int Opcode, int64_t Imm) {
427 return (MI->getOpcode() == Opcode &&
428 !MI->getOperand(2).getReg() &&
429 MI->getOperand(3).getImm() == Imm);
432 // If the destination of MI has no uses, delete it as dead.
433 static void eraseIfDead(MachineInstr *MI, const MachineRegisterInfo *MRI) {
434 if (MRI->use_nodbg_empty(MI->getOperand(0).getReg()))
435 MI->eraseFromParent();
438 // Compare compares SrcReg against zero. Check whether SrcReg contains
439 // the result of an IPM sequence whose input CC survives until Compare,
440 // and whether Compare is therefore redundant. Delete it and return
442 static bool removeIPMBasedCompare(MachineInstr *Compare, unsigned SrcReg,
443 const MachineRegisterInfo *MRI,
444 const TargetRegisterInfo *TRI) {
445 MachineInstr *LGFR = nullptr;
446 MachineInstr *RLL = getDef(SrcReg, MRI);
447 if (RLL && RLL->getOpcode() == SystemZ::LGFR) {
449 RLL = getDef(LGFR->getOperand(1).getReg(), MRI);
451 if (!RLL || !isShift(RLL, SystemZ::RLL, 31))
454 MachineInstr *SRL = getDef(RLL->getOperand(1).getReg(), MRI);
455 if (!SRL || !isShift(SRL, SystemZ::SRL, SystemZ::IPM_CC))
458 MachineInstr *IPM = getDef(SRL->getOperand(1).getReg(), MRI);
459 if (!IPM || IPM->getOpcode() != SystemZ::IPM)
462 // Check that there are no assignments to CC between the IPM and Compare,
463 if (IPM->getParent() != Compare->getParent())
465 MachineBasicBlock::iterator MBBI = IPM, MBBE = Compare;
466 for (++MBBI; MBBI != MBBE; ++MBBI) {
467 MachineInstr *MI = MBBI;
468 if (MI->modifiesRegister(SystemZ::CC, TRI))
472 Compare->eraseFromParent();
474 eraseIfDead(LGFR, MRI);
475 eraseIfDead(RLL, MRI);
476 eraseIfDead(SRL, MRI);
477 eraseIfDead(IPM, MRI);
483 SystemZInstrInfo::optimizeCompareInstr(MachineInstr *Compare,
484 unsigned SrcReg, unsigned SrcReg2,
486 const MachineRegisterInfo *MRI) const {
487 assert(!SrcReg2 && "Only optimizing constant comparisons so far");
488 bool IsLogical = (Compare->getDesc().TSFlags & SystemZII::IsLogical) != 0;
491 removeIPMBasedCompare(Compare, SrcReg, MRI, TM.getRegisterInfo()))
496 // If Opcode is a move that has a conditional variant, return that variant,
497 // otherwise return 0.
498 static unsigned getConditionalMove(unsigned Opcode) {
500 case SystemZ::LR: return SystemZ::LOCR;
501 case SystemZ::LGR: return SystemZ::LOCGR;
506 bool SystemZInstrInfo::isPredicable(MachineInstr *MI) const {
507 unsigned Opcode = MI->getOpcode();
508 if (TM.getSubtargetImpl()->hasLoadStoreOnCond() &&
509 getConditionalMove(Opcode))
514 bool SystemZInstrInfo::
515 isProfitableToIfCvt(MachineBasicBlock &MBB,
516 unsigned NumCycles, unsigned ExtraPredCycles,
517 const BranchProbability &Probability) const {
518 // For now only convert single instructions.
519 return NumCycles == 1;
522 bool SystemZInstrInfo::
523 isProfitableToIfCvt(MachineBasicBlock &TMBB,
524 unsigned NumCyclesT, unsigned ExtraPredCyclesT,
525 MachineBasicBlock &FMBB,
526 unsigned NumCyclesF, unsigned ExtraPredCyclesF,
527 const BranchProbability &Probability) const {
528 // For now avoid converting mutually-exclusive cases.
532 bool SystemZInstrInfo::
533 PredicateInstruction(MachineInstr *MI,
534 const SmallVectorImpl<MachineOperand> &Pred) const {
535 assert(Pred.size() == 2 && "Invalid condition");
536 unsigned CCValid = Pred[0].getImm();
537 unsigned CCMask = Pred[1].getImm();
538 assert(CCMask > 0 && CCMask < 15 && "Invalid predicate");
539 unsigned Opcode = MI->getOpcode();
540 if (TM.getSubtargetImpl()->hasLoadStoreOnCond()) {
541 if (unsigned CondOpcode = getConditionalMove(Opcode)) {
542 MI->setDesc(get(CondOpcode));
543 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
544 .addImm(CCValid).addImm(CCMask)
545 .addReg(SystemZ::CC, RegState::Implicit);
553 SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
554 MachineBasicBlock::iterator MBBI, DebugLoc DL,
555 unsigned DestReg, unsigned SrcReg,
556 bool KillSrc) const {
557 // Split 128-bit GPR moves into two 64-bit moves. This handles ADDR128 too.
558 if (SystemZ::GR128BitRegClass.contains(DestReg, SrcReg)) {
559 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_h64),
560 RI.getSubReg(SrcReg, SystemZ::subreg_h64), KillSrc);
561 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_l64),
562 RI.getSubReg(SrcReg, SystemZ::subreg_l64), KillSrc);
566 if (SystemZ::GRX32BitRegClass.contains(DestReg, SrcReg)) {
567 emitGRX32Move(MBB, MBBI, DL, DestReg, SrcReg, SystemZ::LR, 32, KillSrc);
571 // Everything else needs only one instruction.
573 if (SystemZ::GR64BitRegClass.contains(DestReg, SrcReg))
574 Opcode = SystemZ::LGR;
575 else if (SystemZ::FP32BitRegClass.contains(DestReg, SrcReg))
576 Opcode = SystemZ::LER;
577 else if (SystemZ::FP64BitRegClass.contains(DestReg, SrcReg))
578 Opcode = SystemZ::LDR;
579 else if (SystemZ::FP128BitRegClass.contains(DestReg, SrcReg))
580 Opcode = SystemZ::LXR;
582 llvm_unreachable("Impossible reg-to-reg copy");
584 BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
585 .addReg(SrcReg, getKillRegState(KillSrc));
589 SystemZInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
590 MachineBasicBlock::iterator MBBI,
591 unsigned SrcReg, bool isKill,
593 const TargetRegisterClass *RC,
594 const TargetRegisterInfo *TRI) const {
595 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
597 // Callers may expect a single instruction, so keep 128-bit moves
598 // together for now and lower them after register allocation.
599 unsigned LoadOpcode, StoreOpcode;
600 getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
601 addFrameReference(BuildMI(MBB, MBBI, DL, get(StoreOpcode))
602 .addReg(SrcReg, getKillRegState(isKill)), FrameIdx);
606 SystemZInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
607 MachineBasicBlock::iterator MBBI,
608 unsigned DestReg, int FrameIdx,
609 const TargetRegisterClass *RC,
610 const TargetRegisterInfo *TRI) const {
611 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
613 // Callers may expect a single instruction, so keep 128-bit moves
614 // together for now and lower them after register allocation.
615 unsigned LoadOpcode, StoreOpcode;
616 getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
617 addFrameReference(BuildMI(MBB, MBBI, DL, get(LoadOpcode), DestReg),
621 // Return true if MI is a simple load or store with a 12-bit displacement
622 // and no index. Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
623 static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag) {
624 const MCInstrDesc &MCID = MI->getDesc();
625 return ((MCID.TSFlags & Flag) &&
626 isUInt<12>(MI->getOperand(2).getImm()) &&
627 MI->getOperand(3).getReg() == 0);
632 LogicOp() : RegSize(0), ImmLSB(0), ImmSize(0) {}
633 LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize)
634 : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}
636 operator bool() const { return RegSize; }
638 unsigned RegSize, ImmLSB, ImmSize;
640 } // end anonymous namespace
642 static LogicOp interpretAndImmediate(unsigned Opcode) {
644 case SystemZ::NILMux: return LogicOp(32, 0, 16);
645 case SystemZ::NIHMux: return LogicOp(32, 16, 16);
646 case SystemZ::NILL64: return LogicOp(64, 0, 16);
647 case SystemZ::NILH64: return LogicOp(64, 16, 16);
648 case SystemZ::NIHL64: return LogicOp(64, 32, 16);
649 case SystemZ::NIHH64: return LogicOp(64, 48, 16);
650 case SystemZ::NIFMux: return LogicOp(32, 0, 32);
651 case SystemZ::NILF64: return LogicOp(64, 0, 32);
652 case SystemZ::NIHF64: return LogicOp(64, 32, 32);
653 default: return LogicOp();
657 // Used to return from convertToThreeAddress after replacing two-address
658 // instruction OldMI with three-address instruction NewMI.
659 static MachineInstr *finishConvertToThreeAddress(MachineInstr *OldMI,
663 unsigned NumOps = OldMI->getNumOperands();
664 for (unsigned I = 1; I < NumOps; ++I) {
665 MachineOperand &Op = OldMI->getOperand(I);
666 if (Op.isReg() && Op.isKill())
667 LV->replaceKillInstruction(Op.getReg(), OldMI, NewMI);
674 SystemZInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
675 MachineBasicBlock::iterator &MBBI,
676 LiveVariables *LV) const {
677 MachineInstr *MI = MBBI;
678 MachineBasicBlock *MBB = MI->getParent();
679 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
681 unsigned Opcode = MI->getOpcode();
682 unsigned NumOps = MI->getNumOperands();
684 // Try to convert something like SLL into SLLK, if supported.
685 // We prefer to keep the two-operand form where possible both
686 // because it tends to be shorter and because some instructions
687 // have memory forms that can be used during spilling.
688 if (TM.getSubtargetImpl()->hasDistinctOps()) {
689 MachineOperand &Dest = MI->getOperand(0);
690 MachineOperand &Src = MI->getOperand(1);
691 unsigned DestReg = Dest.getReg();
692 unsigned SrcReg = Src.getReg();
693 // AHIMux is only really a three-operand instruction when both operands
694 // are low registers. Try to constrain both operands to be low if
696 if (Opcode == SystemZ::AHIMux &&
697 TargetRegisterInfo::isVirtualRegister(DestReg) &&
698 TargetRegisterInfo::isVirtualRegister(SrcReg) &&
699 MRI.getRegClass(DestReg)->contains(SystemZ::R1L) &&
700 MRI.getRegClass(SrcReg)->contains(SystemZ::R1L)) {
701 MRI.constrainRegClass(DestReg, &SystemZ::GR32BitRegClass);
702 MRI.constrainRegClass(SrcReg, &SystemZ::GR32BitRegClass);
704 int ThreeOperandOpcode = SystemZ::getThreeOperandOpcode(Opcode);
705 if (ThreeOperandOpcode >= 0) {
706 MachineInstrBuilder MIB =
707 BuildMI(*MBB, MBBI, MI->getDebugLoc(), get(ThreeOperandOpcode))
709 // Keep the kill state, but drop the tied flag.
710 MIB.addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg());
711 // Keep the remaining operands as-is.
712 for (unsigned I = 2; I < NumOps; ++I)
713 MIB.addOperand(MI->getOperand(I));
714 return finishConvertToThreeAddress(MI, MIB, LV);
718 // Try to convert an AND into an RISBG-type instruction.
719 if (LogicOp And = interpretAndImmediate(Opcode)) {
720 uint64_t Imm = MI->getOperand(2).getImm() << And.ImmLSB;
721 // AND IMMEDIATE leaves the other bits of the register unchanged.
722 Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB);
724 if (isRxSBGMask(Imm, And.RegSize, Start, End)) {
726 if (And.RegSize == 64)
727 NewOpcode = SystemZ::RISBG;
729 NewOpcode = SystemZ::RISBMux;
733 MachineOperand &Dest = MI->getOperand(0);
734 MachineOperand &Src = MI->getOperand(1);
735 MachineInstrBuilder MIB =
736 BuildMI(*MBB, MI, MI->getDebugLoc(), get(NewOpcode))
737 .addOperand(Dest).addReg(0)
738 .addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg())
739 .addImm(Start).addImm(End + 128).addImm(0);
740 return finishConvertToThreeAddress(MI, MIB, LV);
747 SystemZInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
749 const SmallVectorImpl<unsigned> &Ops,
750 int FrameIndex) const {
751 const MachineFrameInfo *MFI = MF.getFrameInfo();
752 unsigned Size = MFI->getObjectSize(FrameIndex);
753 unsigned Opcode = MI->getOpcode();
755 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
756 if ((Opcode == SystemZ::LA || Opcode == SystemZ::LAY) &&
757 isInt<8>(MI->getOperand(2).getImm()) &&
758 !MI->getOperand(3).getReg()) {
759 // LA(Y) %reg, CONST(%reg) -> AGSI %mem, CONST
760 return BuildMI(MF, MI->getDebugLoc(), get(SystemZ::AGSI))
761 .addFrameIndex(FrameIndex).addImm(0)
762 .addImm(MI->getOperand(2).getImm());
767 // All other cases require a single operand.
771 unsigned OpNum = Ops[0];
772 assert(Size == MF.getRegInfo()
773 .getRegClass(MI->getOperand(OpNum).getReg())->getSize() &&
774 "Invalid size combination");
776 if ((Opcode == SystemZ::AHI || Opcode == SystemZ::AGHI) &&
778 isInt<8>(MI->getOperand(2).getImm())) {
779 // A(G)HI %reg, CONST -> A(G)SI %mem, CONST
780 Opcode = (Opcode == SystemZ::AHI ? SystemZ::ASI : SystemZ::AGSI);
781 return BuildMI(MF, MI->getDebugLoc(), get(Opcode))
782 .addFrameIndex(FrameIndex).addImm(0)
783 .addImm(MI->getOperand(2).getImm());
786 if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {
787 bool Op0IsGPR = (Opcode == SystemZ::LGDR);
788 bool Op1IsGPR = (Opcode == SystemZ::LDGR);
789 // If we're spilling the destination of an LDGR or LGDR, store the
790 // source register instead.
792 unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD;
793 return BuildMI(MF, MI->getDebugLoc(), get(StoreOpcode))
794 .addOperand(MI->getOperand(1)).addFrameIndex(FrameIndex)
795 .addImm(0).addReg(0);
797 // If we're spilling the source of an LDGR or LGDR, load the
798 // destination register instead.
800 unsigned LoadOpcode = Op0IsGPR ? SystemZ::LG : SystemZ::LD;
801 unsigned Dest = MI->getOperand(0).getReg();
802 return BuildMI(MF, MI->getDebugLoc(), get(LoadOpcode), Dest)
803 .addFrameIndex(FrameIndex).addImm(0).addReg(0);
807 // Look for cases where the source of a simple store or the destination
808 // of a simple load is being spilled. Try to use MVC instead.
810 // Although MVC is in practice a fast choice in these cases, it is still
811 // logically a bytewise copy. This means that we cannot use it if the
812 // load or store is volatile. We also wouldn't be able to use MVC if
813 // the two memories partially overlap, but that case cannot occur here,
814 // because we know that one of the memories is a full frame index.
816 // For performance reasons, we also want to avoid using MVC if the addresses
817 // might be equal. We don't worry about that case here, because spill slot
818 // coloring happens later, and because we have special code to remove
819 // MVCs that turn out to be redundant.
820 if (OpNum == 0 && MI->hasOneMemOperand()) {
821 MachineMemOperand *MMO = *MI->memoperands_begin();
822 if (MMO->getSize() == Size && !MMO->isVolatile()) {
823 // Handle conversion of loads.
824 if (isSimpleBD12Move(MI, SystemZII::SimpleBDXLoad)) {
825 return BuildMI(MF, MI->getDebugLoc(), get(SystemZ::MVC))
826 .addFrameIndex(FrameIndex).addImm(0).addImm(Size)
827 .addOperand(MI->getOperand(1)).addImm(MI->getOperand(2).getImm())
830 // Handle conversion of stores.
831 if (isSimpleBD12Move(MI, SystemZII::SimpleBDXStore)) {
832 return BuildMI(MF, MI->getDebugLoc(), get(SystemZ::MVC))
833 .addOperand(MI->getOperand(1)).addImm(MI->getOperand(2).getImm())
834 .addImm(Size).addFrameIndex(FrameIndex).addImm(0)
840 // If the spilled operand is the final one, try to change <INSN>R
842 int MemOpcode = SystemZ::getMemOpcode(Opcode);
843 if (MemOpcode >= 0) {
844 unsigned NumOps = MI->getNumExplicitOperands();
845 if (OpNum == NumOps - 1) {
846 const MCInstrDesc &MemDesc = get(MemOpcode);
847 uint64_t AccessBytes = SystemZII::getAccessSize(MemDesc.TSFlags);
848 assert(AccessBytes != 0 && "Size of access should be known");
849 assert(AccessBytes <= Size && "Access outside the frame index");
850 uint64_t Offset = Size - AccessBytes;
851 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(MemOpcode));
852 for (unsigned I = 0; I < OpNum; ++I)
853 MIB.addOperand(MI->getOperand(I));
854 MIB.addFrameIndex(FrameIndex).addImm(Offset);
855 if (MemDesc.TSFlags & SystemZII::HasIndex)
865 SystemZInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr* MI,
866 const SmallVectorImpl<unsigned> &Ops,
867 MachineInstr* LoadMI) const {
872 SystemZInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
873 switch (MI->getOpcode()) {
875 splitMove(MI, SystemZ::LG);
879 splitMove(MI, SystemZ::STG);
883 splitMove(MI, SystemZ::LD);
887 splitMove(MI, SystemZ::STD);
891 expandRXYPseudo(MI, SystemZ::LB, SystemZ::LBH);
895 expandRXYPseudo(MI, SystemZ::LH, SystemZ::LHH);
898 case SystemZ::LLCRMux:
899 expandZExtPseudo(MI, SystemZ::LLCR, 8);
902 case SystemZ::LLHRMux:
903 expandZExtPseudo(MI, SystemZ::LLHR, 16);
906 case SystemZ::LLCMux:
907 expandRXYPseudo(MI, SystemZ::LLC, SystemZ::LLCH);
910 case SystemZ::LLHMux:
911 expandRXYPseudo(MI, SystemZ::LLH, SystemZ::LLHH);
915 expandRXYPseudo(MI, SystemZ::L, SystemZ::LFH);
918 case SystemZ::STCMux:
919 expandRXYPseudo(MI, SystemZ::STC, SystemZ::STCH);
922 case SystemZ::STHMux:
923 expandRXYPseudo(MI, SystemZ::STH, SystemZ::STHH);
927 expandRXYPseudo(MI, SystemZ::ST, SystemZ::STFH);
930 case SystemZ::LHIMux:
931 expandRIPseudo(MI, SystemZ::LHI, SystemZ::IIHF, true);
934 case SystemZ::IIFMux:
935 expandRIPseudo(MI, SystemZ::IILF, SystemZ::IIHF, false);
938 case SystemZ::IILMux:
939 expandRIPseudo(MI, SystemZ::IILL, SystemZ::IIHL, false);
942 case SystemZ::IIHMux:
943 expandRIPseudo(MI, SystemZ::IILH, SystemZ::IIHH, false);
946 case SystemZ::NIFMux:
947 expandRIPseudo(MI, SystemZ::NILF, SystemZ::NIHF, false);
950 case SystemZ::NILMux:
951 expandRIPseudo(MI, SystemZ::NILL, SystemZ::NIHL, false);
954 case SystemZ::NIHMux:
955 expandRIPseudo(MI, SystemZ::NILH, SystemZ::NIHH, false);
958 case SystemZ::OIFMux:
959 expandRIPseudo(MI, SystemZ::OILF, SystemZ::OIHF, false);
962 case SystemZ::OILMux:
963 expandRIPseudo(MI, SystemZ::OILL, SystemZ::OIHL, false);
966 case SystemZ::OIHMux:
967 expandRIPseudo(MI, SystemZ::OILH, SystemZ::OIHH, false);
970 case SystemZ::XIFMux:
971 expandRIPseudo(MI, SystemZ::XILF, SystemZ::XIHF, false);
974 case SystemZ::TMLMux:
975 expandRIPseudo(MI, SystemZ::TMLL, SystemZ::TMHL, false);
978 case SystemZ::TMHMux:
979 expandRIPseudo(MI, SystemZ::TMLH, SystemZ::TMHH, false);
982 case SystemZ::AHIMux:
983 expandRIPseudo(MI, SystemZ::AHI, SystemZ::AIH, false);
986 case SystemZ::AHIMuxK:
987 expandRIEPseudo(MI, SystemZ::AHI, SystemZ::AHIK, SystemZ::AIH);
990 case SystemZ::AFIMux:
991 expandRIPseudo(MI, SystemZ::AFI, SystemZ::AIH, false);
994 case SystemZ::CFIMux:
995 expandRIPseudo(MI, SystemZ::CFI, SystemZ::CIH, false);
998 case SystemZ::CLFIMux:
999 expandRIPseudo(MI, SystemZ::CLFI, SystemZ::CLIH, false);
1003 expandRXYPseudo(MI, SystemZ::C, SystemZ::CHF);
1006 case SystemZ::CLMux:
1007 expandRXYPseudo(MI, SystemZ::CL, SystemZ::CLHF);
1010 case SystemZ::RISBMux: {
1011 bool DestIsHigh = isHighReg(MI->getOperand(0).getReg());
1012 bool SrcIsHigh = isHighReg(MI->getOperand(2).getReg());
1013 if (SrcIsHigh == DestIsHigh)
1014 MI->setDesc(get(DestIsHigh ? SystemZ::RISBHH : SystemZ::RISBLL));
1016 MI->setDesc(get(DestIsHigh ? SystemZ::RISBHL : SystemZ::RISBLH));
1017 MI->getOperand(5).setImm(MI->getOperand(5).getImm() ^ 32);
1022 case SystemZ::ADJDYNALLOC:
1023 splitAdjDynAlloc(MI);
1031 uint64_t SystemZInstrInfo::getInstSizeInBytes(const MachineInstr *MI) const {
1032 if (MI->getOpcode() == TargetOpcode::INLINEASM) {
1033 const MachineFunction *MF = MI->getParent()->getParent();
1034 const char *AsmStr = MI->getOperand(0).getSymbolName();
1035 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1037 return MI->getDesc().getSize();
1041 SystemZInstrInfo::getBranchInfo(const MachineInstr *MI) const {
1042 switch (MI->getOpcode()) {
1046 return SystemZII::Branch(SystemZII::BranchNormal, SystemZ::CCMASK_ANY,
1047 SystemZ::CCMASK_ANY, &MI->getOperand(0));
1051 return SystemZII::Branch(SystemZII::BranchNormal,
1052 MI->getOperand(0).getImm(),
1053 MI->getOperand(1).getImm(), &MI->getOperand(2));
1056 return SystemZII::Branch(SystemZII::BranchCT, SystemZ::CCMASK_ICMP,
1057 SystemZ::CCMASK_CMP_NE, &MI->getOperand(2));
1059 case SystemZ::BRCTG:
1060 return SystemZII::Branch(SystemZII::BranchCTG, SystemZ::CCMASK_ICMP,
1061 SystemZ::CCMASK_CMP_NE, &MI->getOperand(2));
1065 return SystemZII::Branch(SystemZII::BranchC, SystemZ::CCMASK_ICMP,
1066 MI->getOperand(2).getImm(), &MI->getOperand(3));
1070 return SystemZII::Branch(SystemZII::BranchCL, SystemZ::CCMASK_ICMP,
1071 MI->getOperand(2).getImm(), &MI->getOperand(3));
1075 return SystemZII::Branch(SystemZII::BranchCG, SystemZ::CCMASK_ICMP,
1076 MI->getOperand(2).getImm(), &MI->getOperand(3));
1078 case SystemZ::CLGIJ:
1079 case SystemZ::CLGRJ:
1080 return SystemZII::Branch(SystemZII::BranchCLG, SystemZ::CCMASK_ICMP,
1081 MI->getOperand(2).getImm(), &MI->getOperand(3));
1084 llvm_unreachable("Unrecognized branch opcode");
1088 void SystemZInstrInfo::getLoadStoreOpcodes(const TargetRegisterClass *RC,
1089 unsigned &LoadOpcode,
1090 unsigned &StoreOpcode) const {
1091 if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) {
1092 LoadOpcode = SystemZ::L;
1093 StoreOpcode = SystemZ::ST;
1094 } else if (RC == &SystemZ::GRH32BitRegClass) {
1095 LoadOpcode = SystemZ::LFH;
1096 StoreOpcode = SystemZ::STFH;
1097 } else if (RC == &SystemZ::GRX32BitRegClass) {
1098 LoadOpcode = SystemZ::LMux;
1099 StoreOpcode = SystemZ::STMux;
1100 } else if (RC == &SystemZ::GR64BitRegClass ||
1101 RC == &SystemZ::ADDR64BitRegClass) {
1102 LoadOpcode = SystemZ::LG;
1103 StoreOpcode = SystemZ::STG;
1104 } else if (RC == &SystemZ::GR128BitRegClass ||
1105 RC == &SystemZ::ADDR128BitRegClass) {
1106 LoadOpcode = SystemZ::L128;
1107 StoreOpcode = SystemZ::ST128;
1108 } else if (RC == &SystemZ::FP32BitRegClass) {
1109 LoadOpcode = SystemZ::LE;
1110 StoreOpcode = SystemZ::STE;
1111 } else if (RC == &SystemZ::FP64BitRegClass) {
1112 LoadOpcode = SystemZ::LD;
1113 StoreOpcode = SystemZ::STD;
1114 } else if (RC == &SystemZ::FP128BitRegClass) {
1115 LoadOpcode = SystemZ::LX;
1116 StoreOpcode = SystemZ::STX;
1118 llvm_unreachable("Unsupported regclass to load or store");
1121 unsigned SystemZInstrInfo::getOpcodeForOffset(unsigned Opcode,
1122 int64_t Offset) const {
1123 const MCInstrDesc &MCID = get(Opcode);
1124 int64_t Offset2 = (MCID.TSFlags & SystemZII::Is128Bit ? Offset + 8 : Offset);
1125 if (isUInt<12>(Offset) && isUInt<12>(Offset2)) {
1126 // Get the instruction to use for unsigned 12-bit displacements.
1127 int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
1128 if (Disp12Opcode >= 0)
1129 return Disp12Opcode;
1131 // All address-related instructions can use unsigned 12-bit
1135 if (isInt<20>(Offset) && isInt<20>(Offset2)) {
1136 // Get the instruction to use for signed 20-bit displacements.
1137 int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
1138 if (Disp20Opcode >= 0)
1139 return Disp20Opcode;
1141 // Check whether Opcode allows signed 20-bit displacements.
1142 if (MCID.TSFlags & SystemZII::Has20BitOffset)
1148 unsigned SystemZInstrInfo::getLoadAndTest(unsigned Opcode) const {
1150 case SystemZ::L: return SystemZ::LT;
1151 case SystemZ::LY: return SystemZ::LT;
1152 case SystemZ::LG: return SystemZ::LTG;
1153 case SystemZ::LGF: return SystemZ::LTGF;
1154 case SystemZ::LR: return SystemZ::LTR;
1155 case SystemZ::LGFR: return SystemZ::LTGFR;
1156 case SystemZ::LGR: return SystemZ::LTGR;
1157 case SystemZ::LER: return SystemZ::LTEBR;
1158 case SystemZ::LDR: return SystemZ::LTDBR;
1159 case SystemZ::LXR: return SystemZ::LTXBR;
1164 // Return true if Mask matches the regexp 0*1+0*, given that zero masks
1165 // have already been filtered out. Store the first set bit in LSB and
1166 // the number of set bits in Length if so.
1167 static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length) {
1168 unsigned First = findFirstSet(Mask);
1169 uint64_t Top = (Mask >> First) + 1;
1170 if ((Top & -Top) == Top) {
1172 Length = findFirstSet(Top);
1178 bool SystemZInstrInfo::isRxSBGMask(uint64_t Mask, unsigned BitSize,
1179 unsigned &Start, unsigned &End) const {
1180 // Reject trivial all-zero masks.
1184 // Handle the 1+0+ or 0+1+0* cases. Start then specifies the index of
1185 // the msb and End specifies the index of the lsb.
1186 unsigned LSB, Length;
1187 if (isStringOfOnes(Mask, LSB, Length)) {
1188 Start = 63 - (LSB + Length - 1);
1193 // Handle the wrap-around 1+0+1+ cases. Start then specifies the msb
1194 // of the low 1s and End specifies the lsb of the high 1s.
1195 if (isStringOfOnes(Mask ^ allOnes(BitSize), LSB, Length)) {
1196 assert(LSB > 0 && "Bottom bit must be set");
1197 assert(LSB + Length < BitSize && "Top bit must be set");
1198 Start = 63 - (LSB - 1);
1199 End = 63 - (LSB + Length);
1206 unsigned SystemZInstrInfo::getCompareAndBranch(unsigned Opcode,
1207 const MachineInstr *MI) const {
1210 return SystemZ::CRJ;
1212 return SystemZ::CGRJ;
1214 return MI && isInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CIJ : 0;
1216 return MI && isInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CGIJ : 0;
1218 return SystemZ::CLRJ;
1220 return SystemZ::CLGRJ;
1222 return MI && isUInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CLIJ : 0;
1223 case SystemZ::CLGFI:
1224 return MI && isUInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CLGIJ : 0;
1230 void SystemZInstrInfo::loadImmediate(MachineBasicBlock &MBB,
1231 MachineBasicBlock::iterator MBBI,
1232 unsigned Reg, uint64_t Value) const {
1233 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1235 if (isInt<16>(Value))
1236 Opcode = SystemZ::LGHI;
1237 else if (SystemZ::isImmLL(Value))
1238 Opcode = SystemZ::LLILL;
1239 else if (SystemZ::isImmLH(Value)) {
1240 Opcode = SystemZ::LLILH;
1243 assert(isInt<32>(Value) && "Huge values not handled yet");
1244 Opcode = SystemZ::LGFI;
1246 BuildMI(MBB, MBBI, DL, get(Opcode), Reg).addImm(Value);