1 //===-- SystemZInstrInfo.cpp - SystemZ instruction information ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SystemZ implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "SystemZInstrInfo.h"
15 #include "SystemZTargetMachine.h"
16 #include "SystemZInstrBuilder.h"
17 #include "llvm/CodeGen/LiveVariables.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #define GET_INSTRINFO_CTOR
21 #define GET_INSTRMAP_INFO
22 #include "SystemZGenInstrInfo.inc"
26 // Return a mask with Count low bits set.
27 static uint64_t allOnes(unsigned int Count) {
28 return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1;
31 SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm)
32 : SystemZGenInstrInfo(SystemZ::ADJCALLSTACKDOWN, SystemZ::ADJCALLSTACKUP),
36 // MI is a 128-bit load or store. Split it into two 64-bit loads or stores,
37 // each having the opcode given by NewOpcode.
38 void SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI,
39 unsigned NewOpcode) const {
40 MachineBasicBlock *MBB = MI->getParent();
41 MachineFunction &MF = *MBB->getParent();
43 // Get two load or store instructions. Use the original instruction for one
44 // of them (arbitarily the second here) and create a clone for the other.
45 MachineInstr *EarlierMI = MF.CloneMachineInstr(MI);
46 MBB->insert(MI, EarlierMI);
48 // Set up the two 64-bit registers.
49 MachineOperand &HighRegOp = EarlierMI->getOperand(0);
50 MachineOperand &LowRegOp = MI->getOperand(0);
51 HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_high));
52 LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_low));
54 // The address in the first (high) instruction is already correct.
55 // Adjust the offset in the second (low) instruction.
56 MachineOperand &HighOffsetOp = EarlierMI->getOperand(2);
57 MachineOperand &LowOffsetOp = MI->getOperand(2);
58 LowOffsetOp.setImm(LowOffsetOp.getImm() + 8);
61 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm());
62 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm());
63 assert(HighOpcode && LowOpcode && "Both offsets should be in range");
65 EarlierMI->setDesc(get(HighOpcode));
66 MI->setDesc(get(LowOpcode));
69 // Split ADJDYNALLOC instruction MI.
70 void SystemZInstrInfo::splitAdjDynAlloc(MachineBasicBlock::iterator MI) const {
71 MachineBasicBlock *MBB = MI->getParent();
72 MachineFunction &MF = *MBB->getParent();
73 MachineFrameInfo *MFFrame = MF.getFrameInfo();
74 MachineOperand &OffsetMO = MI->getOperand(2);
76 uint64_t Offset = (MFFrame->getMaxCallFrameSize() +
77 SystemZMC::CallFrameSize +
79 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset);
80 assert(NewOpcode && "No support for huge argument lists yet");
81 MI->setDesc(get(NewOpcode));
82 OffsetMO.setImm(Offset);
85 // If MI is a simple load or store for a frame object, return the register
86 // it loads or stores and set FrameIndex to the index of the frame object.
87 // Return 0 otherwise.
89 // Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
90 static int isSimpleMove(const MachineInstr *MI, int &FrameIndex,
92 const MCInstrDesc &MCID = MI->getDesc();
93 if ((MCID.TSFlags & Flag) &&
94 MI->getOperand(1).isFI() &&
95 MI->getOperand(2).getImm() == 0 &&
96 MI->getOperand(3).getReg() == 0) {
97 FrameIndex = MI->getOperand(1).getIndex();
98 return MI->getOperand(0).getReg();
103 unsigned SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
104 int &FrameIndex) const {
105 return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXLoad);
108 unsigned SystemZInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
109 int &FrameIndex) const {
110 return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXStore);
113 bool SystemZInstrInfo::isStackSlotCopy(const MachineInstr *MI,
115 int &SrcFrameIndex) const {
116 // Check for MVC 0(Length,FI1),0(FI2)
117 const MachineFrameInfo *MFI = MI->getParent()->getParent()->getFrameInfo();
118 if (MI->getOpcode() != SystemZ::MVC ||
119 !MI->getOperand(0).isFI() ||
120 MI->getOperand(1).getImm() != 0 ||
121 !MI->getOperand(3).isFI() ||
122 MI->getOperand(4).getImm() != 0)
125 // Check that Length covers the full slots.
126 int64_t Length = MI->getOperand(2).getImm();
127 unsigned FI1 = MI->getOperand(0).getIndex();
128 unsigned FI2 = MI->getOperand(3).getIndex();
129 if (MFI->getObjectSize(FI1) != Length ||
130 MFI->getObjectSize(FI2) != Length)
133 DestFrameIndex = FI1;
138 bool SystemZInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
139 MachineBasicBlock *&TBB,
140 MachineBasicBlock *&FBB,
141 SmallVectorImpl<MachineOperand> &Cond,
142 bool AllowModify) const {
143 // Most of the code and comments here are boilerplate.
145 // Start from the bottom of the block and work up, examining the
146 // terminator instructions.
147 MachineBasicBlock::iterator I = MBB.end();
148 while (I != MBB.begin()) {
150 if (I->isDebugValue())
153 // Working from the bottom, when we see a non-terminator instruction, we're
155 if (!isUnpredicatedTerminator(I))
158 // A terminator that isn't a branch can't easily be handled by this
163 // Can't handle indirect branches.
164 SystemZII::Branch Branch(getBranchInfo(I));
165 if (!Branch.Target->isMBB())
168 // Punt on compound branches.
169 if (Branch.Type != SystemZII::BranchNormal)
172 if (Branch.CCMask == SystemZ::CCMASK_ANY) {
173 // Handle unconditional branches.
175 TBB = Branch.Target->getMBB();
179 // If the block has any instructions after a JMP, delete them.
180 while (llvm::next(I) != MBB.end())
181 llvm::next(I)->eraseFromParent();
186 // Delete the JMP if it's equivalent to a fall-through.
187 if (MBB.isLayoutSuccessor(Branch.Target->getMBB())) {
189 I->eraseFromParent();
194 // TBB is used to indicate the unconditinal destination.
195 TBB = Branch.Target->getMBB();
199 // Working from the bottom, handle the first conditional branch.
201 // FIXME: add X86-style branch swap
203 TBB = Branch.Target->getMBB();
204 Cond.push_back(MachineOperand::CreateImm(Branch.CCValid));
205 Cond.push_back(MachineOperand::CreateImm(Branch.CCMask));
209 // Handle subsequent conditional branches.
210 assert(Cond.size() == 2 && TBB && "Should have seen a conditional branch");
212 // Only handle the case where all conditional branches branch to the same
214 if (TBB != Branch.Target->getMBB())
217 // If the conditions are the same, we can leave them alone.
218 unsigned OldCCValid = Cond[0].getImm();
219 unsigned OldCCMask = Cond[1].getImm();
220 if (OldCCValid == Branch.CCValid && OldCCMask == Branch.CCMask)
223 // FIXME: Try combining conditions like X86 does. Should be easy on Z!
230 unsigned SystemZInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
231 // Most of the code and comments here are boilerplate.
232 MachineBasicBlock::iterator I = MBB.end();
235 while (I != MBB.begin()) {
237 if (I->isDebugValue())
241 if (!getBranchInfo(I).Target->isMBB())
243 // Remove the branch.
244 I->eraseFromParent();
252 bool SystemZInstrInfo::
253 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
254 assert(Cond.size() == 2 && "Invalid condition");
255 Cond[1].setImm(Cond[1].getImm() ^ Cond[0].getImm());
260 SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
261 MachineBasicBlock *FBB,
262 const SmallVectorImpl<MachineOperand> &Cond,
264 // In this function we output 32-bit branches, which should always
265 // have enough range. They can be shortened and relaxed by later code
266 // in the pipeline, if desired.
268 // Shouldn't be a fall through.
269 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
270 assert((Cond.size() == 2 || Cond.size() == 0) &&
271 "SystemZ branch conditions have one component!");
274 // Unconditional branch?
275 assert(!FBB && "Unconditional branch with multiple successors!");
276 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(TBB);
280 // Conditional branch.
282 unsigned CCValid = Cond[0].getImm();
283 unsigned CCMask = Cond[1].getImm();
284 BuildMI(&MBB, DL, get(SystemZ::BRC))
285 .addImm(CCValid).addImm(CCMask).addMBB(TBB);
289 // Two-way Conditional branch. Insert the second branch.
290 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(FBB);
296 // If Opcode is a move that has a conditional variant, return that variant,
297 // otherwise return 0.
298 static unsigned getConditionalMove(unsigned Opcode) {
300 case SystemZ::LR: return SystemZ::LOCR;
301 case SystemZ::LGR: return SystemZ::LOCGR;
306 bool SystemZInstrInfo::isPredicable(MachineInstr *MI) const {
307 unsigned Opcode = MI->getOpcode();
308 if (TM.getSubtargetImpl()->hasLoadStoreOnCond() &&
309 getConditionalMove(Opcode))
314 bool SystemZInstrInfo::
315 isProfitableToIfCvt(MachineBasicBlock &MBB,
316 unsigned NumCycles, unsigned ExtraPredCycles,
317 const BranchProbability &Probability) const {
318 // For now only convert single instructions.
319 return NumCycles == 1;
322 bool SystemZInstrInfo::
323 isProfitableToIfCvt(MachineBasicBlock &TMBB,
324 unsigned NumCyclesT, unsigned ExtraPredCyclesT,
325 MachineBasicBlock &FMBB,
326 unsigned NumCyclesF, unsigned ExtraPredCyclesF,
327 const BranchProbability &Probability) const {
328 // For now avoid converting mutually-exclusive cases.
332 bool SystemZInstrInfo::
333 PredicateInstruction(MachineInstr *MI,
334 const SmallVectorImpl<MachineOperand> &Pred) const {
335 assert(Pred.size() == 2 && "Invalid condition");
336 unsigned CCValid = Pred[0].getImm();
337 unsigned CCMask = Pred[1].getImm();
338 assert(CCMask > 0 && CCMask < 15 && "Invalid predicate");
339 unsigned Opcode = MI->getOpcode();
340 if (TM.getSubtargetImpl()->hasLoadStoreOnCond()) {
341 if (unsigned CondOpcode = getConditionalMove(Opcode)) {
342 MI->setDesc(get(CondOpcode));
343 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
344 .addImm(CCValid).addImm(CCMask)
345 .addReg(SystemZ::CC, RegState::Implicit);;
353 SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
354 MachineBasicBlock::iterator MBBI, DebugLoc DL,
355 unsigned DestReg, unsigned SrcReg,
356 bool KillSrc) const {
357 // Split 128-bit GPR moves into two 64-bit moves. This handles ADDR128 too.
358 if (SystemZ::GR128BitRegClass.contains(DestReg, SrcReg)) {
359 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_high),
360 RI.getSubReg(SrcReg, SystemZ::subreg_high), KillSrc);
361 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_low),
362 RI.getSubReg(SrcReg, SystemZ::subreg_low), KillSrc);
366 // Everything else needs only one instruction.
368 if (SystemZ::GR32BitRegClass.contains(DestReg, SrcReg))
369 Opcode = SystemZ::LR;
370 else if (SystemZ::GR64BitRegClass.contains(DestReg, SrcReg))
371 Opcode = SystemZ::LGR;
372 else if (SystemZ::FP32BitRegClass.contains(DestReg, SrcReg))
373 Opcode = SystemZ::LER;
374 else if (SystemZ::FP64BitRegClass.contains(DestReg, SrcReg))
375 Opcode = SystemZ::LDR;
376 else if (SystemZ::FP128BitRegClass.contains(DestReg, SrcReg))
377 Opcode = SystemZ::LXR;
379 llvm_unreachable("Impossible reg-to-reg copy");
381 BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
382 .addReg(SrcReg, getKillRegState(KillSrc));
386 SystemZInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
387 MachineBasicBlock::iterator MBBI,
388 unsigned SrcReg, bool isKill,
390 const TargetRegisterClass *RC,
391 const TargetRegisterInfo *TRI) const {
392 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
394 // Callers may expect a single instruction, so keep 128-bit moves
395 // together for now and lower them after register allocation.
396 unsigned LoadOpcode, StoreOpcode;
397 getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
398 addFrameReference(BuildMI(MBB, MBBI, DL, get(StoreOpcode))
399 .addReg(SrcReg, getKillRegState(isKill)), FrameIdx);
403 SystemZInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
404 MachineBasicBlock::iterator MBBI,
405 unsigned DestReg, int FrameIdx,
406 const TargetRegisterClass *RC,
407 const TargetRegisterInfo *TRI) const {
408 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
410 // Callers may expect a single instruction, so keep 128-bit moves
411 // together for now and lower them after register allocation.
412 unsigned LoadOpcode, StoreOpcode;
413 getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
414 addFrameReference(BuildMI(MBB, MBBI, DL, get(LoadOpcode), DestReg),
418 // Return true if MI is a simple load or store with a 12-bit displacement
419 // and no index. Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
420 static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag) {
421 const MCInstrDesc &MCID = MI->getDesc();
422 return ((MCID.TSFlags & Flag) &&
423 isUInt<12>(MI->getOperand(2).getImm()) &&
424 MI->getOperand(3).getReg() == 0);
429 LogicOp() : RegSize(0), ImmLSB(0), ImmSize(0) {}
430 LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize)
431 : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}
433 operator bool() const { return RegSize; }
435 unsigned RegSize, ImmLSB, ImmSize;
439 static LogicOp interpretAndImmediate(unsigned Opcode) {
441 case SystemZ::NILL32: return LogicOp(32, 0, 16);
442 case SystemZ::NILH32: return LogicOp(32, 16, 16);
443 case SystemZ::NILL: return LogicOp(64, 0, 16);
444 case SystemZ::NILH: return LogicOp(64, 16, 16);
445 case SystemZ::NIHL: return LogicOp(64, 32, 16);
446 case SystemZ::NIHH: return LogicOp(64, 48, 16);
447 case SystemZ::NILF32: return LogicOp(32, 0, 32);
448 case SystemZ::NILF: return LogicOp(64, 0, 32);
449 case SystemZ::NIHF: return LogicOp(64, 32, 32);
450 default: return LogicOp();
454 // Used to return from convertToThreeAddress after replacing two-address
455 // instruction OldMI with three-address instruction NewMI.
456 static MachineInstr *finishConvertToThreeAddress(MachineInstr *OldMI,
460 unsigned NumOps = OldMI->getNumOperands();
461 for (unsigned I = 1; I < NumOps; ++I) {
462 MachineOperand &Op = OldMI->getOperand(I);
463 if (Op.isReg() && Op.isKill())
464 LV->replaceKillInstruction(Op.getReg(), OldMI, NewMI);
471 SystemZInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
472 MachineBasicBlock::iterator &MBBI,
473 LiveVariables *LV) const {
474 MachineInstr *MI = MBBI;
475 MachineBasicBlock *MBB = MI->getParent();
477 unsigned Opcode = MI->getOpcode();
478 unsigned NumOps = MI->getNumOperands();
480 // Try to convert something like SLL into SLLK, if supported.
481 // We prefer to keep the two-operand form where possible both
482 // because it tends to be shorter and because some instructions
483 // have memory forms that can be used during spilling.
484 if (TM.getSubtargetImpl()->hasDistinctOps()) {
485 int ThreeOperandOpcode = SystemZ::getThreeOperandOpcode(Opcode);
486 if (ThreeOperandOpcode >= 0) {
487 MachineOperand &Dest = MI->getOperand(0);
488 MachineOperand &Src = MI->getOperand(1);
489 MachineInstrBuilder MIB =
490 BuildMI(*MBB, MBBI, MI->getDebugLoc(), get(ThreeOperandOpcode))
492 // Keep the kill state, but drop the tied flag.
493 MIB.addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg());
494 // Keep the remaining operands as-is.
495 for (unsigned I = 2; I < NumOps; ++I)
496 MIB.addOperand(MI->getOperand(I));
497 return finishConvertToThreeAddress(MI, MIB, LV);
501 // Try to convert an AND into an RISBG-type instruction.
502 if (LogicOp And = interpretAndImmediate(Opcode)) {
504 if (And.RegSize == 64)
505 NewOpcode = SystemZ::RISBG;
506 else if (TM.getSubtargetImpl()->hasHighWord())
507 NewOpcode = SystemZ::RISBLG32;
509 // We can't use RISBG for 32-bit operations because it clobbers the
510 // high word of the destination too.
513 uint64_t Imm = MI->getOperand(2).getImm() << And.ImmLSB;
514 // AND IMMEDIATE leaves the other bits of the register unchanged.
515 Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB);
517 if (isRxSBGMask(Imm, And.RegSize, Start, End)) {
518 if (NewOpcode == SystemZ::RISBLG32) {
522 MachineOperand &Dest = MI->getOperand(0);
523 MachineOperand &Src = MI->getOperand(1);
524 MachineInstrBuilder MIB =
525 BuildMI(*MBB, MI, MI->getDebugLoc(), get(NewOpcode))
526 .addOperand(Dest).addReg(0)
527 .addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg())
528 .addImm(Start).addImm(End + 128).addImm(0);
529 return finishConvertToThreeAddress(MI, MIB, LV);
537 SystemZInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
539 const SmallVectorImpl<unsigned> &Ops,
540 int FrameIndex) const {
541 const MachineFrameInfo *MFI = MF.getFrameInfo();
542 unsigned Size = MFI->getObjectSize(FrameIndex);
544 // Eary exit for cases we don't care about
548 unsigned OpNum = Ops[0];
549 assert(Size == MF.getRegInfo()
550 .getRegClass(MI->getOperand(OpNum).getReg())->getSize() &&
551 "Invalid size combination");
553 unsigned Opcode = MI->getOpcode();
554 if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {
555 bool Op0IsGPR = (Opcode == SystemZ::LGDR);
556 bool Op1IsGPR = (Opcode == SystemZ::LDGR);
557 // If we're spilling the destination of an LDGR or LGDR, store the
558 // source register instead.
560 unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD;
561 return BuildMI(MF, MI->getDebugLoc(), get(StoreOpcode))
562 .addOperand(MI->getOperand(1)).addFrameIndex(FrameIndex)
563 .addImm(0).addReg(0);
565 // If we're spilling the source of an LDGR or LGDR, load the
566 // destination register instead.
568 unsigned LoadOpcode = Op0IsGPR ? SystemZ::LG : SystemZ::LD;
569 unsigned Dest = MI->getOperand(0).getReg();
570 return BuildMI(MF, MI->getDebugLoc(), get(LoadOpcode), Dest)
571 .addFrameIndex(FrameIndex).addImm(0).addReg(0);
575 // Look for cases where the source of a simple store or the destination
576 // of a simple load is being spilled. Try to use MVC instead.
578 // Although MVC is in practice a fast choice in these cases, it is still
579 // logically a bytewise copy. This means that we cannot use it if the
580 // load or store is volatile. It also means that the transformation is
581 // not valid in cases where the two memories partially overlap; however,
582 // that is not a problem here, because we know that one of the memories
583 // is a full frame index.
584 if (OpNum == 0 && MI->hasOneMemOperand()) {
585 MachineMemOperand *MMO = *MI->memoperands_begin();
586 if (MMO->getSize() == Size && !MMO->isVolatile()) {
587 // Handle conversion of loads.
588 if (isSimpleBD12Move(MI, SystemZII::SimpleBDXLoad)) {
589 return BuildMI(MF, MI->getDebugLoc(), get(SystemZ::MVC))
590 .addFrameIndex(FrameIndex).addImm(0).addImm(Size)
591 .addOperand(MI->getOperand(1)).addImm(MI->getOperand(2).getImm())
594 // Handle conversion of stores.
595 if (isSimpleBD12Move(MI, SystemZII::SimpleBDXStore)) {
596 return BuildMI(MF, MI->getDebugLoc(), get(SystemZ::MVC))
597 .addOperand(MI->getOperand(1)).addImm(MI->getOperand(2).getImm())
598 .addImm(Size).addFrameIndex(FrameIndex).addImm(0)
604 // If the spilled operand is the final one, try to change <INSN>R
606 int MemOpcode = SystemZ::getMemOpcode(Opcode);
607 if (MemOpcode >= 0) {
608 unsigned NumOps = MI->getNumExplicitOperands();
609 if (OpNum == NumOps - 1) {
610 const MCInstrDesc &MemDesc = get(MemOpcode);
611 uint64_t AccessBytes = SystemZII::getAccessSize(MemDesc.TSFlags);
612 assert(AccessBytes != 0 && "Size of access should be known");
613 assert(AccessBytes <= Size && "Access outside the frame index");
614 uint64_t Offset = Size - AccessBytes;
615 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(MemOpcode));
616 for (unsigned I = 0; I < OpNum; ++I)
617 MIB.addOperand(MI->getOperand(I));
618 MIB.addFrameIndex(FrameIndex).addImm(Offset);
619 if (MemDesc.TSFlags & SystemZII::HasIndex)
629 SystemZInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr* MI,
630 const SmallVectorImpl<unsigned> &Ops,
631 MachineInstr* LoadMI) const {
636 SystemZInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
637 switch (MI->getOpcode()) {
639 splitMove(MI, SystemZ::LG);
643 splitMove(MI, SystemZ::STG);
647 splitMove(MI, SystemZ::LD);
651 splitMove(MI, SystemZ::STD);
654 case SystemZ::ADJDYNALLOC:
655 splitAdjDynAlloc(MI);
663 uint64_t SystemZInstrInfo::getInstSizeInBytes(const MachineInstr *MI) const {
664 if (MI->getOpcode() == TargetOpcode::INLINEASM) {
665 const MachineFunction *MF = MI->getParent()->getParent();
666 const char *AsmStr = MI->getOperand(0).getSymbolName();
667 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
669 return MI->getDesc().getSize();
673 SystemZInstrInfo::getBranchInfo(const MachineInstr *MI) const {
674 switch (MI->getOpcode()) {
678 return SystemZII::Branch(SystemZII::BranchNormal, SystemZ::CCMASK_ANY,
679 SystemZ::CCMASK_ANY, &MI->getOperand(0));
683 return SystemZII::Branch(SystemZII::BranchNormal,
684 MI->getOperand(0).getImm(),
685 MI->getOperand(1).getImm(), &MI->getOperand(2));
689 return SystemZII::Branch(SystemZII::BranchC, SystemZ::CCMASK_ICMP,
690 MI->getOperand(2).getImm(), &MI->getOperand(3));
694 return SystemZII::Branch(SystemZII::BranchCG, SystemZ::CCMASK_ICMP,
695 MI->getOperand(2).getImm(), &MI->getOperand(3));
698 llvm_unreachable("Unrecognized branch opcode");
702 void SystemZInstrInfo::getLoadStoreOpcodes(const TargetRegisterClass *RC,
703 unsigned &LoadOpcode,
704 unsigned &StoreOpcode) const {
705 if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) {
706 LoadOpcode = SystemZ::L;
707 StoreOpcode = SystemZ::ST32;
708 } else if (RC == &SystemZ::GR64BitRegClass ||
709 RC == &SystemZ::ADDR64BitRegClass) {
710 LoadOpcode = SystemZ::LG;
711 StoreOpcode = SystemZ::STG;
712 } else if (RC == &SystemZ::GR128BitRegClass ||
713 RC == &SystemZ::ADDR128BitRegClass) {
714 LoadOpcode = SystemZ::L128;
715 StoreOpcode = SystemZ::ST128;
716 } else if (RC == &SystemZ::FP32BitRegClass) {
717 LoadOpcode = SystemZ::LE;
718 StoreOpcode = SystemZ::STE;
719 } else if (RC == &SystemZ::FP64BitRegClass) {
720 LoadOpcode = SystemZ::LD;
721 StoreOpcode = SystemZ::STD;
722 } else if (RC == &SystemZ::FP128BitRegClass) {
723 LoadOpcode = SystemZ::LX;
724 StoreOpcode = SystemZ::STX;
726 llvm_unreachable("Unsupported regclass to load or store");
729 unsigned SystemZInstrInfo::getOpcodeForOffset(unsigned Opcode,
730 int64_t Offset) const {
731 const MCInstrDesc &MCID = get(Opcode);
732 int64_t Offset2 = (MCID.TSFlags & SystemZII::Is128Bit ? Offset + 8 : Offset);
733 if (isUInt<12>(Offset) && isUInt<12>(Offset2)) {
734 // Get the instruction to use for unsigned 12-bit displacements.
735 int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
736 if (Disp12Opcode >= 0)
739 // All address-related instructions can use unsigned 12-bit
743 if (isInt<20>(Offset) && isInt<20>(Offset2)) {
744 // Get the instruction to use for signed 20-bit displacements.
745 int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
746 if (Disp20Opcode >= 0)
749 // Check whether Opcode allows signed 20-bit displacements.
750 if (MCID.TSFlags & SystemZII::Has20BitOffset)
756 // Return true if Mask matches the regexp 0*1+0*, given that zero masks
757 // have already been filtered out. Store the first set bit in LSB and
758 // the number of set bits in Length if so.
759 static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length) {
760 unsigned First = findFirstSet(Mask);
761 uint64_t Top = (Mask >> First) + 1;
762 if ((Top & -Top) == Top) {
764 Length = findFirstSet(Top);
770 bool SystemZInstrInfo::isRxSBGMask(uint64_t Mask, unsigned BitSize,
771 unsigned &Start, unsigned &End) const {
772 // Reject trivial all-zero masks.
776 // Handle the 1+0+ or 0+1+0* cases. Start then specifies the index of
777 // the msb and End specifies the index of the lsb.
778 unsigned LSB, Length;
779 if (isStringOfOnes(Mask, LSB, Length)) {
780 Start = 63 - (LSB + Length - 1);
785 // Handle the wrap-around 1+0+1+ cases. Start then specifies the msb
786 // of the low 1s and End specifies the lsb of the high 1s.
787 if (isStringOfOnes(Mask ^ allOnes(BitSize), LSB, Length)) {
788 assert(LSB > 0 && "Bottom bit must be set");
789 assert(LSB + Length < BitSize && "Top bit must be set");
790 Start = 63 - (LSB - 1);
791 End = 63 - (LSB + Length);
798 unsigned SystemZInstrInfo::getCompareAndBranch(unsigned Opcode,
799 const MachineInstr *MI) const {
804 return SystemZ::CGRJ;
806 return MI && isInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CIJ : 0;
808 return MI && isInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CGIJ : 0;
814 void SystemZInstrInfo::loadImmediate(MachineBasicBlock &MBB,
815 MachineBasicBlock::iterator MBBI,
816 unsigned Reg, uint64_t Value) const {
817 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
819 if (isInt<16>(Value))
820 Opcode = SystemZ::LGHI;
821 else if (SystemZ::isImmLL(Value))
822 Opcode = SystemZ::LLILL;
823 else if (SystemZ::isImmLH(Value)) {
824 Opcode = SystemZ::LLILH;
827 assert(isInt<32>(Value) && "Huge values not handled yet");
828 Opcode = SystemZ::LGFI;
830 BuildMI(MBB, MBBI, DL, get(Opcode), Reg).addImm(Value);