1 //===- SystemZInstrInfo.cpp - SystemZ Instruction Information --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SystemZ implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "SystemZInstrInfo.h"
16 #include "SystemZMachineFunctionInfo.h"
17 #include "SystemZTargetMachine.h"
18 #include "SystemZGenInstrInfo.inc"
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/PseudoSourceValue.h"
27 SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm)
28 : TargetInstrInfoImpl(SystemZInsts, array_lengthof(SystemZInsts)),
29 RI(tm, *this), TM(tm) {}
31 void SystemZInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
32 MachineBasicBlock::iterator MI,
33 unsigned SrcReg, bool isKill, int FrameIdx,
34 const TargetRegisterClass *RC) const {
35 assert(0 && "Cannot store this register to stack slot!");
38 void SystemZInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
39 MachineBasicBlock::iterator MI,
40 unsigned DestReg, int FrameIdx,
41 const TargetRegisterClass *RC) const{
42 assert(0 && "Cannot store this register to stack slot!");
45 bool SystemZInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
46 MachineBasicBlock::iterator I,
47 unsigned DestReg, unsigned SrcReg,
48 const TargetRegisterClass *DestRC,
49 const TargetRegisterClass *SrcRC) const {
50 DebugLoc DL = DebugLoc::getUnknownLoc();
51 if (I != MBB.end()) DL = I->getDebugLoc();
53 if (DestRC == SrcRC) {
55 if (DestRC == &SystemZ::GR64RegClass) {
56 Opc = SystemZ::MOV64rr;
61 BuildMI(MBB, I, DL, get(Opc), DestReg).addReg(SrcReg);
69 SystemZInstrInfo::isMoveInstr(const MachineInstr& MI,
70 unsigned &SrcReg, unsigned &DstReg,
71 unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
72 SrcSubIdx = DstSubIdx = 0; // No sub-registers yet.
74 switch (MI.getOpcode()) {
77 case SystemZ::MOV64rr:
78 assert(MI.getNumOperands() >= 2 &&
79 MI.getOperand(0).isReg() &&
80 MI.getOperand(1).isReg() &&
81 "invalid register-register move instruction");
82 SrcReg = MI.getOperand(1).getReg();
83 DstReg = MI.getOperand(0).getReg();
89 SystemZInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
90 MachineBasicBlock::iterator MI,
91 const std::vector<CalleeSavedInfo> &CSI) const {
96 SystemZInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
97 MachineBasicBlock::iterator MI,
98 const std::vector<CalleeSavedInfo> &CSI) const {
103 SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
104 MachineBasicBlock *FBB,
105 const SmallVectorImpl<MachineOperand> &Cond) const {
106 assert(0 && "Implement branches!");