1 //===-- SystemZInstrInfo.cpp - SystemZ instruction information ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SystemZ implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "SystemZInstrInfo.h"
15 #include "SystemZInstrBuilder.h"
16 #include "llvm/CodeGen/MachineRegisterInfo.h"
17 #include "llvm/Target/TargetMachine.h"
19 #define GET_INSTRINFO_CTOR
20 #define GET_INSTRMAP_INFO
21 #include "SystemZGenInstrInfo.inc"
25 SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm)
26 : SystemZGenInstrInfo(SystemZ::ADJCALLSTACKDOWN, SystemZ::ADJCALLSTACKUP),
30 // MI is a 128-bit load or store. Split it into two 64-bit loads or stores,
31 // each having the opcode given by NewOpcode.
32 void SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI,
33 unsigned NewOpcode) const {
34 MachineBasicBlock *MBB = MI->getParent();
35 MachineFunction &MF = *MBB->getParent();
37 // Get two load or store instructions. Use the original instruction for one
38 // of them (arbitarily the second here) and create a clone for the other.
39 MachineInstr *EarlierMI = MF.CloneMachineInstr(MI);
40 MBB->insert(MI, EarlierMI);
42 // Set up the two 64-bit registers.
43 MachineOperand &HighRegOp = EarlierMI->getOperand(0);
44 MachineOperand &LowRegOp = MI->getOperand(0);
45 HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_high));
46 LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_low));
48 // The address in the first (high) instruction is already correct.
49 // Adjust the offset in the second (low) instruction.
50 MachineOperand &HighOffsetOp = EarlierMI->getOperand(2);
51 MachineOperand &LowOffsetOp = MI->getOperand(2);
52 LowOffsetOp.setImm(LowOffsetOp.getImm() + 8);
55 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm());
56 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm());
57 assert(HighOpcode && LowOpcode && "Both offsets should be in range");
59 EarlierMI->setDesc(get(HighOpcode));
60 MI->setDesc(get(LowOpcode));
63 // Split ADJDYNALLOC instruction MI.
64 void SystemZInstrInfo::splitAdjDynAlloc(MachineBasicBlock::iterator MI) const {
65 MachineBasicBlock *MBB = MI->getParent();
66 MachineFunction &MF = *MBB->getParent();
67 MachineFrameInfo *MFFrame = MF.getFrameInfo();
68 MachineOperand &OffsetMO = MI->getOperand(2);
70 uint64_t Offset = (MFFrame->getMaxCallFrameSize() +
71 SystemZMC::CallFrameSize +
73 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset);
74 assert(NewOpcode && "No support for huge argument lists yet");
75 MI->setDesc(get(NewOpcode));
76 OffsetMO.setImm(Offset);
79 // If MI is a simple load or store for a frame object, return the register
80 // it loads or stores and set FrameIndex to the index of the frame object.
81 // Return 0 otherwise.
83 // Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
84 static int isSimpleMove(const MachineInstr *MI, int &FrameIndex,
86 const MCInstrDesc &MCID = MI->getDesc();
87 if ((MCID.TSFlags & Flag) &&
88 MI->getOperand(1).isFI() &&
89 MI->getOperand(2).getImm() == 0 &&
90 MI->getOperand(3).getReg() == 0) {
91 FrameIndex = MI->getOperand(1).getIndex();
92 return MI->getOperand(0).getReg();
97 unsigned SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
98 int &FrameIndex) const {
99 return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXLoad);
102 unsigned SystemZInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
103 int &FrameIndex) const {
104 return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXStore);
107 bool SystemZInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
108 MachineBasicBlock *&TBB,
109 MachineBasicBlock *&FBB,
110 SmallVectorImpl<MachineOperand> &Cond,
111 bool AllowModify) const {
112 // Most of the code and comments here are boilerplate.
114 // Start from the bottom of the block and work up, examining the
115 // terminator instructions.
116 MachineBasicBlock::iterator I = MBB.end();
117 while (I != MBB.begin()) {
119 if (I->isDebugValue())
122 // Working from the bottom, when we see a non-terminator instruction, we're
124 if (!isUnpredicatedTerminator(I))
127 // A terminator that isn't a branch can't easily be handled by this
132 // Can't handle indirect branches.
133 SystemZII::Branch Branch(getBranchInfo(I));
134 if (!Branch.Target->isMBB())
137 // Punt on compound branches.
138 if (Branch.Type != SystemZII::BranchNormal)
141 if (Branch.CCMask == SystemZ::CCMASK_ANY) {
142 // Handle unconditional branches.
144 TBB = Branch.Target->getMBB();
148 // If the block has any instructions after a JMP, delete them.
149 while (llvm::next(I) != MBB.end())
150 llvm::next(I)->eraseFromParent();
155 // Delete the JMP if it's equivalent to a fall-through.
156 if (MBB.isLayoutSuccessor(Branch.Target->getMBB())) {
158 I->eraseFromParent();
163 // TBB is used to indicate the unconditinal destination.
164 TBB = Branch.Target->getMBB();
168 // Working from the bottom, handle the first conditional branch.
170 // FIXME: add X86-style branch swap
172 TBB = Branch.Target->getMBB();
173 Cond.push_back(MachineOperand::CreateImm(Branch.CCMask));
177 // Handle subsequent conditional branches.
178 assert(Cond.size() == 1);
181 // Only handle the case where all conditional branches branch to the same
183 if (TBB != Branch.Target->getMBB())
186 // If the conditions are the same, we can leave them alone.
187 unsigned OldCond = Cond[0].getImm();
188 if (OldCond == Branch.CCMask)
191 // FIXME: Try combining conditions like X86 does. Should be easy on Z!
197 unsigned SystemZInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
198 // Most of the code and comments here are boilerplate.
199 MachineBasicBlock::iterator I = MBB.end();
202 while (I != MBB.begin()) {
204 if (I->isDebugValue())
208 if (!getBranchInfo(I).Target->isMBB())
210 // Remove the branch.
211 I->eraseFromParent();
220 SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
221 MachineBasicBlock *FBB,
222 const SmallVectorImpl<MachineOperand> &Cond,
224 // In this function we output 32-bit branches, which should always
225 // have enough range. They can be shortened and relaxed by later code
226 // in the pipeline, if desired.
228 // Shouldn't be a fall through.
229 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
230 assert((Cond.size() == 1 || Cond.size() == 0) &&
231 "SystemZ branch conditions have one component!");
234 // Unconditional branch?
235 assert(!FBB && "Unconditional branch with multiple successors!");
236 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(TBB);
240 // Conditional branch.
242 unsigned CC = Cond[0].getImm();
243 BuildMI(&MBB, DL, get(SystemZ::BRC)).addImm(CC).addMBB(TBB);
247 // Two-way Conditional branch. Insert the second branch.
248 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(FBB);
255 SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
256 MachineBasicBlock::iterator MBBI, DebugLoc DL,
257 unsigned DestReg, unsigned SrcReg,
258 bool KillSrc) const {
259 // Split 128-bit GPR moves into two 64-bit moves. This handles ADDR128 too.
260 if (SystemZ::GR128BitRegClass.contains(DestReg, SrcReg)) {
261 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_high),
262 RI.getSubReg(SrcReg, SystemZ::subreg_high), KillSrc);
263 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_low),
264 RI.getSubReg(SrcReg, SystemZ::subreg_low), KillSrc);
268 // Everything else needs only one instruction.
270 if (SystemZ::GR32BitRegClass.contains(DestReg, SrcReg))
271 Opcode = SystemZ::LR;
272 else if (SystemZ::GR64BitRegClass.contains(DestReg, SrcReg))
273 Opcode = SystemZ::LGR;
274 else if (SystemZ::FP32BitRegClass.contains(DestReg, SrcReg))
275 Opcode = SystemZ::LER;
276 else if (SystemZ::FP64BitRegClass.contains(DestReg, SrcReg))
277 Opcode = SystemZ::LDR;
278 else if (SystemZ::FP128BitRegClass.contains(DestReg, SrcReg))
279 Opcode = SystemZ::LXR;
281 llvm_unreachable("Impossible reg-to-reg copy");
283 BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
284 .addReg(SrcReg, getKillRegState(KillSrc));
288 SystemZInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
289 MachineBasicBlock::iterator MBBI,
290 unsigned SrcReg, bool isKill,
292 const TargetRegisterClass *RC,
293 const TargetRegisterInfo *TRI) const {
294 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
296 // Callers may expect a single instruction, so keep 128-bit moves
297 // together for now and lower them after register allocation.
298 unsigned LoadOpcode, StoreOpcode;
299 getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
300 addFrameReference(BuildMI(MBB, MBBI, DL, get(StoreOpcode))
301 .addReg(SrcReg, getKillRegState(isKill)), FrameIdx);
305 SystemZInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
306 MachineBasicBlock::iterator MBBI,
307 unsigned DestReg, int FrameIdx,
308 const TargetRegisterClass *RC,
309 const TargetRegisterInfo *TRI) const {
310 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
312 // Callers may expect a single instruction, so keep 128-bit moves
313 // together for now and lower them after register allocation.
314 unsigned LoadOpcode, StoreOpcode;
315 getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
316 addFrameReference(BuildMI(MBB, MBBI, DL, get(LoadOpcode), DestReg),
320 // Return true if MI is a simple load or store with a 12-bit displacement
321 // and no index. Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
322 static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag) {
323 const MCInstrDesc &MCID = MI->getDesc();
324 return ((MCID.TSFlags & Flag) &&
325 isUInt<12>(MI->getOperand(2).getImm()) &&
326 MI->getOperand(3).getReg() == 0);
329 // Return a MachineMemOperand for FrameIndex with flags MMOFlags.
330 // Offset is the byte offset from the start of FrameIndex.
331 static MachineMemOperand *getFrameMMO(MachineFunction &MF, int FrameIndex,
332 uint64_t &Offset, unsigned MMOFlags) {
333 const MachineFrameInfo *MFI = MF.getFrameInfo();
334 const Value *V = PseudoSourceValue::getFixedStack(FrameIndex);
335 return MF.getMachineMemOperand(MachinePointerInfo(V, Offset), MMOFlags,
336 MFI->getObjectSize(FrameIndex),
337 MFI->getObjectAlignment(FrameIndex));
341 SystemZInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
343 const SmallVectorImpl<unsigned> &Ops,
344 int FrameIndex) const {
345 const MachineFrameInfo *MFI = MF.getFrameInfo();
346 unsigned Size = MFI->getObjectSize(FrameIndex);
348 // Eary exit for cases we don't care about
352 unsigned OpNum = Ops[0];
353 unsigned Reg = MI->getOperand(OpNum).getReg();
354 assert(Size == MF.getRegInfo().getRegClass(Reg)->getSize() &&
355 "Invalid size combination");
357 // Look for cases where the source of a simple store or the destination
358 // of a simple load is being spilled. Try to use MVC instead.
360 // Although MVC is in practice a fast choice in these cases, it is still
361 // logically a bytewise copy. This means that we cannot use it if the
362 // load or store is volatile. It also means that the transformation is
363 // not valid in cases where the two memories partially overlap; however,
364 // that is not a problem here, because we know that one of the memories
365 // is a full frame index.
367 // For now we punt if the load or store is also to a frame index.
368 // In that case we might end up eliminating both of them to out-of-range
369 // offsets, which might then force the register scavenger to spill two
370 // other registers. The backend can only handle one such scavenger spill
372 if (OpNum == 0 && MI->hasOneMemOperand()) {
373 MachineMemOperand *MMO = *MI->memoperands_begin();
374 if (MMO->getSize() == Size && !MMO->isVolatile()) {
375 // Handle conversion of loads.
376 if (isSimpleBD12Move(MI, SystemZII::SimpleBDXLoad) &&
377 !MI->getOperand(1).isFI()) {
379 MachineMemOperand *FrameMMO = getFrameMMO(MF, FrameIndex, Offset,
380 MachineMemOperand::MOStore);
381 return BuildMI(MF, MI->getDebugLoc(), get(SystemZ::MVC))
382 .addFrameIndex(FrameIndex).addImm(Offset).addImm(Size)
383 .addOperand(MI->getOperand(1)).addImm(MI->getOperand(2).getImm())
384 .addMemOperand(FrameMMO).addMemOperand(MMO);
386 // Handle conversion of stores.
387 if (isSimpleBD12Move(MI, SystemZII::SimpleBDXStore) &&
388 !MI->getOperand(1).isFI()) {
390 MachineMemOperand *FrameMMO = getFrameMMO(MF, FrameIndex, Offset,
391 MachineMemOperand::MOLoad);
392 return BuildMI(MF, MI->getDebugLoc(), get(SystemZ::MVC))
393 .addOperand(MI->getOperand(1)).addImm(MI->getOperand(2).getImm())
394 .addImm(Size).addFrameIndex(FrameIndex).addImm(Offset)
395 .addMemOperand(MMO).addMemOperand(FrameMMO);
404 SystemZInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr* MI,
405 const SmallVectorImpl<unsigned> &Ops,
406 MachineInstr* LoadMI) const {
411 SystemZInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
412 switch (MI->getOpcode()) {
414 splitMove(MI, SystemZ::LG);
418 splitMove(MI, SystemZ::STG);
422 splitMove(MI, SystemZ::LD);
426 splitMove(MI, SystemZ::STD);
429 case SystemZ::ADJDYNALLOC:
430 splitAdjDynAlloc(MI);
438 bool SystemZInstrInfo::
439 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
440 assert(Cond.size() == 1 && "Invalid branch condition!");
441 Cond[0].setImm(Cond[0].getImm() ^ SystemZ::CCMASK_ANY);
445 uint64_t SystemZInstrInfo::getInstSizeInBytes(const MachineInstr *MI) const {
446 if (MI->getOpcode() == TargetOpcode::INLINEASM) {
447 const MachineFunction *MF = MI->getParent()->getParent();
448 const char *AsmStr = MI->getOperand(0).getSymbolName();
449 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
451 return MI->getDesc().getSize();
455 SystemZInstrInfo::getBranchInfo(const MachineInstr *MI) const {
456 switch (MI->getOpcode()) {
460 return SystemZII::Branch(SystemZII::BranchNormal, SystemZ::CCMASK_ANY,
465 return SystemZII::Branch(SystemZII::BranchNormal,
466 MI->getOperand(0).getImm(), &MI->getOperand(1));
470 return SystemZII::Branch(SystemZII::BranchC, MI->getOperand(2).getImm(),
475 return SystemZII::Branch(SystemZII::BranchCG, MI->getOperand(2).getImm(),
479 llvm_unreachable("Unrecognized branch opcode");
483 void SystemZInstrInfo::getLoadStoreOpcodes(const TargetRegisterClass *RC,
484 unsigned &LoadOpcode,
485 unsigned &StoreOpcode) const {
486 if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) {
487 LoadOpcode = SystemZ::L;
488 StoreOpcode = SystemZ::ST32;
489 } else if (RC == &SystemZ::GR64BitRegClass ||
490 RC == &SystemZ::ADDR64BitRegClass) {
491 LoadOpcode = SystemZ::LG;
492 StoreOpcode = SystemZ::STG;
493 } else if (RC == &SystemZ::GR128BitRegClass ||
494 RC == &SystemZ::ADDR128BitRegClass) {
495 LoadOpcode = SystemZ::L128;
496 StoreOpcode = SystemZ::ST128;
497 } else if (RC == &SystemZ::FP32BitRegClass) {
498 LoadOpcode = SystemZ::LE;
499 StoreOpcode = SystemZ::STE;
500 } else if (RC == &SystemZ::FP64BitRegClass) {
501 LoadOpcode = SystemZ::LD;
502 StoreOpcode = SystemZ::STD;
503 } else if (RC == &SystemZ::FP128BitRegClass) {
504 LoadOpcode = SystemZ::LX;
505 StoreOpcode = SystemZ::STX;
507 llvm_unreachable("Unsupported regclass to load or store");
510 unsigned SystemZInstrInfo::getOpcodeForOffset(unsigned Opcode,
511 int64_t Offset) const {
512 const MCInstrDesc &MCID = get(Opcode);
513 int64_t Offset2 = (MCID.TSFlags & SystemZII::Is128Bit ? Offset + 8 : Offset);
514 if (isUInt<12>(Offset) && isUInt<12>(Offset2)) {
515 // Get the instruction to use for unsigned 12-bit displacements.
516 int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
517 if (Disp12Opcode >= 0)
520 // All address-related instructions can use unsigned 12-bit
524 if (isInt<20>(Offset) && isInt<20>(Offset2)) {
525 // Get the instruction to use for signed 20-bit displacements.
526 int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
527 if (Disp20Opcode >= 0)
530 // Check whether Opcode allows signed 20-bit displacements.
531 if (MCID.TSFlags & SystemZII::Has20BitOffset)
537 unsigned SystemZInstrInfo::getCompareAndBranch(unsigned Opcode,
538 const MachineInstr *MI) const {
543 return SystemZ::CGRJ;
545 return MI && isInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CIJ : 0;
547 return MI && isInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CGIJ : 0;
553 void SystemZInstrInfo::loadImmediate(MachineBasicBlock &MBB,
554 MachineBasicBlock::iterator MBBI,
555 unsigned Reg, uint64_t Value) const {
556 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
558 if (isInt<16>(Value))
559 Opcode = SystemZ::LGHI;
560 else if (SystemZ::isImmLL(Value))
561 Opcode = SystemZ::LLILL;
562 else if (SystemZ::isImmLH(Value)) {
563 Opcode = SystemZ::LLILH;
566 assert(isInt<32>(Value) && "Huge values not handled yet");
567 Opcode = SystemZ::LGFI;
569 BuildMI(MBB, MBBI, DL, get(Opcode), Reg).addImm(Value);