1 //===- SystemZInstrInfo.cpp - SystemZ Instruction Information --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SystemZ implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "SystemZInstrBuilder.h"
16 #include "SystemZInstrInfo.h"
17 #include "SystemZMachineFunctionInfo.h"
18 #include "SystemZTargetMachine.h"
19 #include "SystemZGenInstrInfo.inc"
20 #include "llvm/Function.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/PseudoSourceValue.h"
28 SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm)
29 : TargetInstrInfoImpl(SystemZInsts, array_lengthof(SystemZInsts)),
30 RI(tm, *this), TM(tm) {
31 // Fill the spill offsets map
32 static const unsigned SpillOffsTab[][2] = {
33 { SystemZ::R2D, 0x10 },
34 { SystemZ::R3D, 0x18 },
35 { SystemZ::R4D, 0x20 },
36 { SystemZ::R5D, 0x28 },
37 { SystemZ::R6D, 0x30 },
38 { SystemZ::R7D, 0x38 },
39 { SystemZ::R8D, 0x40 },
40 { SystemZ::R9D, 0x48 },
41 { SystemZ::R10D, 0x50 },
42 { SystemZ::R11D, 0x58 },
43 { SystemZ::R12D, 0x60 },
44 { SystemZ::R13D, 0x68 },
45 { SystemZ::R14D, 0x70 },
46 { SystemZ::R15D, 0x78 }
49 RegSpillOffsets.grow(SystemZ::NUM_TARGET_REGS);
51 for (unsigned i = 0, e = array_lengthof(SpillOffsTab); i != e; ++i)
52 RegSpillOffsets[SpillOffsTab[i][0]] = SpillOffsTab[i][1];
55 void SystemZInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
56 MachineBasicBlock::iterator MI,
57 unsigned SrcReg, bool isKill, int FrameIdx,
58 const TargetRegisterClass *RC) const {
59 DebugLoc DL = DebugLoc::getUnknownLoc();
60 if (MI != MBB.end()) DL = MI->getDebugLoc();
63 if (RC == &SystemZ::GR32RegClass ||
64 RC == &SystemZ::ADDR32RegClass)
65 Opc = SystemZ::MOV32mr;
66 else if (RC == &SystemZ::GR64RegClass ||
67 RC == &SystemZ::ADDR64RegClass) {
68 Opc = SystemZ::MOV64mr;
69 } else if (RC == &SystemZ::FP32RegClass) {
70 Opc = SystemZ::FMOV32mr;
71 } else if (RC == &SystemZ::FP64RegClass) {
72 Opc = SystemZ::FMOV64mr;
74 assert(0 && "Unsupported regclass to store");
76 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
77 .addReg(SrcReg, getKillRegState(isKill));
80 void SystemZInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
81 MachineBasicBlock::iterator MI,
82 unsigned DestReg, int FrameIdx,
83 const TargetRegisterClass *RC) const{
84 DebugLoc DL = DebugLoc::getUnknownLoc();
85 if (MI != MBB.end()) DL = MI->getDebugLoc();
88 if (RC == &SystemZ::GR32RegClass ||
89 RC == &SystemZ::ADDR32RegClass)
90 Opc = SystemZ::MOV32rm;
91 else if (RC == &SystemZ::GR64RegClass ||
92 RC == &SystemZ::ADDR64RegClass) {
93 Opc = SystemZ::MOV64rm;
94 } else if (RC == &SystemZ::FP32RegClass) {
95 Opc = SystemZ::FMOV32rm;
96 } else if (RC == &SystemZ::FP64RegClass) {
97 Opc = SystemZ::FMOV64rm;
99 assert(0 && "Unsupported regclass to store");
101 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
104 bool SystemZInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
105 MachineBasicBlock::iterator I,
106 unsigned DestReg, unsigned SrcReg,
107 const TargetRegisterClass *DestRC,
108 const TargetRegisterClass *SrcRC) const {
109 DebugLoc DL = DebugLoc::getUnknownLoc();
110 if (I != MBB.end()) DL = I->getDebugLoc();
112 // Determine if DstRC and SrcRC have a common superclass.
113 const TargetRegisterClass *CommonRC = DestRC;
115 /* Same regclass for source and dest */;
116 else if (CommonRC->hasSuperClass(SrcRC))
118 else if (!CommonRC->hasSubClass(SrcRC))
122 if (CommonRC == &SystemZ::GR64RegClass ||
123 CommonRC == &SystemZ::ADDR64RegClass) {
124 BuildMI(MBB, I, DL, get(SystemZ::MOV64rr), DestReg).addReg(SrcReg);
125 } else if (CommonRC == &SystemZ::GR32RegClass ||
126 CommonRC == &SystemZ::ADDR32RegClass) {
127 BuildMI(MBB, I, DL, get(SystemZ::MOV32rr), DestReg).addReg(SrcReg);
128 } else if (CommonRC == &SystemZ::GR64PRegClass) {
129 BuildMI(MBB, I, DL, get(SystemZ::MOV64rrP), DestReg).addReg(SrcReg);
130 } else if (CommonRC == &SystemZ::GR128RegClass) {
131 BuildMI(MBB, I, DL, get(SystemZ::MOV128rr), DestReg).addReg(SrcReg);
132 } else if (CommonRC == &SystemZ::FP32RegClass) {
133 BuildMI(MBB, I, DL, get(SystemZ::FMOV32rr), DestReg).addReg(SrcReg);
134 } else if (CommonRC == &SystemZ::FP64RegClass) {
135 BuildMI(MBB, I, DL, get(SystemZ::FMOV64rr), DestReg).addReg(SrcReg);
143 if ((SrcRC == &SystemZ::GR64RegClass &&
144 DestRC == &SystemZ::ADDR64RegClass) ||
145 (DestRC == &SystemZ::GR64RegClass &&
146 SrcRC == &SystemZ::ADDR64RegClass)) {
147 BuildMI(MBB, I, DL, get(SystemZ::MOV64rr), DestReg).addReg(SrcReg);
149 } else if ((SrcRC == &SystemZ::GR32RegClass &&
150 DestRC == &SystemZ::ADDR32RegClass) ||
151 (DestRC == &SystemZ::GR32RegClass &&
152 SrcRC == &SystemZ::ADDR32RegClass)) {
153 BuildMI(MBB, I, DL, get(SystemZ::MOV32rr), DestReg).addReg(SrcReg);
161 SystemZInstrInfo::isMoveInstr(const MachineInstr& MI,
162 unsigned &SrcReg, unsigned &DstReg,
163 unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
164 switch (MI.getOpcode()) {
167 case SystemZ::MOV32rr:
168 case SystemZ::MOV64rr:
169 case SystemZ::MOV64rrP:
170 case SystemZ::MOV128rr:
171 case SystemZ::FMOV32rr:
172 case SystemZ::FMOV64rr:
173 assert(MI.getNumOperands() >= 2 &&
174 MI.getOperand(0).isReg() &&
175 MI.getOperand(1).isReg() &&
176 "invalid register-register move instruction");
177 SrcReg = MI.getOperand(1).getReg();
178 DstReg = MI.getOperand(0).getReg();
179 SrcSubIdx = MI.getOperand(1).getSubReg();
180 DstSubIdx = MI.getOperand(0).getSubReg();
186 SystemZInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
187 MachineBasicBlock::iterator MI,
188 const std::vector<CalleeSavedInfo> &CSI) const {
192 DebugLoc DL = DebugLoc::getUnknownLoc();
193 if (MI != MBB.end()) DL = MI->getDebugLoc();
195 MachineFunction &MF = *MBB.getParent();
196 SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>();
197 unsigned CalleeFrameSize = 0;
199 // Scan the callee-saved and find the bounds of register spill area.
200 unsigned LowReg = 0, HighReg = 0, StartOffset = -1U, EndOffset = 0;
201 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
202 unsigned Reg = CSI[i].getReg();
203 const TargetRegisterClass *RegClass = CSI[i].getRegClass();
204 if (RegClass != &SystemZ::FP64RegClass) {
205 unsigned Offset = RegSpillOffsets[Reg];
206 CalleeFrameSize += 8;
207 if (StartOffset > Offset) {
208 LowReg = Reg; StartOffset = Offset;
210 if (EndOffset < Offset) {
211 HighReg = Reg; EndOffset = RegSpillOffsets[Reg];
216 // Save information for epilogue inserter.
217 MFI->setCalleeSavedFrameSize(CalleeFrameSize);
218 MFI->setLowReg(LowReg); MFI->setHighReg(HighReg);
222 // Build a store instruction. Use STORE MULTIPLE instruction if there are many
223 // registers to store, otherwise - just STORE.
224 MachineInstrBuilder MIB =
225 BuildMI(MBB, MI, DL, get((LowReg == HighReg ?
226 SystemZ::MOV64mr : SystemZ::MOV64mrm)));
228 // Add store operands.
229 MIB.addReg(SystemZ::R15D).addImm(StartOffset);
230 if (LowReg == HighReg)
232 MIB.addReg(LowReg, RegState::Kill);
233 if (LowReg != HighReg)
234 MIB.addReg(HighReg, RegState::Kill);
236 // Do a second scan adding regs as being killed by instruction
237 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
238 unsigned Reg = CSI[i].getReg();
239 // Add the callee-saved register as live-in. It's killed at the spill.
241 if (Reg != LowReg && Reg != HighReg)
242 MIB.addReg(Reg, RegState::ImplicitKill);
247 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
248 unsigned Reg = CSI[i].getReg();
249 const TargetRegisterClass *RegClass = CSI[i].getRegClass();
250 if (RegClass == &SystemZ::FP64RegClass) {
252 storeRegToStackSlot(MBB, MI, Reg, true, CSI[i].getFrameIdx(), RegClass);
260 SystemZInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
261 MachineBasicBlock::iterator MI,
262 const std::vector<CalleeSavedInfo> &CSI) const {
266 DebugLoc DL = DebugLoc::getUnknownLoc();
267 if (MI != MBB.end()) DL = MI->getDebugLoc();
269 MachineFunction &MF = *MBB.getParent();
270 const TargetRegisterInfo *RegInfo= MF.getTarget().getRegisterInfo();
271 SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>();
273 // Restore FP registers
274 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
275 unsigned Reg = CSI[i].getReg();
276 const TargetRegisterClass *RegClass = CSI[i].getRegClass();
277 if (RegClass == &SystemZ::FP64RegClass)
278 loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RegClass);
281 // Restore GP registers
282 unsigned LowReg = MFI->getLowReg(), HighReg = MFI->getHighReg();
283 unsigned StartOffset = RegSpillOffsets[LowReg];
286 // Build a load instruction. Use LOAD MULTIPLE instruction if there are many
287 // registers to load, otherwise - just LOAD.
288 MachineInstrBuilder MIB =
289 BuildMI(MBB, MI, DL, get((LowReg == HighReg ?
290 SystemZ::MOV64rm : SystemZ::MOV64rmm)));
291 // Add store operands.
292 MIB.addReg(LowReg, RegState::Define);
293 if (LowReg != HighReg)
294 MIB.addReg(HighReg, RegState::Define);
296 MIB.addReg((RegInfo->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D));
297 MIB.addImm(StartOffset);
298 if (LowReg == HighReg)
301 // Do a second scan adding regs as being defined by instruction
302 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
303 unsigned Reg = CSI[i].getReg();
304 if (Reg != LowReg && Reg != HighReg)
305 MIB.addReg(Reg, RegState::ImplicitDefine);
313 SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
314 MachineBasicBlock *FBB,
315 const SmallVectorImpl<MachineOperand> &Cond) const {
316 // FIXME: this should probably have a DebugLoc operand
317 DebugLoc dl = DebugLoc::getUnknownLoc();
318 // Shouldn't be a fall through.
319 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
320 assert((Cond.size() == 1 || Cond.size() == 0) &&
321 "SystemZ branch conditions have one component!");
324 // Unconditional branch?
325 assert(!FBB && "Unconditional branch with multiple successors!");
326 BuildMI(&MBB, dl, get(SystemZ::JMP)).addMBB(TBB);
330 // Conditional branch.
332 SystemZCC::CondCodes CC = (SystemZCC::CondCodes)Cond[0].getImm();
333 BuildMI(&MBB, dl, getBrCond(CC)).addMBB(TBB);
337 // Two-way Conditional branch. Insert the second branch.
338 BuildMI(&MBB, dl, get(SystemZ::JMP)).addMBB(FBB);
344 const TargetInstrDesc&
345 SystemZInstrInfo::getBrCond(SystemZCC::CondCodes CC) const {
349 assert(0 && "Unknown condition code!");
397 const TargetInstrDesc&
398 SystemZInstrInfo::getLongDispOpc(unsigned Opc) const {
400 case SystemZ::MOV32mr:
401 Opc = SystemZ::MOV32mry;
403 case SystemZ::MOV32rm:
404 Opc = SystemZ::MOV32rmy;
406 case SystemZ::MOVSX32rm16:
407 Opc = SystemZ::MOVSX32rm16y;
409 case SystemZ::MOV32m8r:
410 Opc = SystemZ::MOV32m8ry;
412 case SystemZ::MOV32m16r:
413 Opc = SystemZ::MOV32m16ry;
415 case SystemZ::MOV64m8r:
416 Opc = SystemZ::MOV64m8ry;
418 case SystemZ::MOV64m16r:
419 Opc = SystemZ::MOV64m16ry;
421 case SystemZ::MOV64m32r:
422 Opc = SystemZ::MOV64m32ry;
424 case SystemZ::MOV8mi:
425 Opc = SystemZ::MOV8miy;
427 case SystemZ::MUL32rm:
428 Opc = SystemZ::MUL32rmy;
430 case SystemZ::CMP32rm:
431 Opc = SystemZ::CMP32rmy;
433 case SystemZ::UCMP32rm:
434 Opc = SystemZ::UCMP32rmy;
436 case SystemZ::FMOV32mr:
437 Opc = SystemZ::FMOV32mry;
439 case SystemZ::FMOV64mr:
440 Opc = SystemZ::FMOV64mry;