1 //===-- SystemZInstrInfo.cpp - SystemZ instruction information ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SystemZ implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "SystemZInstrInfo.h"
15 #include "SystemZTargetMachine.h"
16 #include "SystemZInstrBuilder.h"
17 #include "llvm/CodeGen/LiveVariables.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #define GET_INSTRINFO_CTOR
21 #define GET_INSTRMAP_INFO
22 #include "SystemZGenInstrInfo.inc"
26 // Return a mask with Count low bits set.
27 static uint64_t allOnes(unsigned int Count) {
28 return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1;
31 // Reg should be a 32-bit GPR. Return true if it is a high register rather
32 // than a low register.
33 static bool isHighReg(unsigned int Reg) {
34 if (SystemZ::GRH32BitRegClass.contains(Reg))
36 assert(SystemZ::GR32BitRegClass.contains(Reg) && "Invalid GRX32");
40 SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm)
41 : SystemZGenInstrInfo(SystemZ::ADJCALLSTACKDOWN, SystemZ::ADJCALLSTACKUP),
45 // MI is a 128-bit load or store. Split it into two 64-bit loads or stores,
46 // each having the opcode given by NewOpcode.
47 void SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI,
48 unsigned NewOpcode) const {
49 MachineBasicBlock *MBB = MI->getParent();
50 MachineFunction &MF = *MBB->getParent();
52 // Get two load or store instructions. Use the original instruction for one
53 // of them (arbitarily the second here) and create a clone for the other.
54 MachineInstr *EarlierMI = MF.CloneMachineInstr(MI);
55 MBB->insert(MI, EarlierMI);
57 // Set up the two 64-bit registers.
58 MachineOperand &HighRegOp = EarlierMI->getOperand(0);
59 MachineOperand &LowRegOp = MI->getOperand(0);
60 HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64));
61 LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64));
63 // The address in the first (high) instruction is already correct.
64 // Adjust the offset in the second (low) instruction.
65 MachineOperand &HighOffsetOp = EarlierMI->getOperand(2);
66 MachineOperand &LowOffsetOp = MI->getOperand(2);
67 LowOffsetOp.setImm(LowOffsetOp.getImm() + 8);
70 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm());
71 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm());
72 assert(HighOpcode && LowOpcode && "Both offsets should be in range");
74 EarlierMI->setDesc(get(HighOpcode));
75 MI->setDesc(get(LowOpcode));
78 // Split ADJDYNALLOC instruction MI.
79 void SystemZInstrInfo::splitAdjDynAlloc(MachineBasicBlock::iterator MI) const {
80 MachineBasicBlock *MBB = MI->getParent();
81 MachineFunction &MF = *MBB->getParent();
82 MachineFrameInfo *MFFrame = MF.getFrameInfo();
83 MachineOperand &OffsetMO = MI->getOperand(2);
85 uint64_t Offset = (MFFrame->getMaxCallFrameSize() +
86 SystemZMC::CallFrameSize +
88 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset);
89 assert(NewOpcode && "No support for huge argument lists yet");
90 MI->setDesc(get(NewOpcode));
91 OffsetMO.setImm(Offset);
94 // MI is an RI-style pseudo instruction. Replace it with LowOpcode
95 // if the first operand is a low GR32 and HighOpcode if the first operand
96 // is a high GR32. ConvertHigh is true if LowOpcode takes a signed operand
97 // and HighOpcode takes an unsigned 32-bit operand. In those cases,
98 // MI has the same kind of operand as LowOpcode, so needs to be converted
99 // if HighOpcode is used.
100 void SystemZInstrInfo::expandRIPseudo(MachineInstr *MI, unsigned LowOpcode,
102 bool ConvertHigh) const {
103 unsigned Reg = MI->getOperand(0).getReg();
104 bool IsHigh = isHighReg(Reg);
105 MI->setDesc(get(IsHigh ? HighOpcode : LowOpcode));
106 if (IsHigh && ConvertHigh)
107 MI->getOperand(1).setImm(uint32_t(MI->getOperand(1).getImm()));
110 // MI is an RXY-style pseudo instruction. Replace it with LowOpcode
111 // if the first operand is a low GR32 and HighOpcode if the first operand
113 void SystemZInstrInfo::expandRXYPseudo(MachineInstr *MI, unsigned LowOpcode,
114 unsigned HighOpcode) const {
115 unsigned Reg = MI->getOperand(0).getReg();
116 unsigned Opcode = getOpcodeForOffset(isHighReg(Reg) ? HighOpcode : LowOpcode,
117 MI->getOperand(2).getImm());
118 MI->setDesc(get(Opcode));
121 // MI is an RR-style pseudo instruction that zero-extends the low Size bits
122 // of one GRX32 into another. Replace it with LowOpcode if both operands
123 // are low registers, otherwise use RISB[LH]G.
124 void SystemZInstrInfo::expandZExtPseudo(MachineInstr *MI, unsigned LowOpcode,
125 unsigned Size) const {
126 emitGRX32Move(*MI->getParent(), MI, MI->getDebugLoc(),
127 MI->getOperand(0).getReg(), MI->getOperand(1).getReg(),
128 LowOpcode, Size, MI->getOperand(1).isKill());
129 MI->eraseFromParent();
132 // Emit a zero-extending move from 32-bit GPR SrcReg to 32-bit GPR
133 // DestReg before MBBI in MBB. Use LowLowOpcode when both DestReg and SrcReg
134 // are low registers, otherwise use RISB[LH]G. Size is the number of bits
135 // taken from the low end of SrcReg (8 for LLCR, 16 for LLHR and 32 for LR).
136 // KillSrc is true if this move is the last use of SrcReg.
137 void SystemZInstrInfo::emitGRX32Move(MachineBasicBlock &MBB,
138 MachineBasicBlock::iterator MBBI,
139 DebugLoc DL, unsigned DestReg,
140 unsigned SrcReg, unsigned LowLowOpcode,
141 unsigned Size, bool KillSrc) const {
143 bool DestIsHigh = isHighReg(DestReg);
144 bool SrcIsHigh = isHighReg(SrcReg);
145 if (DestIsHigh && SrcIsHigh)
146 Opcode = SystemZ::RISBHH;
147 else if (DestIsHigh && !SrcIsHigh)
148 Opcode = SystemZ::RISBHL;
149 else if (!DestIsHigh && SrcIsHigh)
150 Opcode = SystemZ::RISBLH;
152 BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg)
153 .addReg(SrcReg, getKillRegState(KillSrc));
156 unsigned Rotate = (DestIsHigh != SrcIsHigh ? 32 : 0);
157 BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
158 .addReg(DestReg, RegState::Undef)
159 .addReg(SrcReg, getKillRegState(KillSrc))
160 .addImm(32 - Size).addImm(128 + 31).addImm(Rotate);
163 // If MI is a simple load or store for a frame object, return the register
164 // it loads or stores and set FrameIndex to the index of the frame object.
165 // Return 0 otherwise.
167 // Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
168 static int isSimpleMove(const MachineInstr *MI, int &FrameIndex,
170 const MCInstrDesc &MCID = MI->getDesc();
171 if ((MCID.TSFlags & Flag) &&
172 MI->getOperand(1).isFI() &&
173 MI->getOperand(2).getImm() == 0 &&
174 MI->getOperand(3).getReg() == 0) {
175 FrameIndex = MI->getOperand(1).getIndex();
176 return MI->getOperand(0).getReg();
181 unsigned SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
182 int &FrameIndex) const {
183 return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXLoad);
186 unsigned SystemZInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
187 int &FrameIndex) const {
188 return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXStore);
191 bool SystemZInstrInfo::isStackSlotCopy(const MachineInstr *MI,
193 int &SrcFrameIndex) const {
194 // Check for MVC 0(Length,FI1),0(FI2)
195 const MachineFrameInfo *MFI = MI->getParent()->getParent()->getFrameInfo();
196 if (MI->getOpcode() != SystemZ::MVC ||
197 !MI->getOperand(0).isFI() ||
198 MI->getOperand(1).getImm() != 0 ||
199 !MI->getOperand(3).isFI() ||
200 MI->getOperand(4).getImm() != 0)
203 // Check that Length covers the full slots.
204 int64_t Length = MI->getOperand(2).getImm();
205 unsigned FI1 = MI->getOperand(0).getIndex();
206 unsigned FI2 = MI->getOperand(3).getIndex();
207 if (MFI->getObjectSize(FI1) != Length ||
208 MFI->getObjectSize(FI2) != Length)
211 DestFrameIndex = FI1;
216 bool SystemZInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
217 MachineBasicBlock *&TBB,
218 MachineBasicBlock *&FBB,
219 SmallVectorImpl<MachineOperand> &Cond,
220 bool AllowModify) const {
221 // Most of the code and comments here are boilerplate.
223 // Start from the bottom of the block and work up, examining the
224 // terminator instructions.
225 MachineBasicBlock::iterator I = MBB.end();
226 while (I != MBB.begin()) {
228 if (I->isDebugValue())
231 // Working from the bottom, when we see a non-terminator instruction, we're
233 if (!isUnpredicatedTerminator(I))
236 // A terminator that isn't a branch can't easily be handled by this
241 // Can't handle indirect branches.
242 SystemZII::Branch Branch(getBranchInfo(I));
243 if (!Branch.Target->isMBB())
246 // Punt on compound branches.
247 if (Branch.Type != SystemZII::BranchNormal)
250 if (Branch.CCMask == SystemZ::CCMASK_ANY) {
251 // Handle unconditional branches.
253 TBB = Branch.Target->getMBB();
257 // If the block has any instructions after a JMP, delete them.
258 while (llvm::next(I) != MBB.end())
259 llvm::next(I)->eraseFromParent();
264 // Delete the JMP if it's equivalent to a fall-through.
265 if (MBB.isLayoutSuccessor(Branch.Target->getMBB())) {
267 I->eraseFromParent();
272 // TBB is used to indicate the unconditinal destination.
273 TBB = Branch.Target->getMBB();
277 // Working from the bottom, handle the first conditional branch.
279 // FIXME: add X86-style branch swap
281 TBB = Branch.Target->getMBB();
282 Cond.push_back(MachineOperand::CreateImm(Branch.CCValid));
283 Cond.push_back(MachineOperand::CreateImm(Branch.CCMask));
287 // Handle subsequent conditional branches.
288 assert(Cond.size() == 2 && TBB && "Should have seen a conditional branch");
290 // Only handle the case where all conditional branches branch to the same
292 if (TBB != Branch.Target->getMBB())
295 // If the conditions are the same, we can leave them alone.
296 unsigned OldCCValid = Cond[0].getImm();
297 unsigned OldCCMask = Cond[1].getImm();
298 if (OldCCValid == Branch.CCValid && OldCCMask == Branch.CCMask)
301 // FIXME: Try combining conditions like X86 does. Should be easy on Z!
308 unsigned SystemZInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
309 // Most of the code and comments here are boilerplate.
310 MachineBasicBlock::iterator I = MBB.end();
313 while (I != MBB.begin()) {
315 if (I->isDebugValue())
319 if (!getBranchInfo(I).Target->isMBB())
321 // Remove the branch.
322 I->eraseFromParent();
330 bool SystemZInstrInfo::
331 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
332 assert(Cond.size() == 2 && "Invalid condition");
333 Cond[1].setImm(Cond[1].getImm() ^ Cond[0].getImm());
338 SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
339 MachineBasicBlock *FBB,
340 const SmallVectorImpl<MachineOperand> &Cond,
342 // In this function we output 32-bit branches, which should always
343 // have enough range. They can be shortened and relaxed by later code
344 // in the pipeline, if desired.
346 // Shouldn't be a fall through.
347 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
348 assert((Cond.size() == 2 || Cond.size() == 0) &&
349 "SystemZ branch conditions have one component!");
352 // Unconditional branch?
353 assert(!FBB && "Unconditional branch with multiple successors!");
354 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(TBB);
358 // Conditional branch.
360 unsigned CCValid = Cond[0].getImm();
361 unsigned CCMask = Cond[1].getImm();
362 BuildMI(&MBB, DL, get(SystemZ::BRC))
363 .addImm(CCValid).addImm(CCMask).addMBB(TBB);
367 // Two-way Conditional branch. Insert the second branch.
368 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(FBB);
374 bool SystemZInstrInfo::analyzeCompare(const MachineInstr *MI,
375 unsigned &SrcReg, unsigned &SrcReg2,
376 int &Mask, int &Value) const {
377 assert(MI->isCompare() && "Caller should have checked for a comparison");
379 if (MI->getNumExplicitOperands() == 2 &&
380 MI->getOperand(0).isReg() &&
381 MI->getOperand(1).isImm()) {
382 SrcReg = MI->getOperand(0).getReg();
384 Value = MI->getOperand(1).getImm();
392 // If Reg is a virtual register, return its definition, otherwise return null.
393 static MachineInstr *getDef(unsigned Reg,
394 const MachineRegisterInfo *MRI) {
395 if (TargetRegisterInfo::isPhysicalRegister(Reg))
397 return MRI->getUniqueVRegDef(Reg);
400 // Return true if MI is a shift of type Opcode by Imm bits.
401 static bool isShift(MachineInstr *MI, int Opcode, int64_t Imm) {
402 return (MI->getOpcode() == Opcode &&
403 !MI->getOperand(2).getReg() &&
404 MI->getOperand(3).getImm() == Imm);
407 // If the destination of MI has no uses, delete it as dead.
408 static void eraseIfDead(MachineInstr *MI, const MachineRegisterInfo *MRI) {
409 if (MRI->use_nodbg_empty(MI->getOperand(0).getReg()))
410 MI->eraseFromParent();
413 // Compare compares SrcReg against zero. Check whether SrcReg contains
414 // the result of an IPM sequence whose input CC survives until Compare,
415 // and whether Compare is therefore redundant. Delete it and return
417 static bool removeIPMBasedCompare(MachineInstr *Compare, unsigned SrcReg,
418 const MachineRegisterInfo *MRI,
419 const TargetRegisterInfo *TRI) {
420 MachineInstr *LGFR = 0;
421 MachineInstr *RLL = getDef(SrcReg, MRI);
422 if (RLL && RLL->getOpcode() == SystemZ::LGFR) {
424 RLL = getDef(LGFR->getOperand(1).getReg(), MRI);
426 if (!RLL || !isShift(RLL, SystemZ::RLL, 31))
429 MachineInstr *SRL = getDef(RLL->getOperand(1).getReg(), MRI);
430 if (!SRL || !isShift(SRL, SystemZ::SRL, 28))
433 MachineInstr *IPM = getDef(SRL->getOperand(1).getReg(), MRI);
434 if (!IPM || IPM->getOpcode() != SystemZ::IPM)
437 // Check that there are no assignments to CC between the IPM and Compare,
438 if (IPM->getParent() != Compare->getParent())
440 MachineBasicBlock::iterator MBBI = IPM, MBBE = Compare;
441 for (++MBBI; MBBI != MBBE; ++MBBI) {
442 MachineInstr *MI = MBBI;
443 if (MI->modifiesRegister(SystemZ::CC, TRI))
447 Compare->eraseFromParent();
449 eraseIfDead(LGFR, MRI);
450 eraseIfDead(RLL, MRI);
451 eraseIfDead(SRL, MRI);
452 eraseIfDead(IPM, MRI);
458 SystemZInstrInfo::optimizeCompareInstr(MachineInstr *Compare,
459 unsigned SrcReg, unsigned SrcReg2,
461 const MachineRegisterInfo *MRI) const {
462 assert(!SrcReg2 && "Only optimizing constant comparisons so far");
463 bool IsLogical = (Compare->getDesc().TSFlags & SystemZII::IsLogical) != 0;
466 removeIPMBasedCompare(Compare, SrcReg, MRI, TM.getRegisterInfo()))
471 // If Opcode is a move that has a conditional variant, return that variant,
472 // otherwise return 0.
473 static unsigned getConditionalMove(unsigned Opcode) {
475 case SystemZ::LR: return SystemZ::LOCR;
476 case SystemZ::LGR: return SystemZ::LOCGR;
481 bool SystemZInstrInfo::isPredicable(MachineInstr *MI) const {
482 unsigned Opcode = MI->getOpcode();
483 if (TM.getSubtargetImpl()->hasLoadStoreOnCond() &&
484 getConditionalMove(Opcode))
489 bool SystemZInstrInfo::
490 isProfitableToIfCvt(MachineBasicBlock &MBB,
491 unsigned NumCycles, unsigned ExtraPredCycles,
492 const BranchProbability &Probability) const {
493 // For now only convert single instructions.
494 return NumCycles == 1;
497 bool SystemZInstrInfo::
498 isProfitableToIfCvt(MachineBasicBlock &TMBB,
499 unsigned NumCyclesT, unsigned ExtraPredCyclesT,
500 MachineBasicBlock &FMBB,
501 unsigned NumCyclesF, unsigned ExtraPredCyclesF,
502 const BranchProbability &Probability) const {
503 // For now avoid converting mutually-exclusive cases.
507 bool SystemZInstrInfo::
508 PredicateInstruction(MachineInstr *MI,
509 const SmallVectorImpl<MachineOperand> &Pred) const {
510 assert(Pred.size() == 2 && "Invalid condition");
511 unsigned CCValid = Pred[0].getImm();
512 unsigned CCMask = Pred[1].getImm();
513 assert(CCMask > 0 && CCMask < 15 && "Invalid predicate");
514 unsigned Opcode = MI->getOpcode();
515 if (TM.getSubtargetImpl()->hasLoadStoreOnCond()) {
516 if (unsigned CondOpcode = getConditionalMove(Opcode)) {
517 MI->setDesc(get(CondOpcode));
518 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
519 .addImm(CCValid).addImm(CCMask)
520 .addReg(SystemZ::CC, RegState::Implicit);;
528 SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
529 MachineBasicBlock::iterator MBBI, DebugLoc DL,
530 unsigned DestReg, unsigned SrcReg,
531 bool KillSrc) const {
532 // Split 128-bit GPR moves into two 64-bit moves. This handles ADDR128 too.
533 if (SystemZ::GR128BitRegClass.contains(DestReg, SrcReg)) {
534 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_h64),
535 RI.getSubReg(SrcReg, SystemZ::subreg_h64), KillSrc);
536 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_l64),
537 RI.getSubReg(SrcReg, SystemZ::subreg_l64), KillSrc);
541 if (SystemZ::GRX32BitRegClass.contains(DestReg, SrcReg)) {
542 emitGRX32Move(MBB, MBBI, DL, DestReg, SrcReg, SystemZ::LR, 32, KillSrc);
546 // Everything else needs only one instruction.
548 if (SystemZ::GR64BitRegClass.contains(DestReg, SrcReg))
549 Opcode = SystemZ::LGR;
550 else if (SystemZ::FP32BitRegClass.contains(DestReg, SrcReg))
551 Opcode = SystemZ::LER;
552 else if (SystemZ::FP64BitRegClass.contains(DestReg, SrcReg))
553 Opcode = SystemZ::LDR;
554 else if (SystemZ::FP128BitRegClass.contains(DestReg, SrcReg))
555 Opcode = SystemZ::LXR;
557 llvm_unreachable("Impossible reg-to-reg copy");
559 BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
560 .addReg(SrcReg, getKillRegState(KillSrc));
564 SystemZInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
565 MachineBasicBlock::iterator MBBI,
566 unsigned SrcReg, bool isKill,
568 const TargetRegisterClass *RC,
569 const TargetRegisterInfo *TRI) const {
570 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
572 // Callers may expect a single instruction, so keep 128-bit moves
573 // together for now and lower them after register allocation.
574 unsigned LoadOpcode, StoreOpcode;
575 getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
576 addFrameReference(BuildMI(MBB, MBBI, DL, get(StoreOpcode))
577 .addReg(SrcReg, getKillRegState(isKill)), FrameIdx);
581 SystemZInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
582 MachineBasicBlock::iterator MBBI,
583 unsigned DestReg, int FrameIdx,
584 const TargetRegisterClass *RC,
585 const TargetRegisterInfo *TRI) const {
586 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
588 // Callers may expect a single instruction, so keep 128-bit moves
589 // together for now and lower them after register allocation.
590 unsigned LoadOpcode, StoreOpcode;
591 getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
592 addFrameReference(BuildMI(MBB, MBBI, DL, get(LoadOpcode), DestReg),
596 // Return true if MI is a simple load or store with a 12-bit displacement
597 // and no index. Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
598 static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag) {
599 const MCInstrDesc &MCID = MI->getDesc();
600 return ((MCID.TSFlags & Flag) &&
601 isUInt<12>(MI->getOperand(2).getImm()) &&
602 MI->getOperand(3).getReg() == 0);
607 LogicOp() : RegSize(0), ImmLSB(0), ImmSize(0) {}
608 LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize)
609 : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}
611 operator bool() const { return RegSize; }
613 unsigned RegSize, ImmLSB, ImmSize;
617 static LogicOp interpretAndImmediate(unsigned Opcode) {
619 case SystemZ::NILMux: return LogicOp(32, 0, 16);
620 case SystemZ::NIHMux: return LogicOp(32, 16, 16);
621 case SystemZ::NILL64: return LogicOp(64, 0, 16);
622 case SystemZ::NILH64: return LogicOp(64, 16, 16);
623 case SystemZ::NIHL64: return LogicOp(64, 32, 16);
624 case SystemZ::NIHH64: return LogicOp(64, 48, 16);
625 case SystemZ::NIFMux: return LogicOp(32, 0, 32);
626 case SystemZ::NILF64: return LogicOp(64, 0, 32);
627 case SystemZ::NIHF64: return LogicOp(64, 32, 32);
628 default: return LogicOp();
632 // Used to return from convertToThreeAddress after replacing two-address
633 // instruction OldMI with three-address instruction NewMI.
634 static MachineInstr *finishConvertToThreeAddress(MachineInstr *OldMI,
638 unsigned NumOps = OldMI->getNumOperands();
639 for (unsigned I = 1; I < NumOps; ++I) {
640 MachineOperand &Op = OldMI->getOperand(I);
641 if (Op.isReg() && Op.isKill())
642 LV->replaceKillInstruction(Op.getReg(), OldMI, NewMI);
649 SystemZInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
650 MachineBasicBlock::iterator &MBBI,
651 LiveVariables *LV) const {
652 MachineInstr *MI = MBBI;
653 MachineBasicBlock *MBB = MI->getParent();
655 unsigned Opcode = MI->getOpcode();
656 unsigned NumOps = MI->getNumOperands();
658 // Try to convert something like SLL into SLLK, if supported.
659 // We prefer to keep the two-operand form where possible both
660 // because it tends to be shorter and because some instructions
661 // have memory forms that can be used during spilling.
662 if (TM.getSubtargetImpl()->hasDistinctOps()) {
663 int ThreeOperandOpcode = SystemZ::getThreeOperandOpcode(Opcode);
664 if (ThreeOperandOpcode >= 0) {
665 MachineOperand &Dest = MI->getOperand(0);
666 MachineOperand &Src = MI->getOperand(1);
667 MachineInstrBuilder MIB =
668 BuildMI(*MBB, MBBI, MI->getDebugLoc(), get(ThreeOperandOpcode))
670 // Keep the kill state, but drop the tied flag.
671 MIB.addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg());
672 // Keep the remaining operands as-is.
673 for (unsigned I = 2; I < NumOps; ++I)
674 MIB.addOperand(MI->getOperand(I));
675 return finishConvertToThreeAddress(MI, MIB, LV);
679 // Try to convert an AND into an RISBG-type instruction.
680 if (LogicOp And = interpretAndImmediate(Opcode)) {
681 uint64_t Imm = MI->getOperand(2).getImm() << And.ImmLSB;
682 // AND IMMEDIATE leaves the other bits of the register unchanged.
683 Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB);
685 if (isRxSBGMask(Imm, And.RegSize, Start, End)) {
687 if (And.RegSize == 64)
688 NewOpcode = SystemZ::RISBG;
690 NewOpcode = SystemZ::RISBMux;
694 MachineOperand &Dest = MI->getOperand(0);
695 MachineOperand &Src = MI->getOperand(1);
696 MachineInstrBuilder MIB =
697 BuildMI(*MBB, MI, MI->getDebugLoc(), get(NewOpcode))
698 .addOperand(Dest).addReg(0)
699 .addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg())
700 .addImm(Start).addImm(End + 128).addImm(0);
701 return finishConvertToThreeAddress(MI, MIB, LV);
708 SystemZInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
710 const SmallVectorImpl<unsigned> &Ops,
711 int FrameIndex) const {
712 const MachineFrameInfo *MFI = MF.getFrameInfo();
713 unsigned Size = MFI->getObjectSize(FrameIndex);
715 // Eary exit for cases we don't care about
719 unsigned OpNum = Ops[0];
720 assert(Size == MF.getRegInfo()
721 .getRegClass(MI->getOperand(OpNum).getReg())->getSize() &&
722 "Invalid size combination");
724 unsigned Opcode = MI->getOpcode();
725 if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {
726 bool Op0IsGPR = (Opcode == SystemZ::LGDR);
727 bool Op1IsGPR = (Opcode == SystemZ::LDGR);
728 // If we're spilling the destination of an LDGR or LGDR, store the
729 // source register instead.
731 unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD;
732 return BuildMI(MF, MI->getDebugLoc(), get(StoreOpcode))
733 .addOperand(MI->getOperand(1)).addFrameIndex(FrameIndex)
734 .addImm(0).addReg(0);
736 // If we're spilling the source of an LDGR or LGDR, load the
737 // destination register instead.
739 unsigned LoadOpcode = Op0IsGPR ? SystemZ::LG : SystemZ::LD;
740 unsigned Dest = MI->getOperand(0).getReg();
741 return BuildMI(MF, MI->getDebugLoc(), get(LoadOpcode), Dest)
742 .addFrameIndex(FrameIndex).addImm(0).addReg(0);
746 // Look for cases where the source of a simple store or the destination
747 // of a simple load is being spilled. Try to use MVC instead.
749 // Although MVC is in practice a fast choice in these cases, it is still
750 // logically a bytewise copy. This means that we cannot use it if the
751 // load or store is volatile. We also wouldn't be able to use MVC if
752 // the two memories partially overlap, but that case cannot occur here,
753 // because we know that one of the memories is a full frame index.
755 // For performance reasons, we also want to avoid using MVC if the addresses
756 // might be equal. We don't worry about that case here, because spill slot
757 // coloring happens later, and because we have special code to remove
758 // MVCs that turn out to be redundant.
759 if (OpNum == 0 && MI->hasOneMemOperand()) {
760 MachineMemOperand *MMO = *MI->memoperands_begin();
761 if (MMO->getSize() == Size && !MMO->isVolatile()) {
762 // Handle conversion of loads.
763 if (isSimpleBD12Move(MI, SystemZII::SimpleBDXLoad)) {
764 return BuildMI(MF, MI->getDebugLoc(), get(SystemZ::MVC))
765 .addFrameIndex(FrameIndex).addImm(0).addImm(Size)
766 .addOperand(MI->getOperand(1)).addImm(MI->getOperand(2).getImm())
769 // Handle conversion of stores.
770 if (isSimpleBD12Move(MI, SystemZII::SimpleBDXStore)) {
771 return BuildMI(MF, MI->getDebugLoc(), get(SystemZ::MVC))
772 .addOperand(MI->getOperand(1)).addImm(MI->getOperand(2).getImm())
773 .addImm(Size).addFrameIndex(FrameIndex).addImm(0)
779 // If the spilled operand is the final one, try to change <INSN>R
781 int MemOpcode = SystemZ::getMemOpcode(Opcode);
782 if (MemOpcode >= 0) {
783 unsigned NumOps = MI->getNumExplicitOperands();
784 if (OpNum == NumOps - 1) {
785 const MCInstrDesc &MemDesc = get(MemOpcode);
786 uint64_t AccessBytes = SystemZII::getAccessSize(MemDesc.TSFlags);
787 assert(AccessBytes != 0 && "Size of access should be known");
788 assert(AccessBytes <= Size && "Access outside the frame index");
789 uint64_t Offset = Size - AccessBytes;
790 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(MemOpcode));
791 for (unsigned I = 0; I < OpNum; ++I)
792 MIB.addOperand(MI->getOperand(I));
793 MIB.addFrameIndex(FrameIndex).addImm(Offset);
794 if (MemDesc.TSFlags & SystemZII::HasIndex)
804 SystemZInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr* MI,
805 const SmallVectorImpl<unsigned> &Ops,
806 MachineInstr* LoadMI) const {
811 SystemZInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
812 switch (MI->getOpcode()) {
814 splitMove(MI, SystemZ::LG);
818 splitMove(MI, SystemZ::STG);
822 splitMove(MI, SystemZ::LD);
826 splitMove(MI, SystemZ::STD);
830 expandRXYPseudo(MI, SystemZ::LB, SystemZ::LBH);
834 expandRXYPseudo(MI, SystemZ::LH, SystemZ::LHH);
837 case SystemZ::LLCRMux:
838 expandZExtPseudo(MI, SystemZ::LLCR, 8);
841 case SystemZ::LLHRMux:
842 expandZExtPseudo(MI, SystemZ::LLHR, 16);
845 case SystemZ::LLCMux:
846 expandRXYPseudo(MI, SystemZ::LLC, SystemZ::LLCH);
849 case SystemZ::LLHMux:
850 expandRXYPseudo(MI, SystemZ::LLH, SystemZ::LLHH);
854 expandRXYPseudo(MI, SystemZ::L, SystemZ::LFH);
857 case SystemZ::STCMux:
858 expandRXYPseudo(MI, SystemZ::STC, SystemZ::STCH);
861 case SystemZ::STHMux:
862 expandRXYPseudo(MI, SystemZ::STH, SystemZ::STHH);
866 expandRXYPseudo(MI, SystemZ::ST, SystemZ::STFH);
869 case SystemZ::LHIMux:
870 expandRIPseudo(MI, SystemZ::LHI, SystemZ::IIHF, true);
873 case SystemZ::IIFMux:
874 expandRIPseudo(MI, SystemZ::IILF, SystemZ::IIHF, false);
877 case SystemZ::IILMux:
878 expandRIPseudo(MI, SystemZ::IILL, SystemZ::IIHL, false);
881 case SystemZ::IIHMux:
882 expandRIPseudo(MI, SystemZ::IILH, SystemZ::IIHH, false);
885 case SystemZ::NIFMux:
886 expandRIPseudo(MI, SystemZ::NILF, SystemZ::NIHF, false);
889 case SystemZ::NILMux:
890 expandRIPseudo(MI, SystemZ::NILL, SystemZ::NIHL, false);
893 case SystemZ::NIHMux:
894 expandRIPseudo(MI, SystemZ::NILH, SystemZ::NIHH, false);
897 case SystemZ::OIFMux:
898 expandRIPseudo(MI, SystemZ::OILF, SystemZ::OIHF, false);
901 case SystemZ::OILMux:
902 expandRIPseudo(MI, SystemZ::OILL, SystemZ::OIHL, false);
905 case SystemZ::OIHMux:
906 expandRIPseudo(MI, SystemZ::OILH, SystemZ::OIHH, false);
909 case SystemZ::XIFMux:
910 expandRIPseudo(MI, SystemZ::XILF, SystemZ::XIHF, false);
913 case SystemZ::TMLMux:
914 expandRIPseudo(MI, SystemZ::TMLL, SystemZ::TMHL, false);
917 case SystemZ::TMHMux:
918 expandRIPseudo(MI, SystemZ::TMLH, SystemZ::TMHH, false);
921 case SystemZ::RISBMux: {
922 bool DestIsHigh = isHighReg(MI->getOperand(0).getReg());
923 bool SrcIsHigh = isHighReg(MI->getOperand(2).getReg());
924 if (SrcIsHigh == DestIsHigh)
925 MI->setDesc(get(DestIsHigh ? SystemZ::RISBHH : SystemZ::RISBLL));
927 MI->setDesc(get(DestIsHigh ? SystemZ::RISBHL : SystemZ::RISBLH));
928 MI->getOperand(5).setImm(MI->getOperand(5).getImm() ^ 32);
933 case SystemZ::ADJDYNALLOC:
934 splitAdjDynAlloc(MI);
942 uint64_t SystemZInstrInfo::getInstSizeInBytes(const MachineInstr *MI) const {
943 if (MI->getOpcode() == TargetOpcode::INLINEASM) {
944 const MachineFunction *MF = MI->getParent()->getParent();
945 const char *AsmStr = MI->getOperand(0).getSymbolName();
946 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
948 return MI->getDesc().getSize();
952 SystemZInstrInfo::getBranchInfo(const MachineInstr *MI) const {
953 switch (MI->getOpcode()) {
957 return SystemZII::Branch(SystemZII::BranchNormal, SystemZ::CCMASK_ANY,
958 SystemZ::CCMASK_ANY, &MI->getOperand(0));
962 return SystemZII::Branch(SystemZII::BranchNormal,
963 MI->getOperand(0).getImm(),
964 MI->getOperand(1).getImm(), &MI->getOperand(2));
967 return SystemZII::Branch(SystemZII::BranchCT, SystemZ::CCMASK_ICMP,
968 SystemZ::CCMASK_CMP_NE, &MI->getOperand(2));
971 return SystemZII::Branch(SystemZII::BranchCTG, SystemZ::CCMASK_ICMP,
972 SystemZ::CCMASK_CMP_NE, &MI->getOperand(2));
976 return SystemZII::Branch(SystemZII::BranchC, SystemZ::CCMASK_ICMP,
977 MI->getOperand(2).getImm(), &MI->getOperand(3));
981 return SystemZII::Branch(SystemZII::BranchCL, SystemZ::CCMASK_ICMP,
982 MI->getOperand(2).getImm(), &MI->getOperand(3));
986 return SystemZII::Branch(SystemZII::BranchCG, SystemZ::CCMASK_ICMP,
987 MI->getOperand(2).getImm(), &MI->getOperand(3));
991 return SystemZII::Branch(SystemZII::BranchCLG, SystemZ::CCMASK_ICMP,
992 MI->getOperand(2).getImm(), &MI->getOperand(3));
995 llvm_unreachable("Unrecognized branch opcode");
999 void SystemZInstrInfo::getLoadStoreOpcodes(const TargetRegisterClass *RC,
1000 unsigned &LoadOpcode,
1001 unsigned &StoreOpcode) const {
1002 if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) {
1003 LoadOpcode = SystemZ::L;
1004 StoreOpcode = SystemZ::ST;
1005 } else if (RC == &SystemZ::GRH32BitRegClass) {
1006 LoadOpcode = SystemZ::LFH;
1007 StoreOpcode = SystemZ::STFH;
1008 } else if (RC == &SystemZ::GRX32BitRegClass) {
1009 LoadOpcode = SystemZ::LMux;
1010 StoreOpcode = SystemZ::STMux;
1011 } else if (RC == &SystemZ::GR64BitRegClass ||
1012 RC == &SystemZ::ADDR64BitRegClass) {
1013 LoadOpcode = SystemZ::LG;
1014 StoreOpcode = SystemZ::STG;
1015 } else if (RC == &SystemZ::GR128BitRegClass ||
1016 RC == &SystemZ::ADDR128BitRegClass) {
1017 LoadOpcode = SystemZ::L128;
1018 StoreOpcode = SystemZ::ST128;
1019 } else if (RC == &SystemZ::FP32BitRegClass) {
1020 LoadOpcode = SystemZ::LE;
1021 StoreOpcode = SystemZ::STE;
1022 } else if (RC == &SystemZ::FP64BitRegClass) {
1023 LoadOpcode = SystemZ::LD;
1024 StoreOpcode = SystemZ::STD;
1025 } else if (RC == &SystemZ::FP128BitRegClass) {
1026 LoadOpcode = SystemZ::LX;
1027 StoreOpcode = SystemZ::STX;
1029 llvm_unreachable("Unsupported regclass to load or store");
1032 unsigned SystemZInstrInfo::getOpcodeForOffset(unsigned Opcode,
1033 int64_t Offset) const {
1034 const MCInstrDesc &MCID = get(Opcode);
1035 int64_t Offset2 = (MCID.TSFlags & SystemZII::Is128Bit ? Offset + 8 : Offset);
1036 if (isUInt<12>(Offset) && isUInt<12>(Offset2)) {
1037 // Get the instruction to use for unsigned 12-bit displacements.
1038 int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
1039 if (Disp12Opcode >= 0)
1040 return Disp12Opcode;
1042 // All address-related instructions can use unsigned 12-bit
1046 if (isInt<20>(Offset) && isInt<20>(Offset2)) {
1047 // Get the instruction to use for signed 20-bit displacements.
1048 int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
1049 if (Disp20Opcode >= 0)
1050 return Disp20Opcode;
1052 // Check whether Opcode allows signed 20-bit displacements.
1053 if (MCID.TSFlags & SystemZII::Has20BitOffset)
1059 unsigned SystemZInstrInfo::getLoadAndTest(unsigned Opcode) const {
1061 case SystemZ::L: return SystemZ::LT;
1062 case SystemZ::LY: return SystemZ::LT;
1063 case SystemZ::LG: return SystemZ::LTG;
1064 case SystemZ::LGF: return SystemZ::LTGF;
1065 case SystemZ::LR: return SystemZ::LTR;
1066 case SystemZ::LGFR: return SystemZ::LTGFR;
1067 case SystemZ::LGR: return SystemZ::LTGR;
1068 case SystemZ::LER: return SystemZ::LTEBR;
1069 case SystemZ::LDR: return SystemZ::LTDBR;
1070 case SystemZ::LXR: return SystemZ::LTXBR;
1075 // Return true if Mask matches the regexp 0*1+0*, given that zero masks
1076 // have already been filtered out. Store the first set bit in LSB and
1077 // the number of set bits in Length if so.
1078 static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length) {
1079 unsigned First = findFirstSet(Mask);
1080 uint64_t Top = (Mask >> First) + 1;
1081 if ((Top & -Top) == Top) {
1083 Length = findFirstSet(Top);
1089 bool SystemZInstrInfo::isRxSBGMask(uint64_t Mask, unsigned BitSize,
1090 unsigned &Start, unsigned &End) const {
1091 // Reject trivial all-zero masks.
1095 // Handle the 1+0+ or 0+1+0* cases. Start then specifies the index of
1096 // the msb and End specifies the index of the lsb.
1097 unsigned LSB, Length;
1098 if (isStringOfOnes(Mask, LSB, Length)) {
1099 Start = 63 - (LSB + Length - 1);
1104 // Handle the wrap-around 1+0+1+ cases. Start then specifies the msb
1105 // of the low 1s and End specifies the lsb of the high 1s.
1106 if (isStringOfOnes(Mask ^ allOnes(BitSize), LSB, Length)) {
1107 assert(LSB > 0 && "Bottom bit must be set");
1108 assert(LSB + Length < BitSize && "Top bit must be set");
1109 Start = 63 - (LSB - 1);
1110 End = 63 - (LSB + Length);
1117 unsigned SystemZInstrInfo::getCompareAndBranch(unsigned Opcode,
1118 const MachineInstr *MI) const {
1121 return SystemZ::CRJ;
1123 return SystemZ::CGRJ;
1125 return MI && isInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CIJ : 0;
1127 return MI && isInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CGIJ : 0;
1129 return SystemZ::CLRJ;
1131 return SystemZ::CLGRJ;
1133 return MI && isUInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CLIJ : 0;
1134 case SystemZ::CLGFI:
1135 return MI && isUInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CLGIJ : 0;
1141 void SystemZInstrInfo::loadImmediate(MachineBasicBlock &MBB,
1142 MachineBasicBlock::iterator MBBI,
1143 unsigned Reg, uint64_t Value) const {
1144 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1146 if (isInt<16>(Value))
1147 Opcode = SystemZ::LGHI;
1148 else if (SystemZ::isImmLL(Value))
1149 Opcode = SystemZ::LLILL;
1150 else if (SystemZ::isImmLH(Value)) {
1151 Opcode = SystemZ::LLILH;
1154 assert(isInt<32>(Value) && "Huge values not handled yet");
1155 Opcode = SystemZ::LGFI;
1157 BuildMI(MBB, MBBI, DL, get(Opcode), Reg).addImm(Value);