1 //===-- SystemZInstrInfo.cpp - SystemZ instruction information ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SystemZ implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "SystemZInstrInfo.h"
15 #include "SystemZTargetMachine.h"
16 #include "SystemZInstrBuilder.h"
17 #include "llvm/CodeGen/LiveVariables.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #define GET_INSTRINFO_CTOR
21 #define GET_INSTRMAP_INFO
22 #include "SystemZGenInstrInfo.inc"
26 SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm)
27 : SystemZGenInstrInfo(SystemZ::ADJCALLSTACKDOWN, SystemZ::ADJCALLSTACKUP),
31 // MI is a 128-bit load or store. Split it into two 64-bit loads or stores,
32 // each having the opcode given by NewOpcode.
33 void SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI,
34 unsigned NewOpcode) const {
35 MachineBasicBlock *MBB = MI->getParent();
36 MachineFunction &MF = *MBB->getParent();
38 // Get two load or store instructions. Use the original instruction for one
39 // of them (arbitarily the second here) and create a clone for the other.
40 MachineInstr *EarlierMI = MF.CloneMachineInstr(MI);
41 MBB->insert(MI, EarlierMI);
43 // Set up the two 64-bit registers.
44 MachineOperand &HighRegOp = EarlierMI->getOperand(0);
45 MachineOperand &LowRegOp = MI->getOperand(0);
46 HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_high));
47 LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_low));
49 // The address in the first (high) instruction is already correct.
50 // Adjust the offset in the second (low) instruction.
51 MachineOperand &HighOffsetOp = EarlierMI->getOperand(2);
52 MachineOperand &LowOffsetOp = MI->getOperand(2);
53 LowOffsetOp.setImm(LowOffsetOp.getImm() + 8);
56 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm());
57 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm());
58 assert(HighOpcode && LowOpcode && "Both offsets should be in range");
60 EarlierMI->setDesc(get(HighOpcode));
61 MI->setDesc(get(LowOpcode));
64 // Split ADJDYNALLOC instruction MI.
65 void SystemZInstrInfo::splitAdjDynAlloc(MachineBasicBlock::iterator MI) const {
66 MachineBasicBlock *MBB = MI->getParent();
67 MachineFunction &MF = *MBB->getParent();
68 MachineFrameInfo *MFFrame = MF.getFrameInfo();
69 MachineOperand &OffsetMO = MI->getOperand(2);
71 uint64_t Offset = (MFFrame->getMaxCallFrameSize() +
72 SystemZMC::CallFrameSize +
74 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset);
75 assert(NewOpcode && "No support for huge argument lists yet");
76 MI->setDesc(get(NewOpcode));
77 OffsetMO.setImm(Offset);
80 // If MI is a simple load or store for a frame object, return the register
81 // it loads or stores and set FrameIndex to the index of the frame object.
82 // Return 0 otherwise.
84 // Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
85 static int isSimpleMove(const MachineInstr *MI, int &FrameIndex,
87 const MCInstrDesc &MCID = MI->getDesc();
88 if ((MCID.TSFlags & Flag) &&
89 MI->getOperand(1).isFI() &&
90 MI->getOperand(2).getImm() == 0 &&
91 MI->getOperand(3).getReg() == 0) {
92 FrameIndex = MI->getOperand(1).getIndex();
93 return MI->getOperand(0).getReg();
98 unsigned SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
99 int &FrameIndex) const {
100 return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXLoad);
103 unsigned SystemZInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
104 int &FrameIndex) const {
105 return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXStore);
108 bool SystemZInstrInfo::isStackSlotCopy(const MachineInstr *MI,
110 int &SrcFrameIndex) const {
111 // Check for MVC 0(Length,FI1),0(FI2)
112 const MachineFrameInfo *MFI = MI->getParent()->getParent()->getFrameInfo();
113 if (MI->getOpcode() != SystemZ::MVC ||
114 !MI->getOperand(0).isFI() ||
115 MI->getOperand(1).getImm() != 0 ||
116 !MI->getOperand(3).isFI() ||
117 MI->getOperand(4).getImm() != 0)
120 // Check that Length covers the full slots.
121 int64_t Length = MI->getOperand(2).getImm();
122 unsigned FI1 = MI->getOperand(0).getIndex();
123 unsigned FI2 = MI->getOperand(3).getIndex();
124 if (MFI->getObjectSize(FI1) != Length ||
125 MFI->getObjectSize(FI2) != Length)
128 DestFrameIndex = FI1;
133 bool SystemZInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
134 MachineBasicBlock *&TBB,
135 MachineBasicBlock *&FBB,
136 SmallVectorImpl<MachineOperand> &Cond,
137 bool AllowModify) const {
138 // Most of the code and comments here are boilerplate.
140 // Start from the bottom of the block and work up, examining the
141 // terminator instructions.
142 MachineBasicBlock::iterator I = MBB.end();
143 while (I != MBB.begin()) {
145 if (I->isDebugValue())
148 // Working from the bottom, when we see a non-terminator instruction, we're
150 if (!isUnpredicatedTerminator(I))
153 // A terminator that isn't a branch can't easily be handled by this
158 // Can't handle indirect branches.
159 SystemZII::Branch Branch(getBranchInfo(I));
160 if (!Branch.Target->isMBB())
163 // Punt on compound branches.
164 if (Branch.Type != SystemZII::BranchNormal)
167 if (Branch.CCMask == SystemZ::CCMASK_ANY) {
168 // Handle unconditional branches.
170 TBB = Branch.Target->getMBB();
174 // If the block has any instructions after a JMP, delete them.
175 while (llvm::next(I) != MBB.end())
176 llvm::next(I)->eraseFromParent();
181 // Delete the JMP if it's equivalent to a fall-through.
182 if (MBB.isLayoutSuccessor(Branch.Target->getMBB())) {
184 I->eraseFromParent();
189 // TBB is used to indicate the unconditinal destination.
190 TBB = Branch.Target->getMBB();
194 // Working from the bottom, handle the first conditional branch.
196 // FIXME: add X86-style branch swap
198 TBB = Branch.Target->getMBB();
199 Cond.push_back(MachineOperand::CreateImm(Branch.CCMask));
203 // Handle subsequent conditional branches.
204 assert(Cond.size() == 1);
207 // Only handle the case where all conditional branches branch to the same
209 if (TBB != Branch.Target->getMBB())
212 // If the conditions are the same, we can leave them alone.
213 unsigned OldCond = Cond[0].getImm();
214 if (OldCond == Branch.CCMask)
217 // FIXME: Try combining conditions like X86 does. Should be easy on Z!
223 unsigned SystemZInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
224 // Most of the code and comments here are boilerplate.
225 MachineBasicBlock::iterator I = MBB.end();
228 while (I != MBB.begin()) {
230 if (I->isDebugValue())
234 if (!getBranchInfo(I).Target->isMBB())
236 // Remove the branch.
237 I->eraseFromParent();
246 SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
247 MachineBasicBlock *FBB,
248 const SmallVectorImpl<MachineOperand> &Cond,
250 // In this function we output 32-bit branches, which should always
251 // have enough range. They can be shortened and relaxed by later code
252 // in the pipeline, if desired.
254 // Shouldn't be a fall through.
255 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
256 assert((Cond.size() == 1 || Cond.size() == 0) &&
257 "SystemZ branch conditions have one component!");
260 // Unconditional branch?
261 assert(!FBB && "Unconditional branch with multiple successors!");
262 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(TBB);
266 // Conditional branch.
268 unsigned CC = Cond[0].getImm();
269 BuildMI(&MBB, DL, get(SystemZ::BRC)).addImm(CC).addMBB(TBB);
273 // Two-way Conditional branch. Insert the second branch.
274 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(FBB);
280 // If Opcode is a move that has a conditional variant, return that variant,
281 // otherwise return 0.
282 static unsigned getConditionalMove(unsigned Opcode) {
284 case SystemZ::LR: return SystemZ::LOCR;
285 case SystemZ::LGR: return SystemZ::LOCGR;
290 bool SystemZInstrInfo::isPredicable(MachineInstr *MI) const {
291 unsigned Opcode = MI->getOpcode();
292 if (TM.getSubtargetImpl()->hasLoadStoreOnCond() &&
293 getConditionalMove(Opcode))
298 bool SystemZInstrInfo::
299 isProfitableToIfCvt(MachineBasicBlock &MBB,
300 unsigned NumCycles, unsigned ExtraPredCycles,
301 const BranchProbability &Probability) const {
302 // For now only convert single instructions.
303 return NumCycles == 1;
306 bool SystemZInstrInfo::
307 isProfitableToIfCvt(MachineBasicBlock &TMBB,
308 unsigned NumCyclesT, unsigned ExtraPredCyclesT,
309 MachineBasicBlock &FMBB,
310 unsigned NumCyclesF, unsigned ExtraPredCyclesF,
311 const BranchProbability &Probability) const {
312 // For now avoid converting mutually-exclusive cases.
316 bool SystemZInstrInfo::
317 PredicateInstruction(MachineInstr *MI,
318 const SmallVectorImpl<MachineOperand> &Pred) const {
319 unsigned CCMask = Pred[0].getImm();
320 assert(CCMask > 0 && CCMask < 15 && "Invalid predicate");
321 unsigned Opcode = MI->getOpcode();
322 if (TM.getSubtargetImpl()->hasLoadStoreOnCond()) {
323 if (unsigned CondOpcode = getConditionalMove(Opcode)) {
324 MI->setDesc(get(CondOpcode));
325 MachineInstrBuilder(*MI->getParent()->getParent(), MI).addImm(CCMask);
333 SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
334 MachineBasicBlock::iterator MBBI, DebugLoc DL,
335 unsigned DestReg, unsigned SrcReg,
336 bool KillSrc) const {
337 // Split 128-bit GPR moves into two 64-bit moves. This handles ADDR128 too.
338 if (SystemZ::GR128BitRegClass.contains(DestReg, SrcReg)) {
339 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_high),
340 RI.getSubReg(SrcReg, SystemZ::subreg_high), KillSrc);
341 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_low),
342 RI.getSubReg(SrcReg, SystemZ::subreg_low), KillSrc);
346 // Everything else needs only one instruction.
348 if (SystemZ::GR32BitRegClass.contains(DestReg, SrcReg))
349 Opcode = SystemZ::LR;
350 else if (SystemZ::GR64BitRegClass.contains(DestReg, SrcReg))
351 Opcode = SystemZ::LGR;
352 else if (SystemZ::FP32BitRegClass.contains(DestReg, SrcReg))
353 Opcode = SystemZ::LER;
354 else if (SystemZ::FP64BitRegClass.contains(DestReg, SrcReg))
355 Opcode = SystemZ::LDR;
356 else if (SystemZ::FP128BitRegClass.contains(DestReg, SrcReg))
357 Opcode = SystemZ::LXR;
359 llvm_unreachable("Impossible reg-to-reg copy");
361 BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
362 .addReg(SrcReg, getKillRegState(KillSrc));
366 SystemZInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
367 MachineBasicBlock::iterator MBBI,
368 unsigned SrcReg, bool isKill,
370 const TargetRegisterClass *RC,
371 const TargetRegisterInfo *TRI) const {
372 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
374 // Callers may expect a single instruction, so keep 128-bit moves
375 // together for now and lower them after register allocation.
376 unsigned LoadOpcode, StoreOpcode;
377 getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
378 addFrameReference(BuildMI(MBB, MBBI, DL, get(StoreOpcode))
379 .addReg(SrcReg, getKillRegState(isKill)), FrameIdx);
383 SystemZInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
384 MachineBasicBlock::iterator MBBI,
385 unsigned DestReg, int FrameIdx,
386 const TargetRegisterClass *RC,
387 const TargetRegisterInfo *TRI) const {
388 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
390 // Callers may expect a single instruction, so keep 128-bit moves
391 // together for now and lower them after register allocation.
392 unsigned LoadOpcode, StoreOpcode;
393 getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
394 addFrameReference(BuildMI(MBB, MBBI, DL, get(LoadOpcode), DestReg),
398 // Return true if MI is a simple load or store with a 12-bit displacement
399 // and no index. Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
400 static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag) {
401 const MCInstrDesc &MCID = MI->getDesc();
402 return ((MCID.TSFlags & Flag) &&
403 isUInt<12>(MI->getOperand(2).getImm()) &&
404 MI->getOperand(3).getReg() == 0);
408 SystemZInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
409 MachineBasicBlock::iterator &MBBI,
410 LiveVariables *LV) const {
411 MachineInstr *MI = MBBI;
412 MachineBasicBlock *MBB = MI->getParent();
414 unsigned Opcode = MI->getOpcode();
415 unsigned NumOps = MI->getNumOperands();
417 // Try to convert something like SLL into SLLK, if supported.
418 // We prefer to keep the two-operand form where possible both
419 // because it tends to be shorter and because some instructions
420 // have memory forms that can be used during spilling.
421 if (TM.getSubtargetImpl()->hasDistinctOps()) {
422 int ThreeOperandOpcode = SystemZ::getThreeOperandOpcode(Opcode);
423 if (ThreeOperandOpcode >= 0) {
424 unsigned DestReg = MI->getOperand(0).getReg();
425 MachineOperand &Src = MI->getOperand(1);
426 MachineInstrBuilder MIB = BuildMI(*MBB, MBBI, MI->getDebugLoc(),
427 get(ThreeOperandOpcode), DestReg);
428 // Keep the kill state, but drop the tied flag.
429 MIB.addReg(Src.getReg(), getKillRegState(Src.isKill()));
430 // Keep the remaining operands as-is.
431 for (unsigned I = 2; I < NumOps; ++I)
432 MIB.addOperand(MI->getOperand(I));
433 MachineInstr *NewMI = MIB;
435 // Transfer killing information to the new instruction.
437 for (unsigned I = 1; I < NumOps; ++I) {
438 MachineOperand &Op = MI->getOperand(I);
439 if (Op.isReg() && Op.isKill())
440 LV->replaceKillInstruction(Op.getReg(), MI, NewMI);
450 SystemZInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
452 const SmallVectorImpl<unsigned> &Ops,
453 int FrameIndex) const {
454 const MachineFrameInfo *MFI = MF.getFrameInfo();
455 unsigned Size = MFI->getObjectSize(FrameIndex);
457 // Eary exit for cases we don't care about
461 unsigned OpNum = Ops[0];
462 assert(Size == MF.getRegInfo()
463 .getRegClass(MI->getOperand(OpNum).getReg())->getSize() &&
464 "Invalid size combination");
466 unsigned Opcode = MI->getOpcode();
467 if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {
468 bool Op0IsGPR = (Opcode == SystemZ::LGDR);
469 bool Op1IsGPR = (Opcode == SystemZ::LDGR);
470 // If we're spilling the destination of an LDGR or LGDR, store the
471 // source register instead.
473 unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD;
474 return BuildMI(MF, MI->getDebugLoc(), get(StoreOpcode))
475 .addOperand(MI->getOperand(1)).addFrameIndex(FrameIndex)
476 .addImm(0).addReg(0);
478 // If we're spilling the source of an LDGR or LGDR, load the
479 // destination register instead.
481 unsigned LoadOpcode = Op0IsGPR ? SystemZ::LG : SystemZ::LD;
482 unsigned Dest = MI->getOperand(0).getReg();
483 return BuildMI(MF, MI->getDebugLoc(), get(LoadOpcode), Dest)
484 .addFrameIndex(FrameIndex).addImm(0).addReg(0);
488 // Look for cases where the source of a simple store or the destination
489 // of a simple load is being spilled. Try to use MVC instead.
491 // Although MVC is in practice a fast choice in these cases, it is still
492 // logically a bytewise copy. This means that we cannot use it if the
493 // load or store is volatile. It also means that the transformation is
494 // not valid in cases where the two memories partially overlap; however,
495 // that is not a problem here, because we know that one of the memories
496 // is a full frame index.
497 if (OpNum == 0 && MI->hasOneMemOperand()) {
498 MachineMemOperand *MMO = *MI->memoperands_begin();
499 if (MMO->getSize() == Size && !MMO->isVolatile()) {
500 // Handle conversion of loads.
501 if (isSimpleBD12Move(MI, SystemZII::SimpleBDXLoad)) {
502 return BuildMI(MF, MI->getDebugLoc(), get(SystemZ::MVC))
503 .addFrameIndex(FrameIndex).addImm(0).addImm(Size)
504 .addOperand(MI->getOperand(1)).addImm(MI->getOperand(2).getImm())
507 // Handle conversion of stores.
508 if (isSimpleBD12Move(MI, SystemZII::SimpleBDXStore)) {
509 return BuildMI(MF, MI->getDebugLoc(), get(SystemZ::MVC))
510 .addOperand(MI->getOperand(1)).addImm(MI->getOperand(2).getImm())
511 .addImm(Size).addFrameIndex(FrameIndex).addImm(0)
517 // If the spilled operand is the final one, try to change <INSN>R
519 int MemOpcode = SystemZ::getMemOpcode(Opcode);
520 if (MemOpcode >= 0) {
521 unsigned NumOps = MI->getNumExplicitOperands();
522 if (OpNum == NumOps - 1) {
523 const MCInstrDesc &MemDesc = get(MemOpcode);
524 uint64_t AccessBytes = SystemZII::getAccessSize(MemDesc.TSFlags);
525 assert(AccessBytes != 0 && "Size of access should be known");
526 assert(AccessBytes <= Size && "Access outside the frame index");
527 uint64_t Offset = Size - AccessBytes;
528 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(MemOpcode));
529 for (unsigned I = 0; I < OpNum; ++I)
530 MIB.addOperand(MI->getOperand(I));
531 MIB.addFrameIndex(FrameIndex).addImm(Offset);
532 if (MemDesc.TSFlags & SystemZII::HasIndex)
542 SystemZInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr* MI,
543 const SmallVectorImpl<unsigned> &Ops,
544 MachineInstr* LoadMI) const {
549 SystemZInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
550 switch (MI->getOpcode()) {
552 splitMove(MI, SystemZ::LG);
556 splitMove(MI, SystemZ::STG);
560 splitMove(MI, SystemZ::LD);
564 splitMove(MI, SystemZ::STD);
567 case SystemZ::ADJDYNALLOC:
568 splitAdjDynAlloc(MI);
576 bool SystemZInstrInfo::
577 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
578 assert(Cond.size() == 1 && "Invalid branch condition!");
579 Cond[0].setImm(Cond[0].getImm() ^ SystemZ::CCMASK_ANY);
583 uint64_t SystemZInstrInfo::getInstSizeInBytes(const MachineInstr *MI) const {
584 if (MI->getOpcode() == TargetOpcode::INLINEASM) {
585 const MachineFunction *MF = MI->getParent()->getParent();
586 const char *AsmStr = MI->getOperand(0).getSymbolName();
587 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
589 return MI->getDesc().getSize();
593 SystemZInstrInfo::getBranchInfo(const MachineInstr *MI) const {
594 switch (MI->getOpcode()) {
598 return SystemZII::Branch(SystemZII::BranchNormal, SystemZ::CCMASK_ANY,
603 return SystemZII::Branch(SystemZII::BranchNormal,
604 MI->getOperand(0).getImm(), &MI->getOperand(1));
608 return SystemZII::Branch(SystemZII::BranchC, MI->getOperand(2).getImm(),
613 return SystemZII::Branch(SystemZII::BranchCG, MI->getOperand(2).getImm(),
617 llvm_unreachable("Unrecognized branch opcode");
621 void SystemZInstrInfo::getLoadStoreOpcodes(const TargetRegisterClass *RC,
622 unsigned &LoadOpcode,
623 unsigned &StoreOpcode) const {
624 if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) {
625 LoadOpcode = SystemZ::L;
626 StoreOpcode = SystemZ::ST32;
627 } else if (RC == &SystemZ::GR64BitRegClass ||
628 RC == &SystemZ::ADDR64BitRegClass) {
629 LoadOpcode = SystemZ::LG;
630 StoreOpcode = SystemZ::STG;
631 } else if (RC == &SystemZ::GR128BitRegClass ||
632 RC == &SystemZ::ADDR128BitRegClass) {
633 LoadOpcode = SystemZ::L128;
634 StoreOpcode = SystemZ::ST128;
635 } else if (RC == &SystemZ::FP32BitRegClass) {
636 LoadOpcode = SystemZ::LE;
637 StoreOpcode = SystemZ::STE;
638 } else if (RC == &SystemZ::FP64BitRegClass) {
639 LoadOpcode = SystemZ::LD;
640 StoreOpcode = SystemZ::STD;
641 } else if (RC == &SystemZ::FP128BitRegClass) {
642 LoadOpcode = SystemZ::LX;
643 StoreOpcode = SystemZ::STX;
645 llvm_unreachable("Unsupported regclass to load or store");
648 unsigned SystemZInstrInfo::getOpcodeForOffset(unsigned Opcode,
649 int64_t Offset) const {
650 const MCInstrDesc &MCID = get(Opcode);
651 int64_t Offset2 = (MCID.TSFlags & SystemZII::Is128Bit ? Offset + 8 : Offset);
652 if (isUInt<12>(Offset) && isUInt<12>(Offset2)) {
653 // Get the instruction to use for unsigned 12-bit displacements.
654 int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
655 if (Disp12Opcode >= 0)
658 // All address-related instructions can use unsigned 12-bit
662 if (isInt<20>(Offset) && isInt<20>(Offset2)) {
663 // Get the instruction to use for signed 20-bit displacements.
664 int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
665 if (Disp20Opcode >= 0)
668 // Check whether Opcode allows signed 20-bit displacements.
669 if (MCID.TSFlags & SystemZII::Has20BitOffset)
675 unsigned SystemZInstrInfo::getCompareAndBranch(unsigned Opcode,
676 const MachineInstr *MI) const {
681 return SystemZ::CGRJ;
683 return MI && isInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CIJ : 0;
685 return MI && isInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CGIJ : 0;
691 void SystemZInstrInfo::loadImmediate(MachineBasicBlock &MBB,
692 MachineBasicBlock::iterator MBBI,
693 unsigned Reg, uint64_t Value) const {
694 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
696 if (isInt<16>(Value))
697 Opcode = SystemZ::LGHI;
698 else if (SystemZ::isImmLL(Value))
699 Opcode = SystemZ::LLILL;
700 else if (SystemZ::isImmLH(Value)) {
701 Opcode = SystemZ::LLILH;
704 assert(isInt<32>(Value) && "Huge values not handled yet");
705 Opcode = SystemZ::LGFI;
707 BuildMI(MBB, MBBI, DL, get(Opcode), Reg).addImm(Value);