1 //===-- SystemZInstrInfo.h - SystemZ instruction information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SystemZ implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_SYSTEMZINSTRINFO_H
15 #define LLVM_TARGET_SYSTEMZINSTRINFO_H
18 #include "SystemZRegisterInfo.h"
19 #include "llvm/Target/TargetInstrInfo.h"
21 #define GET_INSTRINFO_HEADER
22 #include "SystemZGenInstrInfo.inc"
26 class SystemZTargetMachine;
30 // See comments in SystemZInstrFormats.td.
31 SimpleBDXLoad = (1 << 0),
32 SimpleBDXStore = (1 << 1),
33 Has20BitOffset = (1 << 2),
36 AccessSizeMask = (31 << 5),
39 static inline unsigned getAccessSize(unsigned int Flags) {
40 return (Flags & AccessSizeMask) >> AccessSizeShift;
43 // SystemZ MachineOperand target flags.
45 // Masks out the bits for the access model.
46 MO_SYMBOL_MODIFIER = (1 << 0),
51 // Classifies a branch.
53 // An instruction that branches on the current value of CC.
56 // An instruction that peforms a 32-bit signed comparison and branches
60 // An instruction that peforms a 64-bit signed comparison and branches
64 // Information about a branch instruction.
66 // The type of the branch.
69 // CCMASK_<N> is set if the branch should be taken when CC == N.
72 // The target of the branch.
73 const MachineOperand *Target;
75 Branch(BranchType type, unsigned ccMask, const MachineOperand *target)
76 : Type(type), CCMask(ccMask), Target(target) {}
80 class SystemZInstrInfo : public SystemZGenInstrInfo {
81 const SystemZRegisterInfo RI;
83 void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
84 void splitAdjDynAlloc(MachineBasicBlock::iterator MI) const;
87 explicit SystemZInstrInfo(SystemZTargetMachine &TM);
89 // Override TargetInstrInfo.
90 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
91 int &FrameIndex) const LLVM_OVERRIDE;
92 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
93 int &FrameIndex) const LLVM_OVERRIDE;
94 virtual bool AnalyzeBranch(MachineBasicBlock &MBB,
95 MachineBasicBlock *&TBB,
96 MachineBasicBlock *&FBB,
97 SmallVectorImpl<MachineOperand> &Cond,
98 bool AllowModify) const LLVM_OVERRIDE;
99 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const LLVM_OVERRIDE;
100 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
101 MachineBasicBlock *FBB,
102 const SmallVectorImpl<MachineOperand> &Cond,
103 DebugLoc DL) const LLVM_OVERRIDE;
104 virtual void copyPhysReg(MachineBasicBlock &MBB,
105 MachineBasicBlock::iterator MBBI, DebugLoc DL,
106 unsigned DestReg, unsigned SrcReg,
107 bool KillSrc) const LLVM_OVERRIDE;
109 storeRegToStackSlot(MachineBasicBlock &MBB,
110 MachineBasicBlock::iterator MBBI,
111 unsigned SrcReg, bool isKill, int FrameIndex,
112 const TargetRegisterClass *RC,
113 const TargetRegisterInfo *TRI) const LLVM_OVERRIDE;
115 loadRegFromStackSlot(MachineBasicBlock &MBB,
116 MachineBasicBlock::iterator MBBI,
117 unsigned DestReg, int FrameIdx,
118 const TargetRegisterClass *RC,
119 const TargetRegisterInfo *TRI) const LLVM_OVERRIDE;
120 virtual MachineInstr *
121 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
122 const SmallVectorImpl<unsigned> &Ops,
123 int FrameIndex) const;
124 virtual MachineInstr *
125 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr* MI,
126 const SmallVectorImpl<unsigned> &Ops,
127 MachineInstr* LoadMI) const;
129 expandPostRAPseudo(MachineBasicBlock::iterator MBBI) const LLVM_OVERRIDE;
131 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
134 // Return the SystemZRegisterInfo, which this class owns.
135 const SystemZRegisterInfo &getRegisterInfo() const { return RI; }
137 // Return the size in bytes of MI.
138 uint64_t getInstSizeInBytes(const MachineInstr *MI) const;
140 // Return true if MI is a conditional or unconditional branch.
141 // When returning true, set Cond to the mask of condition-code
142 // values on which the instruction will branch, and set Target
143 // to the operand that contains the branch target. This target
144 // can be a register or a basic block.
145 SystemZII::Branch getBranchInfo(const MachineInstr *MI) const;
147 // Get the load and store opcodes for a given register class.
148 void getLoadStoreOpcodes(const TargetRegisterClass *RC,
149 unsigned &LoadOpcode, unsigned &StoreOpcode) const;
151 // Opcode is the opcode of an instruction that has an address operand,
152 // and the caller wants to perform that instruction's operation on an
153 // address that has displacement Offset. Return the opcode of a suitable
154 // instruction (which might be Opcode itself) or 0 if no such instruction
156 unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const;
158 // If Opcode is a COMPARE opcode for which an associated COMPARE AND
159 // BRANCH exists, return the opcode for the latter, otherwise return 0.
160 // MI, if nonnull, is the compare instruction.
161 unsigned getCompareAndBranch(unsigned Opcode,
162 const MachineInstr *MI = 0) const;
164 // Emit code before MBBI in MI to move immediate value Value into
165 // physical register Reg.
166 void loadImmediate(MachineBasicBlock &MBB,
167 MachineBasicBlock::iterator MBBI,
168 unsigned Reg, uint64_t Value) const;
170 } // end namespace llvm