1 //===-- SystemZInstrInfo.h - SystemZ instruction information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SystemZ implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_SYSTEMZINSTRINFO_H
15 #define LLVM_TARGET_SYSTEMZINSTRINFO_H
18 #include "SystemZRegisterInfo.h"
19 #include "llvm/Target/TargetInstrInfo.h"
21 #define GET_INSTRINFO_HEADER
22 #include "SystemZGenInstrInfo.inc"
26 class SystemZTargetMachine;
30 // See comments in SystemZInstrFormats.td.
31 SimpleBDXLoad = (1 << 0),
32 SimpleBDXStore = (1 << 1),
33 Has20BitOffset = (1 << 2),
36 AccessSizeMask = (31 << 5),
38 CCValuesMask = (15 << 10),
40 CompareZeroCCMaskMask = (15 << 14),
41 CompareZeroCCMaskShift = 14,
42 CCMaskFirst = (1 << 18),
43 CCMaskLast = (1 << 19),
46 static inline unsigned getAccessSize(unsigned int Flags) {
47 return (Flags & AccessSizeMask) >> AccessSizeShift;
49 static inline unsigned getCCValues(unsigned int Flags) {
50 return (Flags & CCValuesMask) >> CCValuesShift;
52 static inline unsigned getCompareZeroCCMask(unsigned int Flags) {
53 return (Flags & CompareZeroCCMaskMask) >> CompareZeroCCMaskShift;
56 // SystemZ MachineOperand target flags.
58 // Masks out the bits for the access model.
59 MO_SYMBOL_MODIFIER = (1 << 0),
64 // Classifies a branch.
66 // An instruction that branches on the current value of CC.
69 // An instruction that peforms a 32-bit signed comparison and branches
73 // An instruction that peforms a 64-bit signed comparison and branches
77 // An instruction that decrements a 32-bit register and branches if
78 // the result is nonzero.
81 // An instruction that decrements a 64-bit register and branches if
82 // the result is nonzero.
85 // Information about a branch instruction.
87 // The type of the branch.
90 // CCMASK_<N> is set if CC might be equal to N.
93 // CCMASK_<N> is set if the branch should be taken when CC == N.
96 // The target of the branch.
97 const MachineOperand *Target;
99 Branch(BranchType type, unsigned ccValid, unsigned ccMask,
100 const MachineOperand *target)
101 : Type(type), CCValid(ccValid), CCMask(ccMask), Target(target) {}
105 class SystemZInstrInfo : public SystemZGenInstrInfo {
106 const SystemZRegisterInfo RI;
107 SystemZTargetMachine &TM;
109 void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
110 void splitAdjDynAlloc(MachineBasicBlock::iterator MI) const;
113 explicit SystemZInstrInfo(SystemZTargetMachine &TM);
115 // Override TargetInstrInfo.
116 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
117 int &FrameIndex) const LLVM_OVERRIDE;
118 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
119 int &FrameIndex) const LLVM_OVERRIDE;
120 virtual bool isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex,
121 int &SrcFrameIndex) const LLVM_OVERRIDE;
122 virtual bool AnalyzeBranch(MachineBasicBlock &MBB,
123 MachineBasicBlock *&TBB,
124 MachineBasicBlock *&FBB,
125 SmallVectorImpl<MachineOperand> &Cond,
126 bool AllowModify) const LLVM_OVERRIDE;
127 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const LLVM_OVERRIDE;
128 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
129 MachineBasicBlock *FBB,
130 const SmallVectorImpl<MachineOperand> &Cond,
131 DebugLoc DL) const LLVM_OVERRIDE;
132 virtual bool isPredicable(MachineInstr *MI) const LLVM_OVERRIDE;
133 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
134 unsigned ExtraPredCycles,
135 const BranchProbability &Probability) const
137 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
139 unsigned ExtraPredCyclesT,
140 MachineBasicBlock &FMBB,
142 unsigned ExtraPredCyclesF,
143 const BranchProbability &Probability) const
146 PredicateInstruction(MachineInstr *MI,
147 const SmallVectorImpl<MachineOperand> &Pred) const
149 virtual void copyPhysReg(MachineBasicBlock &MBB,
150 MachineBasicBlock::iterator MBBI, DebugLoc DL,
151 unsigned DestReg, unsigned SrcReg,
152 bool KillSrc) const LLVM_OVERRIDE;
154 storeRegToStackSlot(MachineBasicBlock &MBB,
155 MachineBasicBlock::iterator MBBI,
156 unsigned SrcReg, bool isKill, int FrameIndex,
157 const TargetRegisterClass *RC,
158 const TargetRegisterInfo *TRI) const LLVM_OVERRIDE;
160 loadRegFromStackSlot(MachineBasicBlock &MBB,
161 MachineBasicBlock::iterator MBBI,
162 unsigned DestReg, int FrameIdx,
163 const TargetRegisterClass *RC,
164 const TargetRegisterInfo *TRI) const LLVM_OVERRIDE;
165 virtual MachineInstr *
166 convertToThreeAddress(MachineFunction::iterator &MFI,
167 MachineBasicBlock::iterator &MBBI,
168 LiveVariables *LV) const;
169 virtual MachineInstr *
170 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
171 const SmallVectorImpl<unsigned> &Ops,
172 int FrameIndex) const;
173 virtual MachineInstr *
174 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr* MI,
175 const SmallVectorImpl<unsigned> &Ops,
176 MachineInstr* LoadMI) const;
178 expandPostRAPseudo(MachineBasicBlock::iterator MBBI) const LLVM_OVERRIDE;
180 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
183 // Return the SystemZRegisterInfo, which this class owns.
184 const SystemZRegisterInfo &getRegisterInfo() const { return RI; }
186 // Return the size in bytes of MI.
187 uint64_t getInstSizeInBytes(const MachineInstr *MI) const;
189 // Return true if MI is a conditional or unconditional branch.
190 // When returning true, set Cond to the mask of condition-code
191 // values on which the instruction will branch, and set Target
192 // to the operand that contains the branch target. This target
193 // can be a register or a basic block.
194 SystemZII::Branch getBranchInfo(const MachineInstr *MI) const;
196 // Get the load and store opcodes for a given register class.
197 void getLoadStoreOpcodes(const TargetRegisterClass *RC,
198 unsigned &LoadOpcode, unsigned &StoreOpcode) const;
200 // Opcode is the opcode of an instruction that has an address operand,
201 // and the caller wants to perform that instruction's operation on an
202 // address that has displacement Offset. Return the opcode of a suitable
203 // instruction (which might be Opcode itself) or 0 if no such instruction
205 unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const;
207 // If Opcode is a load instruction that has a LOAD AND TEST form,
208 // return the opcode for the testing form, otherwise return 0.
209 unsigned getLoadAndTest(unsigned Opcode) const;
211 // Return true if ROTATE AND ... SELECTED BITS can be used to select bits
212 // Mask of the R2 operand, given that only the low BitSize bits of Mask are
213 // significant. Set Start and End to the I3 and I4 operands if so.
214 bool isRxSBGMask(uint64_t Mask, unsigned BitSize,
215 unsigned &Start, unsigned &End) const;
217 // If Opcode is a COMPARE opcode for which an associated COMPARE AND
218 // BRANCH exists, return the opcode for the latter, otherwise return 0.
219 // MI, if nonnull, is the compare instruction.
220 unsigned getCompareAndBranch(unsigned Opcode,
221 const MachineInstr *MI = 0) const;
223 // Emit code before MBBI in MI to move immediate value Value into
224 // physical register Reg.
225 void loadImmediate(MachineBasicBlock &MBB,
226 MachineBasicBlock::iterator MBBI,
227 unsigned Reg, uint64_t Value) const;
229 } // end namespace llvm