1 //===-- SystemZInstrInfo.h - SystemZ instruction information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SystemZ implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_SYSTEMZINSTRINFO_H
15 #define LLVM_TARGET_SYSTEMZINSTRINFO_H
18 #include "SystemZRegisterInfo.h"
19 #include "llvm/Target/TargetInstrInfo.h"
21 #define GET_INSTRINFO_HEADER
22 #include "SystemZGenInstrInfo.inc"
26 class SystemZTargetMachine;
30 // See comments in SystemZInstrFormats.td.
31 SimpleBDXLoad = (1 << 0),
32 SimpleBDXStore = (1 << 1),
33 Has20BitOffset = (1 << 2),
36 AccessSizeMask = (31 << 5),
39 static inline unsigned getAccessSize(unsigned int Flags) {
40 return (Flags & AccessSizeMask) >> AccessSizeShift;
43 // SystemZ MachineOperand target flags.
45 // Masks out the bits for the access model.
46 MO_SYMBOL_MODIFIER = (1 << 0),
51 // Classifies a branch.
53 // An instruction that branches on the current value of CC.
56 // An instruction that peforms a 32-bit signed comparison and branches
60 // An instruction that peforms a 64-bit signed comparison and branches
64 // Information about a branch instruction.
66 // The type of the branch.
69 // CCMASK_<N> is set if the branch should be taken when CC == N.
72 // The target of the branch.
73 const MachineOperand *Target;
75 Branch(BranchType type, unsigned ccMask, const MachineOperand *target)
76 : Type(type), CCMask(ccMask), Target(target) {}
80 class SystemZInstrInfo : public SystemZGenInstrInfo {
81 const SystemZRegisterInfo RI;
82 SystemZTargetMachine &TM;
84 void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
85 void splitAdjDynAlloc(MachineBasicBlock::iterator MI) const;
88 explicit SystemZInstrInfo(SystemZTargetMachine &TM);
90 // Override TargetInstrInfo.
91 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
92 int &FrameIndex) const LLVM_OVERRIDE;
93 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
94 int &FrameIndex) const LLVM_OVERRIDE;
95 virtual bool isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex,
96 int &SrcFrameIndex) const LLVM_OVERRIDE;
97 virtual bool AnalyzeBranch(MachineBasicBlock &MBB,
98 MachineBasicBlock *&TBB,
99 MachineBasicBlock *&FBB,
100 SmallVectorImpl<MachineOperand> &Cond,
101 bool AllowModify) const LLVM_OVERRIDE;
102 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const LLVM_OVERRIDE;
103 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
104 MachineBasicBlock *FBB,
105 const SmallVectorImpl<MachineOperand> &Cond,
106 DebugLoc DL) const LLVM_OVERRIDE;
107 virtual bool analyzeCompare(const MachineInstr *MI,
108 unsigned &SrcReg, unsigned &SrcReg2,
109 int &Mask, int &Value) const LLVM_OVERRIDE;
110 virtual bool optimizeCompareInstr(MachineInstr *CmpInstr,
111 unsigned SrcReg, unsigned SrcReg2,
113 const MachineRegisterInfo *MRI) const
115 virtual bool isPredicable(MachineInstr *MI) const LLVM_OVERRIDE;
116 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
117 unsigned ExtraPredCycles,
118 const BranchProbability &Probability) const
120 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
122 unsigned ExtraPredCyclesT,
123 MachineBasicBlock &FMBB,
125 unsigned ExtraPredCyclesF,
126 const BranchProbability &Probability) const
129 PredicateInstruction(MachineInstr *MI,
130 const SmallVectorImpl<MachineOperand> &Pred) const
132 virtual void copyPhysReg(MachineBasicBlock &MBB,
133 MachineBasicBlock::iterator MBBI, DebugLoc DL,
134 unsigned DestReg, unsigned SrcReg,
135 bool KillSrc) const LLVM_OVERRIDE;
137 storeRegToStackSlot(MachineBasicBlock &MBB,
138 MachineBasicBlock::iterator MBBI,
139 unsigned SrcReg, bool isKill, int FrameIndex,
140 const TargetRegisterClass *RC,
141 const TargetRegisterInfo *TRI) const LLVM_OVERRIDE;
143 loadRegFromStackSlot(MachineBasicBlock &MBB,
144 MachineBasicBlock::iterator MBBI,
145 unsigned DestReg, int FrameIdx,
146 const TargetRegisterClass *RC,
147 const TargetRegisterInfo *TRI) const LLVM_OVERRIDE;
148 virtual MachineInstr *
149 convertToThreeAddress(MachineFunction::iterator &MFI,
150 MachineBasicBlock::iterator &MBBI,
151 LiveVariables *LV) const;
152 virtual MachineInstr *
153 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
154 const SmallVectorImpl<unsigned> &Ops,
155 int FrameIndex) const;
156 virtual MachineInstr *
157 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr* MI,
158 const SmallVectorImpl<unsigned> &Ops,
159 MachineInstr* LoadMI) const;
161 expandPostRAPseudo(MachineBasicBlock::iterator MBBI) const LLVM_OVERRIDE;
163 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
166 // Return the SystemZRegisterInfo, which this class owns.
167 const SystemZRegisterInfo &getRegisterInfo() const { return RI; }
169 // Return the size in bytes of MI.
170 uint64_t getInstSizeInBytes(const MachineInstr *MI) const;
172 // Return true if MI is a conditional or unconditional branch.
173 // When returning true, set Cond to the mask of condition-code
174 // values on which the instruction will branch, and set Target
175 // to the operand that contains the branch target. This target
176 // can be a register or a basic block.
177 SystemZII::Branch getBranchInfo(const MachineInstr *MI) const;
179 // Get the load and store opcodes for a given register class.
180 void getLoadStoreOpcodes(const TargetRegisterClass *RC,
181 unsigned &LoadOpcode, unsigned &StoreOpcode) const;
183 // Opcode is the opcode of an instruction that has an address operand,
184 // and the caller wants to perform that instruction's operation on an
185 // address that has displacement Offset. Return the opcode of a suitable
186 // instruction (which might be Opcode itself) or 0 if no such instruction
188 unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const;
190 // Return true if ROTATE AND ... SELECTED BITS can be used to select bits
191 // Mask of the R2 operand, given that only the low BitSize bits of Mask are
192 // significant. Set Start and End to the I3 and I4 operands if so.
193 bool isRxSBGMask(uint64_t Mask, unsigned BitSize,
194 unsigned &Start, unsigned &End) const;
196 // If Opcode is a COMPARE opcode for which an associated COMPARE AND
197 // BRANCH exists, return the opcode for the latter, otherwise return 0.
198 // MI, if nonnull, is the compare instruction.
199 unsigned getCompareAndBranch(unsigned Opcode,
200 const MachineInstr *MI = 0) const;
202 // Emit code before MBBI in MI to move immediate value Value into
203 // physical register Reg.
204 void loadImmediate(MachineBasicBlock &MBB,
205 MachineBasicBlock::iterator MBBI,
206 unsigned Reg, uint64_t Value) const;
208 } // end namespace llvm